Philips Semiconductors Product specification TrenchMOS transistor Logic level FET FEATURES PHP42N03LT, PHB42N03LT SYMBOL • ’Trench’ technology • Very low on-state resistance • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance QUICK REFERENCE DATA VDSS = 30 V d ID = 42 A RDS(ON) ≤ 26 mΩ (VGS = 5 V) g RDS(ON) ≤ 23 mΩ (VGS = 10 V) s GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP42N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB42N03LT is supplied in the SOT404 surface mounting package. PINNING SOT78 (TO220AB) PIN SOT404 DESCRIPTION tab tab 1 gate 2 drain 1 3 source tab 2 drain 1 1 23 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature - 55 30 30 ± 15 42 30 168 86 175 V V V A A A W ˚C November 1998 Tmb = 25 ˚C; VGS = 5 V Tmb = 100 ˚C; VGS = 5 V Tmb = 25 ˚C Tmb = 25 ˚C 1 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP42N03LT, PHB42N03LT THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT78 package, in free air SOT404 package, pcb mounted, minimum footprint TYP. MAX. UNIT - - 1.75 K/W - 60 50 - K/W K/W ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 0.25 mA; VGS(TO) Drain-source breakdown voltage Gate threshold voltage MIN. Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) 30 27 1 0.5 8 - 1.5 16 20 27 0.05 10 2 2.3 23 26 48 10 500 100 V V V V V mΩ mΩ mΩ S µA µA nA IGSS VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175˚C Forward transconductance VDS = 25 V; ID = 25 A Zero gate voltage drain VDS = 30 V; VGS = 0 V; current Tj = 175˚C Gate source leakage current VGS = ±5 V; VDS = 0 V Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 20 A; VDD = 24 V; VGS = 10 V - 40 7 10 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 15 V; ID = 25 A; VGS = 5 V; RG = 5 Ω Resistive load - 12 80 35 31 20 130 60 45 ns ns ns ns Ld Ld Internal drain inductance Internal drain inductance - 3.5 4.5 - nH nH Ls Internal source inductance Measured tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad - 7.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1050 270 140 - pF pF pF gfs IDSS Drain-source on-state resistance TYP. MAX. UNIT November 1998 2 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP42N03LT, PHB42N03LT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge IS ISM 120 MIN. - - 45 A - - 180 A IF = 25 A; VGS = 0 V IF = 40 A; VGS = 0 V - 0.95 1.0 1.2 - V IF = 40 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 25 V - 52 0.08 - ns µC Normalised Power Derating PD% TYP. MAX. UNIT PHP42N03LT ID, Drain current (Amps) 1000 110 100 90 80 100 ) (ON /ID DS =V tp = 10us S RD 70 100 us 60 50 40 1 ms 10 DC 30 10 ms 100 ms 20 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 1 180 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 10 VDS, Drain-source voltage (Volts) 100 Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp Normalised Current Derating ID% Tmb = 25 C 1 10 110 Zth j-mb / (K/W) 7528-30 D= 100 90 80 1 0.5 70 60 0.2 50 40 0.1 0.1 30 0.05 20 0.02 10 PD 0 0 0 20 40 60 80 100 Tmb / C 120 140 160 0.01 1E-07 180 D= T 1E-05 1E-03 t/s tp T t 1E-01 1E+01 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V November 1998 tp 3 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET 80 70 ID, Drain current (Amps) 15 V 5V 10 V PHP42N03LT, PHB42N03LT PHP45N03LT Tj = 25 C VDS = 25 V Tj = 25 C 25 60 4V 20 50 175 C 40 15 3.5 V 30 10 3V 20 5 10 0 PHP45N03LT Transconductance, gfs (S) 30 4.5 V VGS = 2.5 V 0 2 4 6 8 VDS, Drain-Source voltage (Volts) 0 10 0 Fig.5. Typical output characteristics ID = f(VDS); parameter VGS 0.06 3.5 V a 40 50 30V TrenchMOS 2 4.5 V 4V 20 30 Drain current, ID (A) Fig.8. Typical transconductance gfs = f(ID) Drain-Source on resistance, RDS(on) (Ohms) 3V 10 0.05 1.5 0.04 0.03 1 5V 0.02 10 V 0.5 VGS = 15 V 0.01 Tj = 25 C 0 0 10 20 30 40 50 ID, Drain current (Amps) PHP45N03LT 60 70 0 -100 80 Fig.6. Typical on-state resistance RDS(ON) = f(ID); parameter VGS 50 0 50 Tj / C 100 200 150 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj) PHP45N03LT Drain current, ID (A) -50 2.5 BUK959-60 VGS(TO) / V VDS = 25 V max. 40 2 30 1.5 20 1 typ. min. 10 0.5 175 C 0 0 1 Tj = 25 C 2 3 4 Gate-source voltage, VGS (V) 5 0 -100 6 Fig.7. Typical transfer characteristics. ID = f(VGS) November 1998 -50 0 50 Tj / C 100 150 200 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 4 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP42N03LT, PHB42N03LT Sub-Threshold Conduction 1E-01 15 VGS, Gate-Source voltage (Volts) PHP50N03LT VDD=24V ID=20A Tj = 25C 1E-02 10 2% 1E-03 typ 98% 1E-04 5 1E-05 0 1E-05 0 0.5 1 1.5 2 2.5 Fig.11. Sub-threshold drain current. ID = f(VGS); VDS = VGS 10000 C / pF 0 10 3 20 30 Qg, Gate charge (nC) 40 50 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) 9528-30 60 IF / A 9528-30 50 40 Ciss 1000 Tj / C = 175 25 30 20 10 Coss Crss 100 0.1 1 10 0 100 VDS / V Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); VGS = 0 V; f = 1 MHz November 1998 0 0.5 1 VSDS / V 1.5 2 Fig.14. Typical reverse diode current. IF = f(VSDS) 5 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP42N03LT, PHB42N03LT MECHANICAL DATA Dimensions in mm 4,5 max Net Mass: 2 g 10,3 max 1,3 3,7 2,8 5,9 min 15,8 max 3,0 max not tinned 3,0 13,5 min 1,3 max 1 2 3 (2x) 0,9 max (3x) 2,54 2,54 0,6 2,4 Fig.15. SOT78 (TO220AB); pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8". November 1998 6 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP42N03LT, PHB42N03LT MECHANICAL DATA Dimensions in mm 4.5 max 1.4 max 10.3 max Net Mass: 1.4 g 11 max 15.4 2.5 0.85 max (x2) 0.5 2.54 (x2) Fig.16. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.17. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". November 1998 7 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP42N03LT, PHB42N03LT DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. November 1998 8 Rev 1.400