Philips Semiconductors Product specification TrenchMOS transistor Logic level FET FEATURES PHP69N03LT, PHB69N03LT, PHD69N03LT SYMBOL • ’Trench’ technology • Very low on-state resistance • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance QUICK REFERENCE DATA VDSS = 25 V d ID = 69 A RDS(ON) ≤ 14 mΩ (VGS = 5 V) g RDS(ON) ≤ 12 mΩ (VGS = 10 V) s GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology. The combination of very low on-state resistance and low switching losses make this device the optimum choice in high speed computer motherboard d.c. to d.c. converters. The PHP69N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB69N03LT is supplied in the SOT404 surface mounting package. The PHD69N03LT is supplied in the SOT428 surface mounting package. PINNING PIN SOT78 (TO220AB) SOT404 SOT428 DESCRIPTION tab tab tab 1 gate 2 drain1 3 source 2 2 tab drain 1 1 23 1 3 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS VGSM ID Drain-source voltage Drain-gate voltage Gate-source voltage Pulsed gate-source voltage Continuous drain current Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature - 55 25 25 ± 15 ± 20 69 48 240 125 175 V V V V A A A W ˚C Tj ≤ 150˚C Tmb = 25 ˚C; VGS = 5 V Tmb = 100 ˚C; VGS = 5 V Tmb = 25 ˚C Tmb = 25 ˚C 1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages. June 1998 1 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LT, PHD69N03LT THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT78 package, in free air SOT404 and SOT428 packages, pcb mounted, minimum footprint TYP. MAX. UNIT - - 1.2 K/W - 60 50 - K/W K/W ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 0.25 mA; VGS(TO) Drain-source breakdown voltage Gate threshold voltage MIN. Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) gfs IGSS IDSS Drain-source on-state resistance VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175˚C Forward transconductance VDS = 25 V; ID = 25 A Gate source leakage current VGS = ±5 V; VDS = 0 V Zero gate voltage drain VDS = 25 V; VGS = 0 V; current Tj = 175˚C TYP. MAX. UNIT 25 22 1 0.5 12 - 1.5 8.5 11 25 10 0.05 - 2 2.3 12 14 26 100 10 500 V V V V V mΩ mΩ mΩ S nA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 20 A; VDD = 24 V; VGS = 10 V - 70 9 20 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 15 V; ID = 25 A; VGS = 10 V; RG = 5 Ω Resistive load - 10 50 80 50 20 75 120 75 ns ns ns ns Ld Ld Internal drain inductance Internal drain inductance - 3.5 4.5 - nH nH Ls Internal source inductance Measured tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad - 7.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1700 480 250 - pF pF pF June 1998 2 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LT, PHD69N03LT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge IS ISM MIN. TYP. MAX. UNIT - - 69 A - - 240 A IF = 25 A; VGS = 0 V IF = 69 A; VGS = 0 V - 0.95 1.0 1.2 - V IF = 69 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 25 V - 65 0.1 - ns µC AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS Drain-source non-repetitive ID = 25 A; VDD ≤ 15 V; unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C energy WDSS 120 Normalised Power Derating PD% 120 110 110 100 100 90 90 80 80 70 70 60 60 50 50 40 40 30 30 20 20 10 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 MAX. UNIT - 60 mJ Normalised Current Derating ID% 0 180 0 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) June 1998 MIN. 20 40 60 80 100 Tmb / C 120 140 160 180 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V 3 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LT, PHD69N03LT 7514-30 ID, Drain current (Amps) 1000 = N) S/ VD ID 0.05 RD 3V 2.8 V 3.2 V 0.04 100 us 0.03 1 ms DC 10 Tj = 25 C 2.6 V tp = 10 us S(O 100 RDS(on), Drain-Source on resistance (Ohms) 0.06 10 ms 100 ms 0.02 10 V 5V 0.01 VGS = 15 V Tmb = 25 C 1 1 10 VDS, Drain-source voltage (Volts) 0 100 Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp Zth j-mb / (K/W) 10 0 10 20 30 ID, Drain current (Amps) 40 50 PHP69N03LT Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS BUKx55-lv Drain current, ID (A) 50 PHP69N03LT VDS > RDS(ON) x ID 40 D= 1 0.5 30 0.2 0.1 0.05 0.02 0.1 0.01 20 PD 0 tp D= T tp 175 C 10 Tj = 25 C t T 0.001 1E-07 1E-05 1E-03 t/s 1E-01 0 1E+01 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 50 ID, Drain current (Amps) 15V 40 50 Tj = 25 C 5V 1 2 3 Gate-source voltage, VGS (V) 4 5 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj PHP69N03LT 10 V 0 Transconductance, gfs (S) VDS > RDS(ON) x ID 3.2 V 40 3V 30 PHP69N03LT Tj = 25 C 175 C 30 2.8 V 20 20 2.6 V 10 10 2.4 V VGS = 2.2 V 0 0 1 2 3 4 VDS, Drain-Source voltage (Volts) 0 5 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS June 1998 0 10 20 30 Drain current, ID (A) 40 50 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 4 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LT, PHD69N03LT a 30V TrenchMOS 2 9514-30 Capacitances, Ciss, Coss, Crss (pF) 10000 1.5 Ciss 1000 1 Coss 0.5 Crss 0 -100 -50 0 50 Tj / C 100 100 0.1 200 150 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj) 2.5 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz BUK959-60 VGS(TO) / V 1 10 Drain-source volage, VDS (V) VGS, Gate-Source voltage (Volts) 15 PHP69N03LT VDD=24V ID=20A Tj = 25C max. 2 typ. 10 1.5 min. 1 5 0.5 0 -100 0 -50 0 50 Tj / C 100 150 200 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 100 20 30 40 50 Qg, Gate charge (nC) 60 70 80 IF / A 9514-30 80 1E-02 2% 1E-03 typ 98% 60 40 1E-04 Tj / C = 175 25 0.5 1 VSDS / V 20 1E-05 0 1E-05 10 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Sub-Threshold Conduction 1E-01 0 0 0.5 1 1.5 2 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS June 1998 0 1.5 2 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj 5 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET 120 PHP69N03LT, PHB69N03LT, PHD69N03LT WDSS% VDD + 110 100 L 90 80 VDS - 70 VGS 60 -ID/100 50 T.U.T. 0 40 30 20 RGS 10 R 01 shunt 0 20 40 60 80 100 120 Tmb / C 140 160 180 Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb) June 1998 6 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LT, PHD69N03LT MECHANICAL DATA Dimensions in mm 4,5 max Net Mass: 2 g 10,3 max 1,3 3,7 2,8 5,9 min 15,8 max 3,0 max not tinned 3,0 13,5 min 1,3 max 1 2 3 (2x) 0,9 max (3x) 2,54 2,54 0,6 2,4 Fig.17. SOT78 (TO220AB); pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8". June 1998 7 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LT, PHD69N03LT MECHANICAL DATA Dimensions in mm 4.5 max 1.4 max 10.3 max Net Mass: 1.4 g 11 max 15.4 2.5 0.85 max (x2) 0.5 2.54 (x2) Fig.18. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.19. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". June 1998 8 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LT, PHD69N03LT MECHANICAL DATA Dimensions in mm : Net Mass: 1.4 g seating plane 6.73 max 1.1 tab 2.38 max 0.93 max 5.4 4 min 6.22 max 10.4 max 4.6 2 1 0.5 0.5 min 3 0.3 0.5 0.8 max (x2) 2.285 (x2) Fig.20. SOT428 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 7.0 7.0 2.15 1.5 2.5 4.57 Fig.21. SOT428 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". June 1998 9 Rev 1.400 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LT, PHD69N03LT DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. June 1998 10 Rev 1.400