INTEGRATED CIRCUITS DATA SHEET 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Product specification Supersedes data of 1998 Jun 04 2003 Jun 25 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 FEATURES DESCRIPTION • 8-bit serial input The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. • 8-bit serial or parallel output • Storage register with 3-state outputs • Shift register with direct clear The 74HC/HCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks. • 100 MHz (typical) shift out frequency • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. Data is shifted on the positive-going transitions of the SH_CP input. The data in each register is transferred to the storage register on a positive-going transition of the ST_CP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. APPLICATIONS • Serial-to-parallel data conversion • Remote control holding register. The shift register has a serial input (DS) and a serial standard output (Q7’) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT 74HC tPHL/tPLH propagation delay CL = 50 pF; VCC = 4.5 V SH_CP to Q7’ 19 25 ns SH_CP to Qn 20 24 ns MR to Q7’ 100 52 ns 100 57 MHz 3.5 3.5 pF 115 130 pF fmax maximum clock frequency SH_CP and ST_CP CI input capacitance CPD power dissipation capacitance per package notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. For 74HC595 the condition is VI = GND to VCC. For 74HCT595 the condition is VI = GND to VCC − 1.5 V. 2003 Jun 25 74HCT 2 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 FUNCTION TABLE See note 1. INPUT OUTPUT FUNCTION SH_CP ST_CP X OE MR DS Q7’ Qn L L X L n.c. X a LOW level on MR only affects the shift registers X ↑ L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state ↑ X L H H Q6’ n.c. logic high level shifted into shift register stage 0; contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6’) appears on the serial output (Q7’) X ↑ L H X n.c. Qn’ contents of shift register stages (internal Qn’) are transferred to the storage register and parallel output stages ↑ ↑ L H X Q6’ Qn’ contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages Note 1. H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition; Z = high-impedance OFF-state; n.c. = no change; X = don’t care. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74HC595N −40 to +125 °C 16 DIP16 plastic SOT38-4 74HCT595N −40 to +125 °C 16 DIP16 plastic SOT38-4 74HC595D −40 to +125 °C 16 SO16 plastic SOT109-1 74HCT595D −40 to +125 °C 16 SO16 plastic SOT109-1 74HC595DB −40 to +125 °C 16 SSOP16 plastic SOT338-1 74HCT595DB −40 to +125 °C 16 SSOP16 plastic SOT338-1 74HC595PW −40 to +125 °C 16 TSSOP16 plastic SOT403-1 74HCT595PW −40 to +125 °C 16 TSSOP16 plastic SOT403-1 74HC595BQ −40 to +125 °C 16 DHVQFN16 plastic SOT763-1 74HCT595BQ −40 to +125 °C 16 DHVQFN16 plastic SOT763-1 2003 Jun 25 3 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 PINNING PIN SYMBOL DESCRIPTION 1 Q1 parallel data output 2 Q2 parallel data output 3 Q3 parallel data output 4 Q4 parallel data output 5 Q5 parallel data output 6 Q6 parallel data output 7 Q7 parallel data output 8 GND ground (0 V) 9 Q7’ serial data output 10 MR master reset (active LOW) 11 SH_CP shift register clock input 12 ST_CP storage register clock input 13 OE output enable (active LOW) 14 DS serial data input 15 Q0 parallel data output 16 VCC positive supply voltage handbook, halfpage handbook, halfpage 1 16 VCC Q2 2 15 Q0 Q3 3 14 DS Q4 4 Q1 VCC 1 16 Q2 2 15 Q0 Q3 3 14 DS 13 OE Q4 4 13 OE Q5 5 12 ST_CP Q6 6 11 SH_CP Q7 7 10 MR GND(1) 595 Q5 5 12 ST_CP Q6 6 11 SH_CP Q7 7 10 MR GND 8 Q1 9 Q7' MLA001 Top view 8 9 GND Q7' MBL893 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration DIP16, SO16 and (T)SSOP16. 2003 Jun 25 Fig.2 Pin configuration DHVQFN16. 4 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state handbook, halfpage 11 74HC595; 74HCT595 handbook, halfpage 13 12 Q7' Q0 Q1 Q2 14 Q3 DS Q4 Q5 Q6 Q7 MR 10 EN3 OE SH_CP ST_CP ST_CP 9 MR 15 SH_CP 12 C2 10 R 11 1 2 DS 14 1D 2D 3 15 1 3 2 4 3 5 4 6 5 7 6 7 OE 9 13 MLA002 MSA698 Fig.3 Logic symbol. Fig.4 IEC logic symbol. handbook, full pagewidth 14 DS 11 SH_CP 10 12 13 8-STAGE SHIFT REGISTER MR ST_CP OE Q7' 9 Q0 15 Q1 1 8-BIT STORAGE REGISTER 3-STATE OUTPUTS Q2 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 7 MLA003 Fig.5 Functional diagram. 2003 Jun 25 SRG8 C1/ 5 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7' Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state handbook, full pagewidth DS STAGE 0 D 74HC595; 74HCT595 STAGES 1 to 6 Q D STAGE 7 Q D FF0 Q7' Q FF7 CP CP R R SH_CP MR D Q D Q LATCH LATCH CP CP ST_CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Fig.6 Logic diagram. 2003 Jun 25 6 Q7 MLA010 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 handbook, full pagewidth SH_CP DS ST_CP MR OE Q0 high-impedance OFF-state Q1 Q6 Q7 Q7' MLA005-1 Fig.6 Timing diagram. 2003 Jun 25 7 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 RECOMMENDED OPERATING CONDITIONS 74HC SYMBOL PARAMETER 74HCT CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 − VCC 0 − VCC V VO output voltage 0 − VCC 0 − VCC V Tamb ambient temperature −40 − +125 −40 − +125 °C tr, tf input rise and fall time VCC = 2.0 V − − 1000 − − − ns VCC = 4.5 V − 6.0 500 − 6.0 500 ns VCC = 6.0 V − − 400 − − − ns LIMITED VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT −0.5 +7.0 V VI < −0.5 V to VI > VCC + 0.5 V − ±20 mA output diode current VO < −0.5 V to VO > VCC + 0.5 V − ±20 mA output source or sink current VO = −0.5 V to VCC + 0.5 V Q7’ standard output − ±25 mA Qn bus driver outputs − ±35 mA VCC supply voltage IIK input diode current IOK IO ICC, IGND VCC or GND current − ±70 mA Tstg storage temperature −65 +150 °C Ptot power dissipation − 500 mW Tamb = −40 to +125 °C; note 1 Note 1. For DIP16 packages: above 70 °C derate linearly with 12 mW/K. For SO16 packages: above 70 °C derate linearly with 8 mW/K. For SSOP16 packages: above 60 °C derate linearly with 5.5 mW/K. For TSSOP16 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 °C derate linearly with 4.5 mW/K. 2003 Jun 25 8 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 DC CHARACTERISTICS Type 74HC At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = −40 to +85 °C; note 1 VIH VIL VOH 1.2 − V 3.15 2.4 − V 4.2 3.2 − V 2.0 − 0.8 0.5 V 4.5 − 2.1 1.35 V 6.0 − 2.8 1.8 V 2.0 1.9 2.0 − V 4.5 4.4 4.5 − V 6.0 5.9 6.0 − V IO = −4.0 mA 4.5 3.84 4.32 − V IO = −5.2 mA 6.0 5.34 5.81 − V IO = −6.0 mA 4.5 3.84 4.32 − V IO = −7.8 mA 6.0 5.34 5.81 − V 2.0 − 0 0.1 V 4.5 − 0 0.1 V 6.0 − 0 0.1 V IO = 4.0 mA 4.5 − 0.15 0.33 V IO = 5.2 mA 6.0 − 0.16 0.33 V 4.5 − 0.16 0.33 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 2.0 1.5 4.5 6.0 VI = VIH or VIL all outputs IO = −20 µA Q7’ standard output Qn bus driver outputs VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 µA Q7’ standard output Qn bus driver outputs IO = 6.0 mA IO = 7.8 mA 6.0 − 0.16 0.33 V ILI input leakage current VI = VCC or GND 6.0 − − ±1.0 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = VCC or GND 6.0 − − ±5.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 6.0 − − 80 µA 2003 Jun 25 9 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +125 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 2.0 1.5 − − V 4.5 3.15 − − V 6.0 4.2 − − V 2.0 − − 0.5 V 4.5 − − 1.35 V 6.0 − − 1.8 V VI = VIH or VIL all outputs IO = −20 µA 2.0 1.9 − − V 4.5 4.4 − − V 6.0 5.9 − − V IO = −4.0 mA 4.5 3.7 − − V IO = −5.2 mA 6.0 5.2 − − V IO = −6.0 mA 4.5 3.7 − − V IO = −7.8 mA 6.0 5.2 − − V 4.5 − − 0.1 V 4.5 − − 0.4 V 4.5 − − 0.4 V Q7’ standard output Qn bus driver outputs VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 µA Q7’ standard output IO = 4.0 mA Qn bus driver outputs IO = 6.0 mA ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = VCC or GND 5.5 − − ±10.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 160 µA Note 1. All typical values are measured at Tamb = 25 °C. 2003 Jun 25 10 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 Type 74HCT At recommended operating conditions; voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF. TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = −40 to +85 °C; note 1 VIH HIGH-level input voltage 4.5 to 5.5 2.0 1.6 − V VIL LOW-level input voltage 4.5 to 5.5 − 1.2 0.8 V VOH HIGH-level output voltage 4.5 4.4 4.5 − V 4.5 3.84 4.32 − V 4.5 3.7 4.32 − V 4.5 − 0 0.33 V 4.5 − 0.15 0.33 V 4.5 − 0.16 0.33 V VI = VIH or VIL all outputs IO = −20 µA Q7’ standard output IO = −4.0 mA Qn bus driver outputs IO = −6.0 mA VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 µA Q7’ standard output IO = 4.0 mA Qn bus driver outputs IO = 6.0 mA ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = VCC or GND 5.5 − − ±5.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 80 µA ∆ICC additional supply current per input VI = VCC − 2.1 V; IO = 0; note 2 4.5 to 5.5 − 100 450 µA 2003 Jun 25 11 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = −40 to +125 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage 4.5 4.4 − − V 4.5 3.7 − − V 4.5 3.7 − − V 4.5 − − 0.1 V 4.5 − − 0.4 V IO = 6.0 mA 4.5 − − 0.4 V VI = VIH or VIL all outputs IO = −20 µA Q7’ standard output IO = −4.0 mA Qn bus driver outputs IO = −6.0 mA VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 µA Q7’ standard output IO = 4.0 mA Qn bus driver outputs ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = VCC or GND 5.5 − − ±10.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 160 µA ∆ICC additional supply current per input VI = VCC − 2.1 V; IO = 0; note 2 4.5 to 5.5 − − 490 µA Notes 1. All typical values are measured at Tamb = 25 °C. 2. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here. To determine ∆ICC per input, multiply this value by the unit load coefficient per input pin: a. pin DS: 0.25 b. pins MR, SH_CP, ST_CP and OE: 1.50. 2003 Jun 25 12 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 AC CHARACTERISTICS Family 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = 25 °C tPHL/tPLH tPHL tPZH/tPZL tPHZ/tPLZ tW propagation delay SH_CP to Q7’ see Fig.7 propagation delay ST_CP to Qn see Fig.8 propagation delay MR to Q7’ see Fig.10 3-state output enable time OE to Qn see Fig.11 3-state output disable time OE to Qn see Fig.11 shift clock pulse width HIGH or LOW storage clock pulse width HIGH or LOW master reset pulse width LOW tsu set-up time DS to SH_CP set-up time SH_CP to ST_CP th 2003 Jun 25 hold time DS to SH_CP see Fig.7 see Fig.8 see Fig.10 see Fig.9 see Fig.8 see Fig.9 13 2.0 − 52 160 ns 4.5 − 19 32 ns 6.0 − 15 27 ns 2.0 − 55 175 ns 4.5 − 20 35 ns 6.0 − 16 30 ns 2.0 − 47 175 ns 4.5 − 17 35 ns 6.0 − 14 30 ns 2.0 − 47 150 ns 4.5 − 17 30 ns 6.0 − 14 26 ns 2.0 − 41 150 ns 4.5 − 15 30 ns 6.0 − 12 26 ns 2.0 75 17 − ns 4.5 15 6 − ns 6.0 13 5 − ns 2.0 75 11 − ns 4.5 15 4 − ns 6.0 13 3 − ns 2.0 75 17 − ns 4.5 15 6.0 − ns 6.0 13 5.0 − ns 2.0 50 11 − ns 4.5 10 4.0 − ns 6.0 9.0 3.0 − ns 2.0 75 22 − ns 4.5 15 8 − ns 6.0 13 7 − ns 2.0 +3 −6 − ns 4.5 +3 −2 − ns 6.0 +3 −2 − ns Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS trem fmax removal time MR to SH_CP see Fig.10 maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 TYP. MAX. UNIT VCC (V) 2.0 +50 −19 − ns 4.5 +10 −7 − ns 6.0 +9 −6 − ns 2.0 9 30 − MHz 4.5 30 91 − MHz 6.0 35 108 − MHz 2.0 − − 200 ns 4.5 − − 40 ns Tamb = −40 to +85 °C tPHL/tPLH tPHL tPZH/tPZL tPHZ/tPLZ tW propagation delay SH_CP to Q7’ see Fig.7 propagation delay ST_CP to An see Fig.8 propagation delay MR to Q7’ see Fig.10 3-state output enable time OE to Qn 3-state output disable time OE to Qn shift clock pulse width HIGH or LOW storage clock pulse width HIGH or LOW master reset pulse width LOW tsu set-up time DS to SH_CP set-up time SH_CP to ST_CP 2003 Jun 25 see Fig.11 see Fig.11 see Fig.7 see Fig.8 see Fig.10 see Fig.9 see Fig.8 14 6.0 − − 34 ns 2.0 − − 220 ns 4.5 − − 44 ns 6.0 − − 37 ns 2.0 − − 220 ns 4.5 − − 44 ns 6.0 − − 37 ns 2.0 − − 190 ns 4.5 − − 38 ns 6.0 − − 33 ns 2.0 − − 190 ns 4.5 − − 38 ns 6.0 − − 33 ns 2.0 95 − − ns 4.5 19 − − ns 6.0 16 − − ns 2.0 95 − − ns 4.5 19 − − ns 6.0 16 − − ns 2.0 95 − − ns 4.5 19 − − ns 6.0 16 − − ns 2.0 65 − − ns 4.5 13 − − ns 6.0 11 − − ns 2.0 95 − − ns 4.5 19 − − ns 6.0 16 − − ns Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS th trem fmax hold time DS to SH_CP see Fig.9 removal time MR to SH_CP see Fig.10 maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 TYP. MAX. UNIT VCC (V) 2.0 3 − − ns 4.5 3 − − ns 6.0 3 − − ns 2.0 65 − − ns 4.5 13 − − ns 6.0 11 − − ns 2.0 4.8 − − MHz 4.5 24 − − MHz 6.0 28 − − MHz 2.0 − − 240 ns 4.5 − − 48 ns Tamb = −40 to +125 °C tPHL/tPLH tPHL tPZH/tPZL tPHZ/tPLZ tW propagation delay SH_CP to Q7’ see Fig.7 propagation delay ST_CP to Qn see Fig.8 propagation delay MR to Q7’ 3-state output enable time OE to Qn 3-state output disable time OE to Qn shift clock pulse width HIGH or LOW storage clock pulse width HIGH or LOW master reset pulse width LOW 2003 Jun 25 see Fig.10 see Fig.11 see Fig.11 see Fig.7 see Fig.8 see Fig.10 15 6.0 − − 41 ns 2.0 − − 265 ns 4.5 − − 53 ns 6.0 − − 45 ns 2.0 − − 265 ns 4.5 − − 53 ns 6.0 − − 45 ns 2.0 − − 225 ns 4.5 − − 45 ns 6.0 − − 38 ns 2.0 − − 225 ns 4.5 − − 45 ns 6.0 − − 38 ns 2.0 110 − − ns 4.5 22 − − ns 6.0 19 − − ns 2.0 110 − − ns 4.5 22 − − ns 6.0 19 − − ns 2.0 110 − − ns 4.5 22 − − ns 6.0 19 − − ns Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS tsu set-up time DS to SH_CP set-up time SH_CP to ST_CP th trem fmax 2003 Jun 25 hold time DS to SH_CP see Fig.9 see Fig.8 see Fig.9 removal time MR to SH_CP see Fig.10 maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 16 TYP. MAX. UNIT VCC (V) 2.0 75 − − ns 4.5 15 − − ns 6.0 13 − − ns 2.0 110 − − ns 4.5 22 − − ns 6.0 19 − − ns 2.0 3 − − ns 4.5 3 − − ns 6.0 3 − − ns 2.0 75 − − ns 4.5 15 − − ns 6.0 13 − − ns 2.0 4 − − MHz 4.5 20 − − MHz 6.0 24 − − MHz Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 Family 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = 25 °C propagation delay SH_CP to Q7’ see Fig.7 4.5 − 25 42 ns propagation delay ST_CP to Qn see Fig.8 4.5 − 24 40 ns tPHL propagation delay MR to Q7’ see Fig.10 4.5 − 23 40 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 4.5 − 21 35 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 4.5 − 18 30 ns tW shift clock pulse width HIGH or LOW see Fig.7 4.5 16 6 − ns storage clock pulse width HIGH or LOW see Fig.8 4.5 16 5 − ns master reset pulse width LOW see Fig.10 4.5 20 8 − ns set-up time DS to SH_CP see Fig.9 4.5 16 5 − ns set-up time SH_CP to ST_CP see Fig.8 4.5 16 8 − ns th hold time DS to SH_CP see Fig.9 4.5 +3 −2 − ns trem removal time MR to SH_CP see Fig.10 4.5 +10 −7 − ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 4.5 30 52 − MHz propagation delay SH_CP to Q7’ see Fig.7 4.5 − − 53 ns propagation delay ST_CP to Qn see Fig.8 4.5 − − 50 ns tPHL propagation delay MR to Q7’ see Fig.10 4.5 − − 50 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 4.5 − − 44 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 4.5 − − 38 ns tPHL/tPLH tsu Tamb = −40 to +85 °C tPHL/tPLH 2003 Jun 25 17 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS tW tsu TYP. MAX. UNIT VCC (V) shift clock pulse width HIGH or LOW see Fig.7 4.5 20 − − ns storage clock pulse width HIGH or LOW see Fig.8 4.5 20 − − ns master reset pulse width LOW see Fig.10 4.5 25 − − ns set-up time DS to SH_CP see Fig.9 4.5 20 − − ns set-up time SH_CP to ST_CP see Fig.8 4.5 20 − − ns th hold time DS to SH_CP see Fig.9 4.5 3 − − ns trem removal time MR to SH_CP see Fig.10 4.5 13 − − ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 4.5 24 − − MHz propagation delay SH_CP to Q7’ see Fig.7 4.5 − − 63 ns propagation delay ST_CP to Qn see Fig.8 4.5 − − 60 ns tPHL propagation delay MR to Q7’ see Fig.10 4.5 − − 60 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 4.5 − − 53 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 4.5 − − 45 ns tW shift clock pulse width HIGH or LOW see Fig.7 4.5 24 − − ns storage clock pulse width HIGH or LOW see Fig.8 4.5 24 − − ns master reset pulse width LOW see Fig.10 4.5 30 − − ns set-up time DS to SH_CP see Fig.9 4.5 24 − − ns set-up time SH_CP to ST_CP see Fig.8 4.5 24 − − ns th hold time DS to SH_CP see Fig.9 4.5 3 − − ns trem removal time MR to SH_CP see Fig.10 4.5 15 − − ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 4.5 20 − − MHz Tamb = −40 to +125 °C tPHL/tPLH tsu 2003 Jun 25 18 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 AC WAVEFORMS 1/fmax handbook, full pagewidth SH_CP input VM tW tPLH tPHL 90% VM Q7' output 10% tTLH tTHL MSA699 74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the clock (SH_CP) to output (Q7’) propagation delays, the shift clock pulse width and maximum shift clock frequency. handbook, full pagewidth SH_CP input VM 1/fmax tsu ST_CP input VM tW tPLH Qn output tPHL VM MSA700 74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the storage clock (ST_CP) to output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time. 2003 Jun 25 19 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 handbook, full pagewidth SH_CP input VM tsu tsu th DS input th VM Q7' output VM MLB196 74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.9 Waveforms showing the data set-up and hold times for the DS input. handbook, full pagewidth MR input VM tW trem SH_CP input VM tPHL VM Q7' output MLB197 74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the Master Reset (MR) pulse width, the master reset to output (Q7’) propagation delay and the master reset to shift clock (SH_CP) removal time. 2003 Jun 25 20 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 tr handbook, full pagewidth tf 90% VM OE input 10% tPLZ tPZL Qn output VM LOW-to-OFF OFF-to-LOW 10% tPHZ tPZH 90% Qn output VM HIGH-to-OFF OFF-to-HIGH outputs enabled outputs enabled outputs disabled MSA697 74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing the 3-state enable and disable times for input OE. VCC handbook, full pagewidth PULSE GENERATOR VI VCC VO RL = 1 kΩ D.U.T RT CL 50 pF MGK563 TEST SWITCH tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.12 Test circuit for 3-state outputs. 2003 Jun 25 21 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 95-01-14 03-02-13 SOT38-4 2003 Jun 25 EUROPEAN PROJECTION 22 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 inches 0.244 0.041 0.228 θ Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 2003 Jun 25 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 23 o 8 0o Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 2003 Jun 25 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 24 o Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 2003 Jun 25 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 25 o Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 0.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- 2003 Jun 25 26 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Jun 25 27 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. 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