PHILIPS 74LV165A

INTEGRATED CIRCUITS
DATA SHEET
74LV165A
8-bit parallel-in/serial-out shift
register
Product specification
2003 Jul 23
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
FEATURES
74LV165A
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall times.
• Wide supply voltage range from 2.0 to 5.5 V
• Complies with JEDEC standard:
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V)
JESD8-1A (4.5 to 5.5 V).
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging current back flow through the
device when it is powered down.
• 5.5 V tolerant inputs/outputs
The 74LV165A is an 8-bit parallel-load or serial-in shift
register with complementary serial outputs (Q7 and Q7)
available from the last stage. When the parallel-load input
(PL) is LOW, parallel data from the inputs D0 to D7 are
loaded into the register asynchronously. When input PL is
HIGH, data enters the register serially at the input DS and
shifts one place to the right (Q0→Q1→Q2, etc.) with each
positive-going clock transition. This feature allows
parallel-to-serial converter expansion by tying the output
Q7 to the input DS of the succeeding stage.
• CMOS LOW power consumption
• Direct interface with TTL levels (2.7 to 3.6 V)
• Power-down mode
• Asynchronous 8-bit parallel load
• Synchronous serial input
• Latch-up performance exceeds 250 mA
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
The clock input is a gate-OR structure which allows one
input to be used as an active LOW clock enable input (CE)
input. The pin assignment for the inputs CP and CE is
arbitrary and can be reversed for layout convenience. The
LOW-to-HIGH transition of the input CE should only take
place while CP HIGH for predictable operation.
DESCRIPTION
The 74LV165A is a high-performance, low-power,
low-voltage, Is-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
tPHL/tPLH
PARAMETER
propagation delay
CONDITIONS
UNIT
VCC = 3.3 V; CL = 15 pF
CE, CP to Q7, Q7
7.5
ns
PL to Q7, Q7
8.0
ns
8.5
ns
115
MHz
3.0
pF
24
pF
D7 to Q7, Q7
fmax
maximum clock frequency
CI
input capacitance
CPD
power dissipation capacitance per buffer
VCC = 3.3 V; CL = 15 pF
VCC = 3.3 V; notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is Vi = GND to VCC.
2003 Jul 23
TYPICAL
2
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165A
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
PINS
PACKAGE
MATERIAL
CODE
74LV165AD
16
SO16
plastic
SOT109-1
74LV165APW
16
TSSOP16
plastic
SOT403-1
FUNCTION TABLE
See note 1.
OPERATING
MODES
INPUT
ON REGISTER
OUTPUT
PL
CE
CP
DS
D0 to D7
Q0
Q1 to Q6
Q7
Q7
L
X
X
X
L
L
L−L
L
H
L
X
X
X
H
H
H−H
H
L
Serial shift
H
L
↑
l
X
L
q0−q5
q6
q6
H
L
↑
h
X
H
q0−q5
q6
q6
Serial shift
H
↑
L
l
X
L
q0−q5
q6
q6
H
↑
L
h
X
H
q0−q5
q6
q6
Hold “do nothing”
H
H
X
X
X
q0
q1−q6
q7
q7
Hold “do nothing”
H
X
H
X
X
q0
q1−q6
q7
q7
Parallel load
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
↑ = LOW-to-HIGH clock transition.
2003 Jul 23
3
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165A
PINNING
PIN
SYMBOL
DESCRIPTION
1
PL
asynchronous parallel load input
(active LOW)
2
CP
clock input (LOW-to-HIGH,
edge-triggered)
3
D4
parallel data input
PL 1
16 VCC
4
D5
parallel data input
CP 2
15 CE
5
D6
parallel data input
D4 3
14 D3
6
D7
parallel data input
D5 4
7
Q7
complementary serial output
from the last stage
8
GND
9
Q7
10
DS
serial data input
11
D0
parallel data input
12
D1
parallel data input
13
D2
parallel data input
14
D3
parallel data input
15
CE
clock enable input (active LOW)
16
VCC
supply voltage
handbook, halfpage
13 D2
165
D6 5
12 D1
ground (0 V)
D7 6
11 D0
serial output from the last stage
Q7 7
10 DS
GND 8
9
Q7
MNA984
Fig.1 Pin configuration.
handbook, halfpage
1
10
handbook, halfpage
11
12
13
14
3
4
5
6
1
DS
SRG8
C2[LOAD]
G1[SHIFT]
D0
15
D1
2
≥1
1
C3/
D2
10
D3
D4
11
D5
12
D6
Q7
D7
Q7
9
3D
2D
2D
13
7
14
3
PL
4
CP CE
2
5
15
MNA985
9
6
7
MNA986
Fig.2 Logic symbol.
2003 Jul 23
Fig.3 Logic symbol (IEEE/IEC).
4
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
D0
handbook, full pagewidth
D1
74LV165A
D2
D3
D4
D5
D6
D7
DS
CP
CE
D
SD
Q
D
SD
Q
D
SD
Q
D
SD
Q
D
SD
Q
D
SD
Q
D
SD
Q
CP
FF0
CP
FF1
CP
FF2
CP
FF3
CP
FF4
CP
FF5
CP
FF6
RD
RD
RD
RD
RD
RD
RD
D
SD
Q
Q7
CP
FF7
Q
RD
Q7
PL
MNA994
Fig.4 Logic diagram.
2003 Jul 23
5
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
handbook, halfpage
11 12 13 14 3
74LV165A
4
5
6
D0 D1 D2 D3 D4 D5 D6 D7
1 PL
10 DS
2 CP
15 CE
Q7 9
8-BIT SHIFT REGISTER
PARALLEL-IN/SERIAL-OUT
Q7 7
MNA992
Fig.5 IEC logic symbol.
handbook, full pagewidth
CP
CE
DS
PL
D0
D1
D2
D3
D4
D5
D6
D7
Q7
Q7
inhibit
serial shift
MNA993
load
Fig.6 Timing diagram.
2003 Jul 23
6
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
2.0
5.5
V
VI
input voltage
0
5.5
V
VO
output voltage
0
VCC
V
Tamb
operating ambient temperature
tr, tf
input rise and fall times
−40
+85
°C
VCC = 2.3 to 2.7 V
0
200
ns/V
VCC = 3.0 to 3.6 V
0
100
ns/V
VCC = 4.5 to 5.5 V
0
20
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
VCC
supply voltage
IIK
input diode current
VI
input voltage
IOK
output diode current
VO
output voltage
CONDITIONS
VI < 0
VO > VCC or VO < 0
MIN.
MAX.
UNIT
−0.5
+7.0
V
−
−20
mA
−0.5
+7.0
V
−
±50
mA
note 1
−0.5
VCC + 0.5
V
Power-down mode
−0.5
+7.0
V
VO = 0 to VCC
−
±25
mA
IO
output source or sink current
ICC, IGND
VCC or GND current
−
±50
mA
Tstg
storage temperature
−65
+150
°C
Ptot
power dissipation
−
500
mW
Tamb = −40 to +85 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO16 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP16 packages: above 60 °C derate linearly with 5.5 mW/K.
2003 Jul 23
7
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
OTHER
TYP.(1)
MAX.
UNIT
VCC (V)
Tamb = −40 to +85 °C
VIH
VIL
VOL
VOH
HIGH-level input
voltage
LOW-level input
voltage
LOW-level output
voltage
HIGH-level output
voltage
2.0
1.5
−
−
V
2.3 to 2.7
0.7 × VCC
−
−
V
3.0 to 3.6
0.7 × VCC
−
−
V
4.5 to 5.5
0.7 × VCC
−
−
V
2.0
−
−
0.5
V
2.3 to 2.7
−
−
0.3 × VCC
V
3.0 to 3.6
−
−
0.3 × VCC
V
4.5 to 5.5
−
−
0.3 × VCC
V
VI = VIH or VIL
IO = 50 µA
2.0 to 5.5
−
−
0.1
V
IO = 2 mA
2.3
−
−
0.4
V
IO = 6 mA
3.0
−
−
0.44
V
IO = 12 mA
4.5
−
−
0.55
V
IO = −50 µA
2.0 to 5.5
VCC − 0.1
−
−
V
IO = −2 mA
2.3
2.0
−
−
V
IO = −6 mA
3.0
2.48
−
−
V
IO = −12 mA
4.5
3.8
−
−
V
VI = 5.5 V or GND
5.5
−
±0.01
±1
µA
VI = VIH or VIL
ILI
input leakage
current
Ioff
power OFF leakage VI or VO = 5.5 V
current
0.0
−
±0.05
±5
µA
ICC
quiescent supply
current
5.5
−
0.2
20
µA
VI = VCC or GND; IO = 0
Note
1. All typical values are measured at VCC = 5.5 V and Tamb = 25 °C.
2003 Jul 23
8
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
SYMBOL
PARAMETER
CL
(pF)
TYP.(1)
MIN.
MAX.
UNIT
WAVEFORMS
VCC (V)
see Figs 7, 8 and
12
2.3 to 2.7
15
1.0
11.0
22.0
ns
3.0 to 3.6
15
1.0
7.5
18.0
ns
4.5 to 5.5
15
1.0
5.5
11.5
ns
2.3 to 2.7
15
1.0
11.5
23.5
ns
3.0 to 3.6
15
1.0
8.0
18.5
ns
4.5 to 5.5
15
1.0
5.5
11.5
ns
2.3 to 2.7
15
1.0
12.0
24.0
ns
3.0 to 3.6
15
1.0
8.5
16.5
ns
4.5 to 5.5
15
1.0
6.0
10.5
ns
2.3 to 2.7
50
1.0
13.0
26.0
ns
3.0 to 3.6
50
1.0
9.0
21.5
ns
4.5 to 5.5
50
1.0
6.1
13.5
ns
2.3 to 2.7
50
1.0
14.0
28.0
ns
3.0 to 3.6
50
1.0
10.0
22.0
ns
4.5 to 5.5
50
1.0
6.5
13.5
ns
2.3 to 2.7
50
1.0
14.0
28.0
ns
3.0 to 3.6
50
1.0
10.0
20.0
ns
4.5 to 5.5
50
1.0
6.5
12.5
ns
Tamb = −40 to +85 °C
tPLH/tPHL
tPLH/tPHL
tPLH/tPHL
tPLH/tPHL
tPLH/tPHL
tPLH/tPHL
tW
tW
trem
tsu
tsu
2003 Jul 23
propagation delay
CE, CP to Q7, Q7
propagation delay
PL to Q7, Q7
propagation delay
D7 to Q7, Q7
propagation delay
CE, CP to Q7, Q7
propagation delay
PL to Q7, Q7
propagation delay
D7 to Q7, Q7
see Figs 7, 8 and
12
see Figs 9 and 12
see Figs 7, 8 and
12
see Figs 7, 8 and
12
see Figs 9 and 12
clock pulse with
HIGH to LOW
see Figs 7, 8 and
12
2.3 to 2.7
−
9.0
−
−
ns
3.0 to 3.6
−
7.0
−
−
ns
4.5 to 5.5
−
4.0
−
−
ns
parallel load pulse
with LOW
see Figs 7, 8 and
12
2.3 to 2.7
−
13.0
−
−
ns
3.0 to 3.6
−
9.0
−
−
ns
4.5 to 5.5
−
6.0
−
−
ns
removal time
PL to CP, CE
see Figs 8 and 12
2.3 to 2.7
−
8.5
−
−
ns
3.0 to 3.6
−
6.0
−
−
ns
4.5 to 5.5
−
4.0
−
−
ns
set-up time
DS to CP, CE
see
Figs 10, 11 and
12
2.3 to 2.7
−
9.5
−
−
ns
3.0 to 3.6
−
6.0
−
−
ns
4.5 to 5.5
−
4.0
−
−
ns
set-up time
CE to CP; CP to CE
see
Figs 10, 11 and
12
2.3 to 2.7
−
7.0
−
−
ns
3.0 to 3.6
−
5.0
−
−
ns
4.5 to 5.5
−
3.5
−
−
ns
9
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165A
TEST CONDITIONS
SYMBOL
PARAMETER
WAVEFORMS
tsu
th
th
fmax
VCC (V)
MAX.
UNIT
see
Figs 10, 11 and
12
2.3 to 2.7
−
12.0
−
−
ns
3.0 to 3.6
−
8.5
−
−
ns
4.5 to 5.5
−
5.0
−
−
ns
hold time
DS to CP; CE
PL to CP; CE
see
Figs 10, 11 and
12
2.3 to 2.7
−
0
−
−
ns
3.0 to 3.6
−
0
−
−
ns
4.5 to 5.5
−
0.5
−
−
ns
hold time Don to PL
see
Figs 10, 11 and
12
2.3 to 2.7
−
0.5
−
−
ns
3.0 to 3.6
−
0.5
−
−
ns
4.5 to 5.5
−
1.0
−
−
ns
set-up time
Don to PL
maximum clock pulse see Figs 7 and 12
frequency
2.3 to 2.7
15
45
80
−
MHz
3.0 to 3.6
15
55
115
−
MHz
4.5 to 5.5
15
90
165
−
MHz
2.3 to 2.7
50
35
65
−
MHz
3.0 to 3.6
50
50
90
−
MHz
4.5 to 5.5
50
85
125
−
MHz
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Jul 23
TYP.(1)
MIN.
CL
(pF)
10
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165A
AC WAVEFORMS
1/fmax
handbook, full pagewidth
VI
CP input
VM
GND
tW
t PHL
t PLH
VOH
VM
Q7 or Q7 output
VOL
MNA987
INPUT
VCC
VM
VI
tr = tf
2.3 to 2.7 V
0.5 × VCC
VCC
≤ 3.0 ns
3.0 to 3.6 V
0.5 × VCC
VCC
≤ 3.0 ns
4.5 to 5.5 V
0.5 × VCC
VCC
≤ 3.0 ns
The changing to output assumes internal Q6 opposite state from Q7.
Fig.7
Clock pulse (CP) to output (Q7 or Q7) propagation delays, the clock pulse width and the maximum clock
frequency.
2003 Jul 23
11
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165A
VI
handbook, full pagewidth
VM
PL input
GND
tW
t rem
VI
CE, CP input
VM
GND
t PLH
VOH
VM
Q7 or Q7 output
GND
MNA988
The changing to output assumes internal Q6 opposite state from Q7.
Fig.8
Parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel load
to clock (CP) and clock enable (CE) removal time.
VI
handbook, full pagewidth
VM
D7 input
GND
t PLH
t PHL
VOH
VM
Q7 output
VOL
t PHL
t PLH
VOH
VM
Q7 output
VOL
MNA989
The changing to output assumes internal Q6 opposite state from Q7.
Fig.9 Data input (Don) to output (Q7 or Q7) propagation delays when PL is LOW.
2003 Jul 23
12
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
handbook, full pagewidth
74LV165A
VI
VM
Dn input
VM
GND
t su
th
t su
th
VI
PL input
VM
VM
GND
MNA991
Fig.10 Set-up and hold times from the data inputs (Don) to the parallel load input (PL).
VI
handbook, full pagewidth
(1)
VM
CP, CE input
GND
th
th
tsu
tsu
VI
VM
DS input
GND
tsu
tW
VI
VM
CP, CE input
GND
MNA990
(1) CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate
when the input is permitted to change for predictable output performance.
Fig.11 Set-up and hold times from the serial data input (DS) to the clock (CP) and the clock enable inputs (CE),
from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable
input (CE).
2003 Jul 23
13
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165A
S1
handbook, full pagewidth
VCC
PULSE
GENERATOR
RL =
VI
1 kΩ
VO
D.U.T.
CL
RT
MNA183
TEST
S1
tPLH/tPHL
open
tPLZ/tPZL
VCC
tPHZ/tPZH
GND
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.12 Load circuitry for switching times.
2003 Jul 23
14
VCC
open
GND
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165A
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
2003 Jul 23
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
15
o
8
0o
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165A
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
2003 Jul 23
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
16
o
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165A
DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Interned at URL tap://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Jul 23
17
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA75
© Koninklijke Philips Electronics N.V. 2003
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/01/pp18
Date of release: 2003
Jul 23
Document order number:
9397 750 11648