INTEGRATED CIRCUITS 74LV165 8-bit parallel-in/serial-out shift register Product specification Supersedes data of 1997 May 15 IC24 Data Handbook 1998 May 07 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register FEATURES 74LV165 DESCRIPTION • Wide operating voltage: 1.0 to 5.5 V • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, The 74LV165 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT165. The 74LV165 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0→Q1→Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. Tamb = 25°C • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C • Asynchronous 8-bit parallel load • Synchronous serial input • Output capability: standard • ICC category: MSI The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER tPHL/tPLH fmax Maximum clock frequency CI Input capacitance CPD CONDITIONS TYPICAL UNIT 18 18 14 ns 78 MHz 3.5 pF 35 pF CL = 15 pF; VCC = 3.3 V Propagation delay CE, CP to Q7, Q7 PL to Q7, Q7 D7 to Q7, Q7 Power dissipation capacitance per gate VCC = 3.3 V VI = GND to VCC1 NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA 16-Pin Plastic DIL –40°C to +125°C 74LV165 N 74LV165 N SOT38-4 16-Pin Plastic SO –40°C to +125°C 74LV165 D 74LV165 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +125°C 74LV165 DB 74LV165 DB SOT338-1 16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV165 PW 74LV165PW DH SOT403-1 PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER PL 1 16 V CC CP 2 15 CE D4 3 14 D3 D5 4 13 D2 D6 5 12 D1 D7 6 11 D0 Q7 7 10 DS Q7 GND 8 1 9 SV00585 1998 May 07 PKG. DWG. # 2 SYMBOL PL FUNCTION Asynchronous parallel load input (active LOW) 2 CP Clock input (LOW to HIGH, edge-triggered) 7 Q7 Complementary output from the last stage 8 GND Ground (0 V) 9 Q7 Serial output from last stage 10 DS Serial data input 11, 12, 13, 14, 3, 4, 5, 6 D0 to D7 Parallel data inputs 15 CE Clock enable input (active LOW) 16 VCC Positive supply voltage 853–1915 19349 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 LOGIC SYMBOL FUNCTIONAL DIAGRAM 10 DS 11 D0 12 D1 13 D2 14 D3 3 D4 4 D5 5 D6 Q7 9 D7 Q7 7 6 1 PL 1 PL 10 DS 2 CP 15 CE 11 12 13 14 3 4 5 6 D0 D1 D2 D3 D4 D5 D6 D7 8–BIT SHIFT REGISTER PARALLEL– IN / SERIAL – OUT CP CE 2 Q7 9 Q7 7 15 SV00586 SV00588 LOGIC SYMBOL (IEEE/IEC) 1 15 2 10 11 12 13 SRG8 C2 [LOAD] G1 [SHIFT] >1 1 C3/ 3D 2D 2D 14 3 4 5 9 6 7 SV00587 LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 DS CP D CE PL SD CP FF0 RD Q D SD CP FF1 RD Q D SD CP FF2 RD Q D SD CP FF3 RD Q D SD CP FF4 RD Q D SD CP FF5 RD Q D SD CP FF6 RD Q D SD Q CP FF7 RD Q Q7 Q7 SV00589 1998 May 07 3 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 FUNCTION TABLE INPUTS OPERATING MODES PL CE CP DS L X X X L L L X X X H H H L ↑ l X L H L ↑ h X H H H X X X q0 Parallel load Serial Shift Hold “do nothing” Qn REGISTERS D0–D7 Q0 OUTPUTS Q1–Q6 Q7 Q7 L–L L H H–H H L q0–q5 q6 q6 q0–q5 q6 q6 q1–q6 q7 q7 NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level I = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition X = don’t care ↑ = LOW-to-HIGH clock transition RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN TYP MAX UNIT See Note 1 1.0 3.3 5.5 V DC supply voltage VI Input voltage 0 – VCC V VO Output voltage 0 – VCC V +85 +125 °C 500 200 100 50 ns/V Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times See DC and AC characteristics –40 –40 VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V – – – – – – – – NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER VCC DC supply voltage CONDITIONS RATING UNIT –0.5 to +7.0 V IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA IO DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 IGND, ICC Tstg PTOT DC VCC or GND current for types with – standard outputs 50 Storage temperature range Power dissipation per package – plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) –65 to +150 for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mA mA °C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 May 07 4 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level Input voltage LOW level Input voltage TYP1 VOH O VOL VOL O HIGH level output voltage; g STANDARD outputs l l output t t LOW level voltage out uts voltage; all outputs LOW level output voltage; g STANDARD outputs MIN 0.9 0.9 VCC = 2.0 V 1.4 1.4 VCC = 2.7 to 3.6 V 2.0 2.0 VCC = 4.5 to 5.5 V 0.7VCC UNIT MAX V 0.7VCC VCC = 1.2 V 0.3 0.3 VCC = 2.0 V 0.6 0.6 VCC = 2.7 to 3.6 V 0.8 0.8 0.3VCC 0.3VCC VCC = 1.2 V; VI = VIH or VIL; –IO = 100µA VOH MAX VCC = 1.2 V VCC = 4.5 to 5.5 HIGH level l l output t t voltage out uts voltage; all outputs -40°C to +125°C V 1.2 VCC = 2.0 V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7 V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0 V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 4.5 V; VI = VIH or VIL; –IO = 100µA 4.3 4.5 4.3 VCC = 3.0 V; VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 VCC = 4.5 V; VI = VIH or VIL; –IO = 12mA 3.60 4.20 3.50 V V VCC = 1.2 V; VI = VIH or VIL; IO = 100µA 0 VCC = 2.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 2.7 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 4.5 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0 V; VI = VIH or VIL; IO = 6mA 0.25 0.40 0.50 VCC = 4.5 V; VI = VIH or VIL; IO = 12mA 0.35 0.55 0.65 V V Input leakage current VCC = 5.5 V; VI = VCC or GND 1.0 1.0 µA ICC Quiescent supply current; MSI VCC = 5.5 V; VI = VCC or GND; IO = 0 20.0 160 µA ∆ICC Additional quiescent supply current per input VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V 500 850 µA II NOTE: 1. All typical values are measured at Tamb = 25°C. 1998 May 07 5 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL tPLH/tPHL tPLH/tPHL tPLH/tPHL PARAMETER Propagation delay CE, CP to Q7, Q7 Propagation delay PL to Q7, Q7 Propagation delay D7 to Q7, Q7 WAVEFORM Figures 1, 2 Figures 1, 2 Figures 1, 2 tw trem tsu tsu 1998 May 07 Clock Pulse width HIGH or LOW Parallel load pulse width LOW Removal time PL to CP, CE Set-up time DS to CP, CE Set-up time CE to CP; CP CP to CE –40 to +85 °C MIN TYP1 1.2 – 115 2.0 – 38 61 – 76 Figures 1, 2 MIN – – 27 43 – 54 – 222 36 – 45 4.5 to 5.5 – 15 24 – 30 1.2 – 110 2.0 – 35 56 – 70 2.7 – 24 39 – 49 3.0 to 3.6 – 202 33 – 41 4.5 to 5.5 – 14 22 – 27 1.2 – 90 2.0 – 28 45 – 56 2.7 – 20 32 – 40 – 172 27 – 33 ns – ns – 4.5 to 5.5 – 11 18 – 22 2.0 34 10 – 41 – 2.7 25 8 – 30 – 3.0 to 3.6 20 72 – 24 – 4.5 to 5.5 15 5 – 18 – 2.0 34 10 – 41 – 2.7 25 8 – 30 – 3.0 to 3.6 20 72 – 24 – 4.5 to 5.5 15 5 – 18 – 1.2 – 40 – – – 2.0 24 15 – 30 – 2.7 18 11 – 23 – 3.0 to 3.6 17 102 – 21 – 4.5 to 5.5 12 7 – 15 – 1.2 – –8 – – – 2.0 22 –2 – 26 – 2.7 16 –1 – 19 – 3.0 to 3.6 13 –12 – 15 – 4.5 to 5.5 9 0 – 10 – 1.2 – 20 – – – 2.0 22 7 – 26 – 2.7 16 5 – 19 – 3.0 to 3.6 13 42 – 15 – 4.5 to 5.5 9 3 – 10 – 6 UNIT MAX 2.7 Figures 1 1, 2 Figures 1, 2 MAX 3.0 to 3.6 Figures 1 1, 2 Figures 1, 2 –40 to +125 °C VCC(V) 3.0 to 3.6 tw LIMITS CONDITION ns ns ns ns ns ns Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 AC CHARACTERISTICS (Continued) GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER Set-up time Dn to PL tsu th th TYP1 MAX MIN MAX 1.2 – 25 – – – 2.0 22 8 – 26 – 2.7 16 6 – 19 – 3.0 to 3.6 13 52 – 15 – 4.5 to 5.5 9 4 – 10 – 1.2 – 20 – – – 2.0 22 7 – 26 – 2.7 16 5 – 19 – 3.0 to 3.6 13 4 – 15 – 4.5 to 5.5 9 3 – 10 – 1.2 – –30 – – – 2.0 5 –8 – 5 – 2.7 5 –6 – 5 – 3.0 to 3.6 5 –52 – 5 – 4.5 to 5.5 5 –4 – 5 – 2.0 14 40 – 12 – 2.7 19 60 – 16 – 3.0 to 3.6 24 652 – 20 – 36 75 – 30 – Figures 1, 2 Maximum clock pulse frequency fmax MIN Figures 1, 2 Hold time CE to CP, CP to t CE Figures 1 1, 2 –40 to +125 °C VCC(V) Figures 1, 2 Hold time Ds to CP, CE Dn to PL –40 to +85 °C CONDITION WAVEFORM 4.5 to 5.5 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25°C 2. Typical values are measured at VCC = 3.3 V. UNIT ns ns ns MHz AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V. VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load. VI 1/fmax PL INPUT VI CP INPUT VM GND VM tW trem GND tW VI tPLH tPHL VM CE, CP INPUT VOH Q7 or Q7 OUTPUT GND VM tPHL VOL The changing to output assumes internal Q6 opposite state from Q7. VOH Q7 or Q7 OUTPUT SV00590 VM VOL Figure 1. Clock (CP) to output (Q7 or Q7) propagation delays, the clock pulse width and the maximum clock frequency. The changing to output assumes internal Q6 opposite state from Q7. SV00591 Note to Figures 1 and 2 Figure 2. Parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel load to clock (CP) and clock enable (CE) removal time. The changing to output assumes internal Q6 opposite state from Q7. 1998 May 07 7 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V. VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load. VI Dn INPUT VM GND VI tsu D7 INPUT tsu tH VM tH VI GND PL INPUT VM GND tPLH tPHL SV00593 VOH Q7 OUTPUT Figure 5. Set-up and hold times from the data inputs (Dn) to the parallel load input (PL). VM VOL TEST CIRCUIT tPHL tPLH Vcc VOH Q7 OUTPUT VM VO Vl VOL PULSE GENERATOR SV00592 D.U.T. Figure 3. Data input (Dn) to output (Q7 or Q7) propagation delays when PL is LOW. DS INPUT VM RL = Load resistor CL = Load capacitance includes jig and probe capacitiance tsu (H) RT = Termination resistance should be equal to ZOUT of pulse generators. th th TEST stable VM tPLH/tPHL GND tsu th tW VI CP, CE INPUT GND VCC VI < 2.7V VCC 2.7–3.6V 2.7V ≥ 4.5 V VCC SV00902 VM Figure 6. Load circuitry for switching times. CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for predictable output performance. SV00595 Figure 4. Set-up and hold times from the serial data input (DS) to the clock (CP) and the clock enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable input (CE). Note to Figure 4 CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for predictable output performance. 1998 May 07 RL= 1k DEFINITIONS tsu (L) VI CL Test Circuit for Outputs see note VI CP, CE INPUT GND 50pF RT 8 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 DIP16: plastic dual in-line package; 16 leads (300 mil) 1998 May 07 9 SOT38-4 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 SO16: plastic small outline package; 16 leads; body width 3.9 mm 1998 May 07 10 SOT109-1 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm 1998 May 07 11 SOT338-1 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 1998 May 07 12 SOT403-1 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 NOTES 1998 May 07 13 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 May 07 14 Date of release: 05-96 9397-750-04432