DS90LV028A 3V LVDS Dual CMOS Differential Line Receiver General Description Features The DS90LV028A is a dual CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LV028A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver also supports open, shorted and terminated (100Ω) input fail-safe. The receiver output will be HIGH for all fail-safe conditions. The DS90LV028A has a flow-through design for easy PCB layout. n n n n n n n n n n The DS90LV028A and companion LVDS line driver provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications. n n n n Connection Diagrams > 400 Mbps (200 MHz) switching rates 50 ps differential skew (typical) 0.1 ns channel-to-channel skew (typical) 2.5 ns maximum propagation delay 3.3V power supply design Flow-through pinout Power down high impedance on LVDS inputs Low Power design (18mW @ 3.3V static) Interoperable with existing 5V LVDS networks Accepts small swing (350 mV typical) differential signal levels Supports open, short and terminated input fail-safe Conforms to ANSI/TIA/EIA-644 Standard Industrial temperature operating range (−40˚C to +85˚C) Available in SOIC and space saving LLP package Functional Diagram SOIC 10007701 Order Number DS90LV028ATM See NS Package Number M08A 10007702 Truth Table LLP (Top View) 10007725 INPUTS OUTPUT [RIN+] − [RIN−] ROUT VID ≥ 0.1V H VID ≤ −0.1V L Full Fail-safe OPEN/SHORT or Terminated H Order Number DS90LV028ATLD See NS Package Number LDC08A © 2005 National Semiconductor Corporation DS100077 www.national.com DS90LV028A 3V LVDS Dual CMOS Differential Line Receiver August 2005 DS90LV028A Absolute Maximum Ratings (Note 1) Lead Temperature Range Soldering If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Maximum Junction Temperature Supply Voltage (VCC) (4 sec.) ESD Rating (Note 4) −0.3V to +4V Input Voltage (RIN+, RIN−) M Package Recommended Operating Conditions 1025 mW 8.2 mW/˚C above +25˚C LD Package 3.3W Derate LD Package ≥ 500 V (EIAJ 0Ω, 200 pF) −0.3V to VCC + 0.3V Maximum Package Power Dissipation @ +25˚C Derate M Package ≥ 7 kV (HBM 1.5 kΩ, 100 pF) −0.3V to +3.9V Output Voltage (ROUT) +260˚C +150˚C 25.6 mW/˚C above +25˚C Storage Temperature Range −65˚C to +150˚C Min Typ Max Units Supply Voltage (VCC) +3.0 +3.3 +3.6 V Receiver Input Voltage GND 3.0 V +85 ˚C Operating Free Air Temperature (TA) −40 25 Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3) Symbol Parameter Conditions VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current Pin VCM = +1.2V, 0V, 3V (Note 12) VCC = 3.6V or 0V VIN = +3.6V Output High Voltage +100 −10 VCC = 0V mV ±1 ±1 +10 µA +10 µA +20 µA 2.7 3.1 V IOH = −0.4 mA, Inputs terminated 2.7 3.1 V IOH = −0.4 mA, Inputs shorted 2.7 3.1 VOL Output Low Voltage IOL = 2 mA, VID = −200 mV IOS Output Short Circuit Current VOUT = 0V (Note 5) VCL Input Clamp Voltage ICL = −18 mA ICC No Load Supply Current Inputs Open ROUT Units mV -20 IOH = −0.4 mA, VID = +200 mV Max −100 −10 VIN = 0V VOH Typ RIN+, RIN− VIN = +2.8V Min V 0.3 0.5 V −15 −50 −100 mA −1.5 −0.8 VCC V 5.4 9 mA Units Switching Characteristics VCC = +3.3V ± 10%, TA = −40˚C to +85˚C (Notes 6, 7) Min Typ Max tPHLD Symbol Differential Propagation Delay High to Low Parameter CL = 15 pF Conditions 1.0 1.6 2.5 ns tPLHD Differential Propagation Delay Low to High VID = 200 mV 1.0 1.7 2.5 ns tSKD1 Differential Pulse Skew |tPHLD − tPLHD| (Note 8) 0 50 400 ps tSKD2 Differential Channel-to-Channel Skew-same device (Note 9) 0 0.1 0.5 ns tSKD3 Differential Part to Part Skew (Note 10) 0 1.0 ns tSKD4 Differential Part to Part Skew (Note 11) 0 1.5 ns tTLH Rise Time 325 800 ps tTHL Fall Time 225 800 fMAX Maximum Operating Frequency (Note 13) (Figure 1 and Figure 2) 200 250 ps MHz Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified (such as VID). Note 3: All typicals are given for: VCC = +3.3V and TA = +25˚C. Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) ≥ 7 kV EIAJ (0Ω, 200 pF) ≥ 500V Note 5: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. Note 6: CL includes probe and jig capacitance. www.national.com 2 Note 8: tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel. Note 9: tSKD2 is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple receivers within the integrated circuit. Note 10: tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5˚C of each other within the operating temperature range. Note 11: tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. Note 12: VCC is always higher than RIN+ and RIN− voltage. RIN+ and RIN− are allowed to have voltage range −0.05V to +3.05V. VID is not allowed to be greater than 100 mV when VCM = 0V or 3V. Note 13: fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.7V), load = 15 pF (stray plus probes). Parameter Measurement Information 10007703 FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit 10007704 FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms Typical Application Balanced System 10007705 FIGURE 3. Point-to-Point Application environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. Other Applications Information General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner’s Manual (lit #550062-002), AN-808, AN-977, AN-971, AN-916, AN-805, AN-903. LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 3. This configuration provides a clean signaling 3 www.national.com DS90LV028A Note 7: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0% to 100%) ≤ 3 ns for RIN. DS90LV028A Applications Information (Continued) configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90LV028A differential line receiver is capable of detecting signals as low as 100 mV, over a ± 1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ± 1V around this center point. The ± 1V shifting may be the result of a ground potential difference between the driver’s ground reference and the receiver’s ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V (measured from each pin to ground). The device will operate for receiver input voltages up to VCC, but exceeding VCC will turn on the ESD protection circuitry which will clamp the bus voltages. 10007726 FIGURE 4. LLP Thermal Land Pad and Pin Pads DIFFERENTIAL TRACES Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result! (Note that the velocity of propagation, v = c/E r where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number of vias and other discontinuities on the line. Avoid 90˚ turns (these cause impedance discontinuities). Use arcs or 45˚ bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended) 0.1µF and 0.01µF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10µF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply and ground. PC BOARD CONSIDERATIONS Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. For PC board considerations for the LLP package, please refer to application note AN-1187 “Leadless Leadframe Package.” It is important to note that to optimize signal integrity (minimize jitter and noise coupling), the LLP thermal land pad, which is a metal (normally copper) rectangular region located under the package as seen in Figure 4, should be attached to ground and match the dimensions of the exposed pad on the PCB (1:1 ratio). www.national.com TERMINATION Use a termination resistor which best matches the differential impedance or your transmission line. The resistor should be between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work correctly without resistor termination. Typically, connecting a single resistor across the pair at the receiver end will suffice. Surface mount 1% - 2% resistors are the best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be < 10mm (12mm MAX). 4 application note AN-1194 “Failsafe Biasing of LVDS Interfaces” for more information. (Continued) FAIL-SAFE FEATURE PROBING LVDS TRANSMISSION LINES Always use high impedance ( > 100kΩ), low capacitance ( < 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results. The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver’s internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The DS90LV028A is a dual receiver device, and if an application requires only 1 receiver, the unused channel inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs. CABLES AND CONNECTORS, GENERAL COMMENTS When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100Ω. They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable. 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Please refer to Pin Descriptions Pin No. Name 1, 4 RIN- Inverting receiver input pin Description 2, 3 RIN+ Non-inverting receiver input pin 6, 7 ROUT Receiver output pin 8 VCC Power supply pin, +3.3V ± 0.3V 5 GND Ground pin Ordering Information 5 Operating Package Type/ Temperature Number Order Number −40˚C to +85˚C SOP/M08A DS90LV028ATM −40˚C to +85˚C LLP/LDC08A DS90LV028ATLD www.national.com DS90LV028A Applications Information DS90LV028A Typical Performance Curves Output High Voltage vs Power Supply Voltage Output Low Voltage vs Power Supply Voltage 10007708 10007707 Output Short Circuit Current vs Power Supply Voltage Differential Transition Voltage vs Power Supply Voltage 10007710 10007709 Power Supply Current vs Frequency Power Supply Current vs Ambient Temperature 10007712 10007711 www.national.com 6 DS90LV028A Typical Performance Curves (Continued) Differential Propagation Delay vs Power Supply Voltage Differential Propagation Delay vs Ambient Temperature 10007713 10007714 Differential Skew vs Power Supply Voltage Differential Skew vs Ambient Temperature 10007715 10007716 Differential Propagation Delay vs Differential Input Voltage Differential Propagation Delay vs Common-Mode Voltage 10007717 10007718 7 www.national.com DS90LV028A Typical Performance Curves (Continued) Transition Time vs Power Supply Voltage Transition Time vs Ambient Temperature 10007719 10007720 Differential Propagation Delay vs Load Transition Time vs Load 10007722 10007721 Differential Propagation Delay vs Load Transition Time vs Load 10007724 10007723 www.national.com 8 DS90LV028A Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead (0.150" Wide) Molded Small Outline Package, JEDEC Order Number DS90LV028ATM NS Package Number M08A LLP-8, 4mm x 4mm Body Order Number DS90LV028ATLD NS Package Number LDC08A 9 www.national.com DS90LV028A 3V LVDS Dual CMOS Differential Line Receiver Notes National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 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