DS90LV031B 3V LVDS Quad CMOS Differential Line Driver General Description Features The DS90LV031B is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LV031B accepts low voltage TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE ® function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical. The DS90LV031B is enhanced over the DS90LV031A in that the inputs are further ruggedized for excessive undershoot. The EN and EN* inputs allow active Low or active High control of the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV031B and companion line receiver (DS90LV032A) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications. n n n n n Connection Diagram Functional Diagram n n n n n n n n > 400 Mbps (200 MHz) switching rates 0.1 ns typical differential skew 0.4 ns maximum differential skew 2.0 ns maximum propagation delay Ruggedized inputs that can withstand excessive undershoot 3.3V power supply design ± 350 mV differential signaling Low power dissipation (13mW at 3.3V static) Interoperable with existing 5V LVDS devices Compatible with IEEE 1596.3 SCI LVDS standard Compatible with TIA/EIA-644 LVDS standard Industrial temperature operating range Available in SOIC and TSSOP surface mount packaging Dual-In-Line DS101311-1 Order Number DS90LV031BTM or DS90LV031BTMTC See NS Package Number M16A or MTC16 DS101311-2 Truth Table DRIVER Enables Input Outputs EN EN* DIN DOUT+ L H X Z Z L L H H H L All other combinations of ENABLE inputs DOUT− TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2000 National Semiconductor Corporation DS101311 www.national.com DS90LV031B 3V LVDS Quad CMOS Differential Line Driver January 2000 DS90LV031B Absolute Maximum Ratings (Note 1) Storage Temperature Range Lead Temperature Range Soldering (4 sec.) Maximum Junction Temperature ESD Rating (HBM, 1.5 kΩ, 100 pF) (EIAJ, 0 Ω, 200 pF) (CDM) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +4V −2V to (VCC + 0.3V) Input Voltage (DIN)(Note 2) Enable Input Voltage (EN, −2V to (VCC + 0.3V) EN*)(Note 2) Output Voltage (DOUT+, DOUT−)(Note 2) −1V to +3.9V Short Circuit Duration Continuous (DOUT+, DOUT−) Maximum Package Power Dissipation @ +25˚C M Package 1088 mW MTC Package 866 mW Derate M Package 8.5 mW/˚C above +25˚C Derate MTC Package 6.9 mW/˚C above +25˚C −65˚C to +150˚C +260˚C +150˚C ≥ 7 kV ≥ 500 V ≥ 1250 V Recommended Operating Conditions Supply Voltage (VCC) Operating Free Air Temperature (TA) Min +3.0 −40 Typ +3.3 +25 Max +3.6 +85 Units V ˚C Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 3, 4, 5) Symbol Parameter VOD1 Differential Output Voltage ∆VOD1 Change in Magnitude of VOD1 for Complementary Output States VOS Offset Voltage ∆VOS Change in Magnitude of VOS for Complementary Output States VOH Output Voltage High VOL Output Voltage Low VIH Input Voltage High VIL Input Voltage Low IIH Input Current IIL Input Current Conditions RL = 100Ω (Figure 1) Pin Min Typ Max Units DOUT− DOUT+ 250 350 450 mV 4 35 |mV| 1.25 1.375 V 5 25 |mV| 1.38 1.6 1.125 0.90 VIN = VCC or 2.5V VIN = GND or 0.4V ICL = −18 mA DIN, EN, EN* 1.03 V V 2.0 VCC V GND 0.8 V +10 µA +10 µA −6.0 −9.0 mA −6.0 −9.0 mA −20 ±1 +20 µA −10 ±1 +10 µA 5.0 8.0 mA −10 ±1 ±1 −1.5 −0.8 −10 VCL Input Clamp Voltage IOS Output Short Circuit Current ENABLED, (Note 11) DIN = VCC, DOUT+ = 0V or DIN = GND, DOUT− = 0V IOSD Differential Output Short Circuit Current IOFF Power-off Leakage ENABLED, VOD = 0V (Note 11) VOUT = 0V or 3.6V, VCC = 0V or Open IOZ Output TRI-STATE Current EN = 0.8V and EN* = 2.0V VOUT = 0V or VCC ICC No Load Supply Current Drivers Enabled DIN = VCC or GND ICCL Loaded Supply Current Drivers Enabled RL = 100Ω All Channels, DIN = VCC or GND (all inputs) 23 30 mA ICCZ No Load Supply Current Drivers Disabled DIN = VCC or GND, EN = GND, EN* = VCC 2.6 6.0 mA www.national.com 2 DOUT− DOUT+ VCC V Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 4, 10, 12) Symbol Parameter Conditions Min Typ Max 0.8 1.18 2.0 ns 0.8 1.25 2.0 ns Differential Pulse Skew |tPHLD − tPLHD| (Note 6) 0 0.07 0.4 ns tSKD2 Channel-to-Channel Skew (Note 7) 0 0.1 0.5 ns tSKD3 Differential Part to Part Skew (Note 8) 0 1.0 ns tSKD4 Differential Part to Part Skew (Note 9) 0 1.2 ns tTLH Rise Time 0.38 1.5 ns tTHL Fall Time 0.40 1.5 ns tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH tPZL fMAX Maximum Operating Frequency (Note 14) tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD1 RL = 100Ω, CL = 10 pF (Figure 2 and Figure 3) Units 5 ns 5 ns Enable Time Z to High 7 ns Enable Time Z to Low 7 RL = 100Ω, CL = 10 pF (Figure 4 and Figure 5) 200 250 ns MHz Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: These ABS-MAX voltage ratings are guaranteed by design and bench characterization. The pin under test is pulled negative with respect to ground, using a curve tracer. During the test, ICC and the current out of the pin under test are monitored using DC meters. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: VOD1 and ∆VOD1. Note 4: All typicals are given for: VCC = +3.3V, TA = +25˚C. Note 5: The DS90LV031B is a current mode device and only functions within datasheet specifications when a resistive load is applied to the driver outputs typical range is (90Ω to 110Ω) Note 6: tSKD1, |tPHLD − tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 7: tSKD2 is the Differential Channel-to-Channel Skew of any event on the same device. Note 8: tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5˚C of each other within the operating temperature range. Note 9: tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. Note 10: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 1 ns, and tf ≤ 1 ns. Note 11: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Note 12: CL includes probe and jig capacitance. Note 13: All input voltages are for one channel unless otherwise specified. Other inputs are set to GND. Note 14: fMAX generator input conditions: tr = tf switching. < 1ns, (0% to 100%), 50% duty cycle, 0V to 3V. Output Criteria: duty cycle = 45%/55%, VOD > 250mV, all channels Parameter Measurement Information DS101311-3 FIGURE 1. Driver VOD and VOS Test Circuit 3 www.national.com DS90LV031B Switching Characteristics - Industrial DS90LV031B Parameter Measurement Information (Continued) DS101311-4 FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit DS101311-5 FIGURE 3. Driver Propagation Delay and Transition Time Waveforms DS101311-6 FIGURE 4. Driver TRI-STATE Delay Test Circuit www.national.com 4 DS90LV031B Parameter Measurement Information (Continued) DS101311-7 FIGURE 5. Driver TRI-STATE Delay Waveform Typical Application DS101311-8 FIGURE 6. Point-to-Point Application duce a logic state and in the other direction to produce the other logic state. The output current is typically 3.5 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 6. AC or unterminated configurations are not allowed. The 3.5 mA loop current will develop a differential voltage of 350 mV across the 100Ω termination resistor which the receiver detects with a 250 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350 mV – 100 mV = 250 mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground as shown in Figure 7. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 700 mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires about 80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers. Applications Information General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner’s Manual (lit #550062-001), AN808, AN977, AN971, AN916, AN805, AN903. LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 6. This configuration provides a clean signaling environment for the quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90LV031B differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to pro5 www.national.com DS90LV031B Applications Information Termination: (Continued) Use a resistor which best matches the differential impedance or your transmission line. The resistor should be between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination. Typically, connect a single resistor across the pair at the receiver end. Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be < 10mm (12mm MAX). Probing LVDS Transmission Lines: Always use high impedance ( > 100kΩ), low capacitance ( < 2pF) scope probes with a wide bandwidth (1GHz) scope. Improper probing will give deceiving results. Cables and Connectors, General Comments: When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100Ω. They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. Fail-safe Feature: The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver’s internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The DS90LV032A is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs. 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or poweroff condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable. The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. The footprint of the DS90LV031B is the same as the industry standard 26LS31 Quad Differential (RS-422) Driver and is a step down replacement for the 5V DS90C031 Quad Driver. Power Decoupling Recommendations: Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1µF in parallel with 0.01µF, in parallel with 0.001µF at the power supply pin as well as scattered capacitors over the printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10µF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board. PC Board considerations: Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. Differential Traces: Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. Plus, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number or vias and other discontinuities on the line. Avoid 90˚ turns (these cause impedance discontinuities). Use arcs or 45˚ bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. www.national.com 6 External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. (Continued) 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. DS101311-9 FIGURE 7. Driver Output Levels Pin Descriptions Pin No. Name 1, 7, 9, 15 DIN Description 2, 6, 10, 14 DOUT+ Non-inverting driver output pin, LVDS levels 3, 5, 11, 13 DOUT− Inverting driver output pin, LVDS levels 4 EN Active high enable pin, OR-ed with EN* 12 EN* Active low enable pin, OR-ed with EN 16 VCC Power supply pin, +3.3V ± 0.3V 8 GND Ground pin Driver input pin, TTL/CMOS compatible Ordering Information Operating Package Type/ Order Number Temperature Number −40˚C to +85˚C SOP/M16A DS90LV031BTM −40˚C to +85˚C TSSOP/MTC16 DS90LV031BTMTC 7 www.national.com DS90LV031B Applications Information DS90LV031B Typical Performance Characteristics DS101311-10 FIGURE 8. Typical DS90LV031B, DOUT (single ended) vs RL, TA = 25˚C DS101311-11 FIGURE 9. Typical DS90LV031B, DOUT vs RL, VCC = 3.3V, TA = 25˚C www.national.com 8 DS90LV031B Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC Order Number DS90LV031BTM NS Package Number M16A 9 www.national.com DS90LV031B 3V LVDS Quad CMOS Differential Line Driver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead (0.100" Wide) Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90LV031BTMTC NS Package Number MTC16 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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