DS90C032B LVDS Quad CMOS Differential Line Receiver General Description Features The DS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90C032B accepts low voltage (350 mV) differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE ® function that may be used to multiplex outputs. The receiver also supports OPEN and terminated (100Ω) input Fail-safe. Receiver output will be HIGH for both Fail-safe conditions. The DS90C032B provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present. The DS90C032B and companion line driver (DS90C031B) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications. n n n n n n n n n Connection Diagram Functional Diagram > 155.5 Mbps (77.7 MHz) switching rates Accepts small swing (350 mV) differential signal levels High Impedance LVDS inputs with power down Ultra low power dissipation 600 ps maximum differential skew (5V, 25˚C) 6.0 ns maximum propagation delay Industrial operating temperature range Available in surface mount packaging (SOIC) Pin compatible with DS26C32A, MB570 (PECL) and 41LF (PECL) n Supports OPEN and terminated input fail-safe n Conforms to ANSI/TIA/EIA-644 LVDS standard Dual-In-Line DS100990-1 Order Number DS90C032BTM See NS Package Number M16A DS100990-2 Receiver Truth Table INPUTS OUTPUT EN ENABLES EN* RIN+ − RIN− ROUT L H X Z VID ≥ 0.1V H All other combinations of ENABLE inputs VID ≤ −0.1V L Fail-safe OPEN H or Terminated TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100990 www.national.com DS90C032B LVDS Quad CMOS Differential Line Receiver March 1999 Absolute Maximum Ratings (Note 1) ESD Rating (Note 7) (HBM, 1.5 kΩ, 100 pF) (EIAJ, 0 Ω, 200 pF) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ≥ 2kV ≥ 250V Recommended Operating Conditions Supply Voltage (VCC) −0.3V to +6V −0.3V to +5.8V Input Voltage (RIN+, RIN−) Enable Input Voltage −0.3V to (VCC + 0.3V) (EN, EN*) −0.3V to (VCC + 0.3V) Output Voltage (ROUT) Maximum Package Power Dissipation @ +25˚C M Package 1025 mW Derate M Package 8.2 mW/˚C above +25˚C Storage Temperature Range −65˚C to +150˚C Lead Temperature Range Soldering (4 sec.) +260˚C Maximum Junction Temperature +150˚C Min Typ +4.5 +5.0 Supply Voltage (VCC) Receiver Input GND Voltage Operating Free Air Temperature (TA) DS90C032BT −40 +25 Max +5.5 Units V 2.4 V +85 ˚C Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3) Symbol Parameter VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current Conditions VCM = +1.2V Output High Voltage VIN = +2.4V VCC = 5.5V or 0V VIN = 0V IOH = −0.4 mA, VID = +200 mV VOL Output Low Voltage IOH = −0.4 mA, Input terminated IOL = 2 mA, VID = −200 mV VOH IOS Output Short Circuit Current IOZ Output TRI-STATE Current VIH Input High Voltage VIL Input Low Voltage II Input Current VCL Input Clamp Voltage ICC No Load Supply Current Receivers Enabled ICCZ No Load Supply Current Receivers Disabled www.national.com Pin RIN+, RIN− ROUT EN, EN* EN = GND, EN* = VCC, Inputs Open 2 VCC Typ Max Units +100 mV −100 mV −10 ±1 ±1 3.8 4.9 3.8 4.9 −10 Enabled, VOUT = 0V (Note 8) Disabled, VOUT = 0V or VCC ICL = −18 mA EN, EN* = VCC or GND, Inputs Open EN, EN* = 2.4 or 0.5, Inputs Open Min +10 µA +10 µA V V 0.07 0.3 V −15 −60 −100 mA −10 ±1 +10 µA 2.0 V −10 ±1 −1.5 −0.8 3.5 0.8 V +10 µA 10 mA V 3.7 11 mA 3.5 10 mA Switching Characteristics VCC = +5.0V, TA = +25˚C (Notes 3, 4, 9) Symbol tPHLD Differential Propagation Delay High to Low Parameter tPLHD Differential Propagation Delay Low to High Conditions CL = 5 pF VID = 200 mV (Figure 1 and Figure 2) Min Typ Max 1.5 3.40 5.0 Units ns 1.5 3.48 5.0 ns 0 80 600 ps 0 0.6 1.0 ns ns tSKD Differential Skew |tPHLD − tPLHD| tSK1 Channel-to-Channel Skew (Note 5) tTLH Rise Time 0.5 2.0 tTHL Fall Time 0.5 2.0 ns tPHZ Disable Time High to Z 10 15 ns tPLZ Disable Time Low to Z RL = 2 kΩ CL = 10 pF 10 15 ns tPZH Enable Time Z to High (Figure 3 and Figure 4) 4 10 ns tPZL Enable Time Z to Low 4 10 ns Min Typ Max Units 1.0 3.40 6.0 ns 1.0 3.48 6.0 ns 0 0.08 1.2 ns 0 0.6 1.5 ns Switching Characteristics VCC = +5.0V ± 10%, TA = −40˚C to +85˚C (Notes 3, 4, 9) Symbol tPHLD Differential Propagation Delay High to Low Parameter tPLHD Differential Propagation Delay Low to High Conditions CL = 5 pF VID = 200 mV (Figure 1 and Figure 2) tSKD Differential Skew |tPHLD − tPLHD| tSK1 Channel-to-Channel Skew (Note 5) tSK2 Chip to Chip Skew (Note 6) tTLH Rise Time tTHL Fall Time tPHZ Disable Time High to Z tPLZ tPZH tPZL Enable Time Z to Low 5.0 ns 0.5 2.5 ns 0.5 2.5 ns 10 20 ns Disable Time Low to Z RL = 2 kΩ CL = 10 pF 10 20 ns Enable Time Z to High (Figure 3 and Figure 4) 4 15 ns 4 15 ns Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified. Note 3: All typicals are given for: VCC = +5.0V, TA = +25˚C. Note 4: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN and tr and tf ≤ 6 ns for EN or EN*. Note 5: Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with an event on the inputs. Note 6: Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. Note 7: ESD Rating: HBM (1.5 kΩ, 100 pF) ≥ 2kV EIAJ (0Ω, 200 pF) ≥ 250V Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. Note 9: CL includes probe and jig capacitance. Parameter Measurement Information DS100990-3 FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit 3 www.national.com Parameter Measurement Information (Continued) DS100990-4 FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms DS100990-5 CL includes load and test jig capacitance. S1 = VCC for tPZL and tPLZ measurements. S1 = GND for tPZH and tPHZ measurements. FIGURE 3. Receiver TRI-STATE Delay Test Circuit DS100990-6 FIGURE 4. Receiver TRI-STATE Delay Waveforms www.national.com 4 Typical Application DS100990-7 FIGURE 5. Point-to-Point Application levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. Applications Information LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 5. This configuration provides a clean signaling environment for the quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90C032B differential line receiver is capable of detecting signals as low as 100 mV, over a ± 1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ± 1V around this center point. The ± 1V shifting may be the result of a ground potential difference between the driver’s ground reference and the receiver’s ground reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground), exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages. Receiver Fail-Safe: The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic The receiver’s internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating or terminated receiver inputs. 1. Open Input Pins. The DS90C032B is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs. 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable. The footprint of the DS90C032B is the same as the industry standard 26LS32 Quad Differential (RS-422) Receiver. For additional LVDS application information, please refer to National’s LVDS Owner’s Manual available through National’s website www.national.com/appinfo/lvds. 5 www.national.com Pin Descriptions Pin No. Name Description 2, 6, 10, 14 RIN+ Non-inverting receiver input pin 1, 7, 9, 15 RIN− Inverting receiver input pin 3, 5, 11, 13 ROUT Receiver output pin 4 EN Pin No. Name Description 12 EN* Active low enable pin, OR-ed with EN 16 VCC Power supply pin, +5V ± 10% 8 GND Ground pin Ordering Information Active high enable pin, OR-ed with EN* Operating Package Type/ Temperature Number −40˚C to +85˚C SOP/M16A Order Number DS90C032BTM Typical Performance Characteristics Output High Voltage vs Power Supply Voltage Output High Voltage vs Ambient Temperature DS100990-8 Output Low Voltage vs Power Supply Voltage DS100990-9 Output Low Voltage vs Ambient Temperature DS100990-10 www.national.com DS100990-11 6 Typical Performance Characteristics (Continued) Output Short Circuit Current vs Power Supply Voltage Output Short Circuit Current vs Ambient Temperature DS100990-12 Differential Propagation Delay vs Power Supply Voltage DS100990-13 Differential Propagation Delay vs Ambient Temperature DS100990-14 Differential Skew vs Power Supply Voltage DS100990-15 Differential Skew vs Ambient Temperature DS100990-17 DS100990-16 7 www.national.com Typical Performance Characteristics (Continued) Transition Time vs Power Supply Voltage Transition Time vs Ambient Temperature DS100990-18 www.national.com DS100990-19 8 DS90C032B LVDS Quad CMOS Differential Line Receiver Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC Order Number DS90C032BTM NS Package Number M16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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