IP4777CZ38 DVI and HDMI interface ESD protection, DDC buffering, hot plug control and backdrive protection Rev. 02 — 12 February 2009 Product data sheet 1. General description The IP4777CZ38 is designed for HDMI transmitter host interface protection. The IP4777CZ38 includes DDC buffering and decoupling, hot plug detect, backdrive protection, CEC slew rate control, and high-level ESD protection diodes for the TMDS lines. The DDC lines use a new buffering concept which decouples the internal capacitive load from the external capacitive load. This allows greater design flexibility of the DDC lines with respect to the maximum load of 50 pF specified in the HDMI 1.3 specification. This buffering also boosts the DDC signals, allowing the use of longer HDMI cables having a higher capacitive load than 700 pF. The CEC slew rate limiter prevents ringing on the CEC line. The internal hot plug detect module simplifies the application of the HDMI transmitter to control the hot plug signal. The DDC, hot plug and CEC lines are backdrive protected to guarantee HDMI interface signals are not pulled down if the system is powered down or enters standby mode. All TMDS intra-pairs are protected by a special diode configuration offering a low line capacitance of 0.7 pF only (to ground) and 0.05 pF between the TMDS pairs. These diodes provide protection to components downstream from ESD voltages of up to ±8 kV contact in accordance with the IEC 61000-4-2, level 4 standard. 2. Features n n n n n n n n n n HDMI 1.3 compliant Pb-free and RoHS compliant; Dark Green Robust ESD protection without degradation after several ESD strikes Low leakage even after several hundred ESD discharges Very high diode switching speed (ns) and low line capacitance of 0.7 pF to ground and 0.05 pF between channel can ensure signal integrity DDC capacitive decoupling between system side and HDMI connector side and buffering to drive cable with high capacitive load (> 700 pF) Hot plug detect module CEC ringing prevention by slew rate limiter All TMDS lines with integrated rail-to-rail clamping diodes with downstream ESD protection of ±8 kV in accordance with IEC 61000-4-2, level 4 standard Matched 0.5 mm trace spacing IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection n Highest integration in a small footprint, PCB-level, optimized RF routing, 38-pin TSSOP lead-free package 3. Applications n The IP4777CZ38 can be used for a wide range of HDMI source devices, consumer and computing electronics e.g.: u SD and HD DVD player u Set-top box u PC graphic card u Game console u HDMI picture performance quality enhancer module 4. Ordering information Table 1. Ordering information Type number IP4777CZ38 IP4777CZ38/V Package Name Description Version TSSOP38 plastic thin shrink small outline package: 38 leads; body width 4.4 mm; lead pitch 0.5 mm SOT510-1 IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 2 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 5. Functional diagram TMDS_D2+ TMDS_D1+ TMDS_BIAS TMDS_D0+ TMDS_CLK+ VCC(5V0) TMDS_D2− TMDS_D1− TMDS_GND VCC(5V0) TDMS_BIAS TMDS_D0− TMDS_BIAS TMDS_CLK− VCC(5V0) SLEW RATE ACCELERATOR HOT_PLUG_DET_OUT HOT_PLUG_DET_IN ENABLE DDC_CLK_OUT 10 µA TMDS_BIAS DDC_CLK_IN VCC(3V3) TMDS_BIAS VCC(5V0) SLEW RATE ACCELERATOR CEC_OUT CEC_IN ENABLE DDC_DAT_OUT DDC_DAT_IN SLEW RATE LIMITER 001aah525 Fig 1. Functional diagram IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 3 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 6. Pinning information 6.1 Pinning VCC(5V0) 1 38 TMDS_BIAS ENABLE 2 37 VCC(3V3) GND 3 36 GND TMDS_D2+ 4 35 n.c. n.c. 5 34 TMDS_D2− TMDS_GND 6 33 TMDS_GND TMDS_D1+ 7 32 n.c. n.c. 8 31 TMDS_D1− TMDS_GND 9 30 TMDS_GND IP4777CZ38 TMDS_D0+ 10 n.c. 11 29 n.c. 28 TMDS_D0− TMDS_GND 12 27 TMDS_GND TMDS_CLK+ 13 26 n.c. n.c. 14 25 TMDS_CLK− TMDS_GND 15 24 TMDS_GND CEC_IN 16 23 CEC_OUT DDC_CLK_IN 17 22 DDC_CLK_OUT DDC_DAT_IN 18 21 DDC_DAT_OUT HOT_PLUG_DET_IN 19 20 HOT_PLUG_DET_OUT 001aah465 Fig 2. Pin configuration IP4777CZ38 VCC(5V0) 1 38 TMDS_BIAS ENABLE 2 37 VCC(3V3) GND 3 36 GND TMDS_D2+ 4 35 n.c. TMDS_GND 5 34 TMDS_GND n.c. 6 33 TMDS_D2− TMDS_D1+ 7 32 n.c. TMDS_GND 8 31 TMDS_GND n.c. 9 TMDS_D0+ 10 30 TMDS_D1− IP4777CZ38/V TMDS_GND 11 29 n.c. 28 TMDS_GND n.c. 12 27 TMDS_D0− TMDS_CLK+ 13 26 n.c. TMDS_GND 14 25 TMDS_GND n.c. 15 24 TMDS_CLK− CEC_IN 16 23 CEC_OUT DDC_CLK_IN 17 22 DDC_CLK_OUT DDC_DAT_IN 18 21 DDC_DAT_OUT HOT_PLUG_DET_IN 19 20 HOT_PLUG_DET_OUT 001aah466 Fig 3. Pin configuration IP4777CZ38/V IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 4 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 6.2 Pin description Table 2. Pin description Symbol Pin Description IP4777CZ38 IP4777CZ38/V[1] VCC(5V0) 1 1 supply voltage for DDC and hot plug circuits ENABLE 2 2 enable input for DDC and hot plug circuits GND 3 3 ground for DDC, hot plug and CEC circuits TMDS_D2+ 4 4 ESD protection TMDS channel D2+ n.c. 5 6 not connected TMDS_GND 6 5 ground for TMDS channel TMDS_D1+ 7 7 ESD protection TMDS channel D1+ n.c. 8 9 not connected TMDS_GND 9 8 ground for TMDS channel TMDS_D0+ 10 10 ESD protection TMDS channel D0+ n.c. 11 12 not connected TMDS_GND 12 11 ground for TMDS channel TMDS_CLK+ 13 13 ESD protection TMDS channel CLK+ n.c. 14 15 not connected TMDS_GND 15 14 ground for TMDS channel CEC_IN 16 16 CEC signal input to system controller DDC_CLK_IN 17 17 DDC clock input to system controller DDC_DAT_IN 18 18 DDC data input to system controller HOT_PLUG_DET_IN 19 19 hot plug detect input from system GPIO HOT_PLUG_DET_OUT 20 20 hot plug detect output to HDMI connector DDC_DAT_OUT 21 21 DDC data output to HDMI connector DDC_CLK_OUT 22 22 DDC clock output to HDMI connector CEC_OUT 23 23 CEC signal output to HDMI connector TMDS_GND 24 25 ground for TMDS channel TMDS_CLK− 25 24 ESD protection TMDS channel CLK− n.c. 26 26 not connected TMDS_GND 27 28 ground for TMDS channel TMDS_D0− 28 27 ESD protection TMDS channel D0− n.c. 29 29 not connected TMDS_GND 30 31 ground for TMDS channel TMDS_D1− 31 30 ESD protection TMDS channel D1− n.c. 32 32 not connected TMDS_GND 33 34 ground for TMDS channel TMDS_D2− 34 33 ESD protection TMDS channel D2− n.c. 35 35 not connected IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 5 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection Table 2. Pin description …continued Symbol Pin Description IP4777CZ38 IP4777CZ38/V[1] GND 36 36 ground for DDC, hot plug and CEC circuits VCC(3V3) 37 37 supply voltage for CEC circuit TMDS_BIAS 38 38 bias input for TMDS ESD protection. This pin must be connected to a 0.1 µF capacitor. [1] Type number IP4777CZ38/V is pin compatible with type number IP4776CZ38. 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VCC supply voltage VI input voltage VESD electrostatic discharge voltage Ptot total power dissipation Tstg storage temperature Max Unit GND − 0.5 5.5 V GND − 0.5 5.5 V connector side pins (to ground); IEC 61000-4-2, level 4 (contact) [1] −8 +8 kV board side pins; IEC 61000-4-2, level 1 (contact) [2] −2 +2 kV - 14 mW −55 +125 °C input pins DDC operating at 100 kHz [1] Connector side pins: TMDS_D2+, TMDS_D2−, TMDS_D1+, TMDS_D1−, TMDS_D0+, TMDS_D0− TMDS_CLK+, TMDS_CLK− CEC_OUT DDC_DAT_OUT and DDC_CLK_OUT HOT_PLUG_DET_OUT [2] Board side pins: CEC_IN DDC_DAT_IN and DDC_CLK_IN HOT_PLUG_DET_IN ENABLE IP4777CZ38_2 Product data sheet Min © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 6 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 8. Static characteristics Table 4. TMDS protection circuit Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VBRzd Zener diode breakdown voltage I = 1 mA 6 - 9 V Rdyn dynamic resistance I = 1 A; IEC 61000-4-5/9 positive transient - 2.4 - Ω negative transient - 1.3 - Ω Zener diode Protection diode Ibck back current from pins TMDS_x to pin TMDS_BIAS; VCC(5V0) = 0 V; VCC(3V3) = 0 V - 0.1 1 µA IL(r) reverse leakage current VI = 3.0 V - 1 - µA VF forward voltage - 0.7 - V VCL(ch)trt(pos) positive transient channel clamping voltage - 8 - V VESD = 8 kV per IEC 61000-4-2; voltage 30 ns after trigger TMDS channel: pins TMDS_x TMDS channel capacitance Cch(TMDS) VCC(5V0) = 5 V; f = 1 MHz; Vbias = 2.5 V [1] - 0.7 - pF VCC(5V0) = 5 V; f = 1 MHz; Vbias = 2.5 V [1] - 0.05 - pF [1] - 0.07 - pF ∆Cch(TMDS) TMDS channel capacitance difference Cch(mutual) mutual channel capacitance between signal pin TMDS_x and pin n.c.; VCC(5V0) = 0 V; f = 1 MHz; Vbias = 2.5 V [1] This parameter is guaranteed by design. Table 5. DDC circuit VCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies: pins VCC(5V0) and VCC(3V3) VCC(5V0) supply voltage (5.0 V) connector side 4.5 5.0 5.5 V VCC(3V3) supply voltage (3.3 V) board side 2.7 3.3 5.5 V ICC(5V0) supply current (5.0 V) VCC(5V0) = 5.5 V; both channels HIGH: DDC_DAT_OUT = VCC(5V0); DDC_CLK_OUT = VCC(5V0) - 1.4 2.5 mA VCC(5V0) = 5.5 V; both channels LOW: DDC_DAT_IN = GND; DDC_CLK_IN = GND; DDC_DAT_OUT = open; DDC_CLK_OUT = open - 1.4 2.5 mA no pull-up resistor connected to VCC(3V3) - - 0.1 µA ICC(3V3) supply current (3.3 V) IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 7 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection Table 5. DDC circuit …continued VCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Board side: pins DDC_CLK_IN and DDC_DAT_IN Used as input VIH HIGH-level input voltage - 410 - mV VIL LOW-level input voltage - 400 - mV IIL LOW-level input current VI = 0.2 V - - 70 µA VIK input clamping voltage II = −18 mA - - −1.2 V ILI input leakage current VI = 3.6 V - - ±1 µA Ci input capacitance VI = 3 V or 0 V VCC(3V3) = 3.3 V - 6 7 pF VCC(3V3) = 3.0 V - 6 7 pF Used as output VOL LOW-level output voltage IOL = 100 µA or 3 mA - 700 - mV IOH HIGH-level output current VO = 3.6 V - - 10 µA Co output capacitance VI = 3 V or 0 V VCC(3V3) = 3.3 V - 6 7 pF VCC(3V3) = 3.0 V - 6 7 pF Connector side: pins DDC_CLK_OUT and DDC_DAT_OUT Used as input VIH HIGH-level input voltage 0.7 × VCC(5V0) - 5.5 V VIL LOW-level input voltage −0.5 - 0.3 × VCC(5V0) V IIL LOW-level input current VI = 0.2 V - - 1 µA VIK input clamping voltage II = −18 mA - - −1.2 V ILI input leakage current VI = 3.6 V - - ±1 µA Ci input capacitance VI = 3 V or 0 V VCC(3V3) = 3.3 V - 8 10 pF VCC(3V3) = 3.0 V - 8 10 pF Used as output VOL LOW-level output voltage IOL = 100 µA or 6 mA - 200 - mV IOH HIGH-level output current VO = 3.6 V - - 10 µA Co output capacitance VI = 3 V or 0 V VCC(3V3) = 3.3 V - 8 10 pF VCC(3V3) = 3.0 V - 8 10 pF IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 8 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection Table 6. CEC circuit VCC(3V3) = 2.7 V o 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit - 14 16 pF Board side: input pin CEC_IN [1] CI(ch-GND)(levsh) level shifting input capacitance from channel to ground VCC(3V3) = 0 V; f = 1 MHz; Vbias = 2.5 V SRr rising slew rate VI > 1.8 V - 10 - mV/µs on-state voltage drop N-FET state = on; VCC(3V3) = 2.5 V; VS = GND; IDS = 3 mA - 125 140 mV - - 0.1 µA positive transient - 2.4 - Ω negative transient - 1.3 - Ω - 8 - V N-FET ∆Von Connector side: output pin CEC_OUT ILO output leakage current Vbias = 3.6 V Rdyn dynamic resistance I = 1 A; IEC 61000-4-5/9 VCL(ch)trt(pos) [1] positive transient channel clamping voltage VESD = 8 kV per IEC 61000-4-2; voltage 30 ns after trigger; Tamb = 25 °C This parameter is guaranteed by design. Table 7. Enable circuit VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Board side: input pin ENABLE[1] VIH HIGH-level input voltage HIGH = enable 0.7 × VCC(3V3) - VCC(3V3) + 0.5 V VIL LOW-level input voltage LOW = disable −0.5 - 0.3 × VCC(3V3) V IIL LOW-level input current VI = 0.2 V; VCC(3V3) = 5.5 V - 10 - µA ILI input leakage current Vbias = 3.6 V −1 +0.1 +1 µA Ci input capacitance VI = 3 V or 0 V - 3 7 pF [1] The ENABLE pin has to be connected permanently to VCC(3V3) if no enable control is needed. Table 8. Hot plug control circuit VCC(5V0) = 4.5 V to 5.5 V; VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Board side: input pin HOT_PLUG_DET_OUT VIH HIGH-level input voltage - 1.9 - V VIL LOW-level input voltage - 200 - mV IIL LOW-level input current pull-down current to ground; VI = 2 V; VCC(5V0) = 5.5 V - 10 - µA Ci input capacitance VI = 3 V or 0 V - 6 7 pF IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 9 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection Table 8. Hot plug control circuit …continued VCC(5V0) = 4.5 V to 5.5 V; VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max - VCC(3V3) - Unit Connector side: output pin HOT_PLUG_DET_IN HIGH-level output voltage VIH V 9. Dynamic characteristics Table 9. DDC circuits VCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Board side to connector side; see Figure 4 Pins DDC_CLK_IN to DDC_CLK_OUT and DDC_DAT_IN to DDC_DAT_OUT tPLH tPHL LOW-to-HIGH propagation delay [1] 275 300 325 ns HIGH-to-LOW propagation delay [1] 195 210 225 ns 90 110 130 ns 1 3 5 ns 110 130 150 ns 20 30 40 ns Pins DDC_CLK_OUT and DDC_DAT_OUT LOW to HIGH transition time tTLH RL =1.35 kΩ; CL = 50 pF [1] HIGH to LOW transition time tTHL Connector side to board side; see Figure 5 Pins DDC_CLK_OUT to DDC_CLK_IN and DDC_DAT_OUT to DDC_DAT_IN LOW-to-HIGH propagation delay tPLH [1] HIGH-to-LOW propagation delay tPHL Pins DDC_CLK_IN and DDC_DAT_IN LOW to HIGH transition time tTLH HIGH to LOW transition time tTHL 100 120 140 ns [1] 2 3 5 ns Enable: pin ENABLE tsu set-up time pin ENABLE = HIGH before start condition [2] 100 - - ns th hold time pin ENABLE = HIGH after stop condition [2] 100 - - ns [1] Typical values are measured at VCC(3V3) = 3.3 V, VCC(5V0) = 5.0 V and Tamb = 25 °C. [2] The ENABLE pin should only change when the DDC bus is in an idle state. IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 10 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 3.3 V input: board side 0.7 V 5.0 V tPLH output: connector side 1.5 V 001aah611 a. Propagation delay tPLH input: board side 3.3 V 1.65 V 0.1 V output: connector side tPHL tPLH 5.0 V 80 % (1) 2.5 V 0.3VCC(5V0) 20 % VOL tTHL tTLH 001aah612 (1) Dotted line indicates effect without slew rate accelerator. b. Propagation delay tPHL and transition time Fig 4. Board side to connector side operation IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 11 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection input: connector side 5.0 V 0.3VCC(5V0) tPHL output: board side VOL tPLH 3.3 V 80 % 1.65 V 20 % VIL tTHL tTLH 001aah613 Propagation delay output to input and transition time input Fig 5. Connector side to board side operation IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 12 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 10. Application information 10.1 TMDS To protect the TMDS lines and also to comply with the impedance requirements of the HDMI specification, the IP4777CZ38 provides ESD protection with a low capacitive load. The dominant value for the TMDS line impedance is the capacitive load to ground. The IP4777CZ38 has a capacitive load of only 0.7 pF. TMDS_D2+ TMDS_D1+ TMDS_BIAS TMDS_D0+ TMDS_CLK+ VCC(5V0) TMDS_D2− TMDS_D1− TMDS_GND TMDS_D0− TMDS_CLK− 001aag039 Fig 6. ESD protection of TMDS lines 10.2 DDC circuit The DDC bus circuit contains full capacitive decoupling between the HDMI connector and the DDC bus lines on the PCB. The capacitive decoupling ensures that the maximum capacitive load is within the 50 pF maximum of the HDMI specification. The slew rate accelerator supports high capacitive load on the HDMI cable side. Various HDMI cable suppliers produce low-cost and long (typically 25 m) HDMI cables with a capacitive load of up to 6 nF. The slew rate accelerator boosts the DDC signal independent of which side of the bus is releasing the signal. The DDC circuit provides a level shifting option. The ENABLE signal is enabling and disabling the complete DDC buffer. TMDS_BIAS VCC(5V0) TMDS_BIAS SLEW RATE ACCELERATOR VCC(5V0) SLEW RATE ACCELERATOR ENABLE DDC_CLK_OUT ENABLE DDC_DAT_OUT DDC_CLK_IN DDC_DAT_IN 001aag040 a. DDC clock Fig 7. 001aag041 b. DDC data DDC circuit IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 13 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 5.0 V (1) (1) 0.3VCC(5V0) 001aag042 (1) Dotted line indicates effect without slew rate accelerator. Fig 8. DDC output waveform 10.3 Hot plug detect circuit The IP4777CZ38 includes a hot plug detect circuit that simplifies the hot plug application. The circuit generates a standard logic level from the hot plug signal. The hot plug detect circuit is pulling down the signal to avoid any floating signal. The comparator guarantees a save detection of the 2 V hot plug signal without any glitches and oscillation at the hot plug output. VCC(5V0) TDMS_BIAS HOT_PLUG_DET_OUT HOT_PLUG_DET_IN 10 µA 001aah467 Fig 9. Hot plug detect circuit 10.4 CEC The CEC signal can generate distortions caused by signal ringing in a 1 kHz domain. The CEC slew rate limiter ensures that a signal does not ring independently of the CEC slave that is releasing the signal. A MOSFET transistor implements the backdrive protection which blocks signals in a power-down state. The slew rate of the CEC bus is controlled by a slew rate that is defined independently of the load (resistive and capacitive) at the CEC bus. IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 14 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection TMDS_BIAS VCC(3V3) CEC_OUT CEC_IN SLEW RATE LIMITER 001aag044 Fig 10. CEC module (1) (1) 0.8 V 001aag045 (1) Dotted line indicates effect without slew rate limiter. Fig 11. CEC output waveform 10.5 Backdrive protection The HDMI contains various signals which can partly supply current into an HDMI device that is powered down. Typically, the DDC lines and the CEC signals can force 5 V into the switched off device. The IP4777CZ38 ensures that at power-down, the critical signals are blocked to prevent any damage to the HDMI sink and HDMI source. supply off 5V HDMI source HDMI sink backdrive current HDMI ASIC I2C-bus ASIC 001aag047 Fig 12. Backdrive protection IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 15 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 10.6 Schematic view of application Only a few external components are needed at the application to adapt the HDMI port to the parameters of the HDMI transmitter device. VCC(5V0) VCC(3V3) 100 kΩ 1.5 kΩ +5.7 V 1.5 kΩ 27 kΩ 1.5 kΩ 1.5 kΩ 500 mA HDMI CONNECTOR ENABLE 1 2 37 TMDS_D2+ TMDS_D2− 4 5 35 34 TMDS_D2+ TMDS_D2− TMDS_D1+ TMDS_D1− 7 8 32 31 TMDS_D1+ TMDS_D1− TMDS_D0+ TMDS_D0− 10 11 12 13 14 29 28 TMDS_D0+ TMDS_D0− 26 25 TMDS_CLK+ TMDS_CLK− IP4777CZ38 TMDS_CLK+ TMDS_CLK− CEC_IN DDC_CLK_IN DDC_DAT_IN HOT_PLUG_DET_IN 16 23 17 22 18 21 19 20 3, 6, 9, 12, 15, 24, 27, 30, 33, 36 CEC DDC_CLK DDC_DAT HOTPLUG_DET +5 V 001aah759 Fig 13. Schematic view of IP4777CZ38 application IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 16 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 10.7 Typical application The optimized pinning variant simplifies the printed-circuit board design. The pinning optimizes the design of the microstrip lines for defined impedance. Underneath the device a solid ground plane is part of the microstrip lines. This application requires only a few external components to adapt the HDMI port to the parameters of the HDMI transmitter device or HDMI multiplexer. VCC(5V0) ENABLE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 TMDS_D2+ TMDS_D2− GND TMDS_D1+ TMDS_D1− GND TMDS_D0+ TMDS_D0− GND TMDS_CLK+ TMDS_CLK− GND CEC_IN DDC_CLK_IN DDC_DAT_IN HOT_PLUG_DET_IN IP4777CZ38 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 VCC(3V3) 1 board side 19 TMDS_D2+ TMDS_GND TMDS_D2− TMDS_D1+ TMDS_GND TMDS_D1− TMDS_D0+ TMDS_GND TMDS_D0− TMDS_CLK+ TMDS_GND TMDS_CLK− CEC n.c. DDC_CLK DDC_DAT GND +5 V HOT_PLUG_DET HDMI connector Rdata 1.5 kΩ Rclock 1.5 kΩ RCEC 100 kΩ RCEC 27 kΩ Rclock 47 kΩ +3.3 V Rdata 47 kΩ +5.0 V +5.7 V CHP 100 nF 001aah469 Fig 14. Application of the IP4777CZ38 showing optimized PCB microstrip lines IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 17 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 11. Test information VCC(3V3) VCC(5V0) VCC RL G VI DUT Rterm VO CL 001aah468 See Table 10 for test data. Rterm = termination resistance should be equal to output impedance Zo of the pulse generator. RL = load resistance. CL = load capacitance. Fig 15. Test circuit for DDC and CEC lines Table 10. Test data Test RL CL DDC lines 1.35 kΩ 50 pF VCC(5V0) CEC line 27 kΩ 50 pF VCC(3V3) IP4777CZ38_2 Product data sheet VCC © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 18 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 12. Package outline TSSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm; lead pitch 0.5 mm SOT510-1 E D A X c HE y v M A Z 20 38 A2 (A 3) A A1 pin 1 index θ Lp L 1 19 bp e detail X w M 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.85 0.25 0.27 0.17 0.20 0.09 9.8 9.6 4.5 4.3 0.5 6.4 1 0.7 0.5 0.2 0.08 0.08 0.49 0.21 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT510-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 03-02-18 05-11-02 Fig 16. Package outline SOT510-1 (TSSOP38) IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 19 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 20 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 17) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12 Table 11. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 12. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 17. IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 21 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 17. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 13. Abbreviations Acronym Description ASIC Application Specific Integrated Circuit CEC Consumer Electronic Control DDC Data Display Channel DVD Digital Versatile Disc ESD ElectroStatic Discharge FET Field-Effect Transistor GPIO General Purpose Input Output HD High Definition HDMI High Definition Multimedia Interface MOSFET Metal-Oxide Semiconductor Field Effect Transistor RoHS Restriction of the use of certain Hazardous Substances SD Standard Definition TMDS Transition Minimized Differential Signaling 15. Glossary HDMI sink — Device which receives HDMI signals e.g. a TV set. HDMI source — Device which transmit HDMI signal e.g. DVD player. IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 22 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 16. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes IP4777CZ38_2 20090212 Product data sheet - IP4777CZ38_1 Modifications: IP4777CZ38_1 • • • • • • Table 3: updated value of Ptot. Table 5: updated values. Table 6: updated values. Table 7: updated values. Table 8: updated values and removed last four rows. Table 9: updated values. 20080415 Objective data sheet IP4777CZ38_2 Product data sheet - - © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 23 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.4 Licenses Purchase of NXP ICs with HDMI technology Use of an NXP IC with HDMI technology in equipment that complies with the HDMI standard requires a license from HDMI Licensing LLC, 1060 E. Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail: [email protected]. 17.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] IP4777CZ38_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 12 February 2009 24 of 25 IP4777CZ38 NXP Semiconductors DVI and HDMI interface ESD protection 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 17.5 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Application information. . . . . . . . . . . . . . . . . . 13 TMDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DDC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hot plug detect circuit . . . . . . . . . . . . . . . . . . . 14 CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Backdrive protection . . . . . . . . . . . . . . . . . . . . 15 Schematic view of application. . . . . . . . . . . . . 16 Typical application. . . . . . . . . . . . . . . . . . . . . . 17 Test information . . . . . . . . . . . . . . . . . . . . . . . . 18 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Soldering of SMD packages . . . . . . . . . . . . . . 20 Introduction to soldering . . . . . . . . . . . . . . . . . 20 Wave and reflow soldering . . . . . . . . . . . . . . . 20 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 20 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23 Legal information. . . . . . . . . . . . . . . . . . . . . . . 24 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact information. . . . . . . . . . . . . . . . . . . . . 24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 February 2009 Document identifier: IP4777CZ38_2