INTEGRATED CIRCUITS DATA SHEET TEA6323T Sound fader control circuit Preliminary specification File under Integrated Circuits, IC01 1995 Dec 20 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T FEATURES • Source selector for three stereo and one differential stereo input for remote sources • The differential stereo input works optional as a fourth stereo input and the common mode pin can be used as well as an additional mono input • Interface for noise reduction circuits • Fast mute control via pin • Interface for external equalizer • I2C-bus control for all functions • Volume, balance and fader control • Power supply with internal power-on reset • Output at volume I for external booster • Power down indication. • Special loudness characteristic automatically controlled in combination with volume setting GENERAL DESCRIPTION • Bass control with equalizer filters The sound fader control circuit TEA6323T is an I2C-bus controlled stereo preamplifier for car radio hi-fi sound applications. • Treble control • Mute control at audio signal zero crossing • Logic output to read mute status • Fast mute control via I2C-bus QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC supply voltage ICC supply current VCC = 8.5 V Vo(rms) maximum output voltage level VCC = 8.5 V; THD ≤ 0.1% − 2000 − mV Gv voltage gain −86 − +20 dB Gstep(vol) step resolution (volume) − 1 − dB Gbass bass control −18 − +18 dB Gtreble treble control −12 − +12 dB Gstep(treble) step resolution (treble) − 1.5 − dB (S+N)/N signal-plus-noise to noise ratio VO = 2.0 V; Gv = 0 dB; unweighted − 105 − dB RR100 ripple rejection − 75 − dB CMRR common mode rejection ratio differential stereo input 43 53 − dB Vr(rms) < 200 mV; f = 100 Hz; Gv = 0 dB 7.5 8.5 9.5 V − 26 − mA ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TEA6323T 1995 Dec 20 VSO40 DESCRIPTION plastic very small outline package; 40 leads 2 VERSION SOT158-1 3.4 kΩ CKVL 270 nF 5.6 nF 270 nF 4.7 kΩ 150 nF MUTE 220 nF 100 µF 11 13 12 10 9 8 7 2 Vref 26 MUTE FUNCTION ZERO CROSS DETECTOR 38 VCC 3 4 GND POWER SUPPLY VOLUME I +20 to −31 dB LOUDNESS LEFT 24 47 µF 9 x 220 nF BASS LEFT TREBLE LEFT ± 18 dB ± 12 dB 5 output left VOLUME II 0 to −55 dB BALANCE FADER FRONT 20 6 40 18 I2C-BUS RECEIVER LOGIC 16 1 SCL SDA 14 17 common mode input/ input mono source SOURCE SELECTOR VOLUME I +20 to −31 dB LOUDNESS RIGHT 27 BASS RIGHT TREBLE RIGHT ± 18 dB ± 12 dB VOLUME II 0 to −55 dB BALANCE FADER FRONT input right source 23 TEA6323T 21 CKIN 28 30 29 31 32 33 35 output right 25 VOLUME II 0 to −55 dB BALANCE FADER REAR 36 34 220 nF MHA258 150 nF 270 nF 270 nF 5.6 nF 3.4 kΩ 20 kΩ 2.2 kΩ Fig.1 Block diagram. OVR TEA6323T 8.2 nF Preliminary specification CKVL handbook, full pagewidth 3 input left source VOLUME II 0 to −55 dB BALANCE FADER REAR Philips Semiconductors 20 kΩ Sound fader control circuit 8.2 nF BLOCK DIAGRAM 1995 Dec 20 OVL +5V 2.2 kΩ Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T PINNING SYMBOL PIN DESCRIPTION SDA 1 serial data input/output MUTE 2 mute control input and output DGND 3 digital ground AGND 4 analog ground OUTLR 5 output left rear OUTLF 6 output left front TL 7 treble control capacitor left channel or input from an external equalizer B2L 8 bass control left channel or output to an external equalizer B1L 9 bass control, left channel OVL 10 output volume I, left channel IVL 11 input volume I, left control part ILL 12 input loudness, left control part QSL 13 output source selector, left channel IDL 14 input D left source i.c. 15 COMM, common mode rejection adjust, centre position ICL 16 input C left source COM 17 common mode input / mono source input IBL 18 input B left source i.c. 19 COML, common mode rejection adjust, left position IAL 20 input A differential source left IAR 21 input A differential source right i.c. 22 COMR, common mode rejection adjust, right position IBR 23 input B right source CAP 24 electronic filtering for supply ICR 25 input C right source Vref 26 reference voltage (0.5VCC) IDR 27 input D right source QSR 28 output source selector right channel ILR 29 input loudness right channel IVR 30 input volume I, right control part OVR 31 output volume I, right channel B1R 32 bass control right channel B2R 33 bass control right channel or output to an external equalizer TR 34 treble control capacitor right channel or input from an external equalizer OUTRF 35 output right front OUTRR 36 output right rear n.c. 37 not connected VCC 38 supply voltage n.c. 39 not connected SCL 40 serial clock input 1995 Dec 20 4 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T The volume control function is split into two sections: volume I control block and volume II control block. handbook, halfpage SDA 1 40 SCL MUTE 2 39 n.c. DGND 3 38 VCC AGND 4 37 n.c. OUTLR 5 36 OUTRR OUTLF 6 35 OUTRF TL 7 34 TR B2L 8 33 B2R B1L 9 32 B1R OVL 10 The control range of volume I is between +20 dB and −31 dB in steps of 1 dB. The volume II control range is between 0 dB and −55 dB in steps of 1 dB. Although the theoretical possible control range is 106 dB (+20 to −86 dB), in practice a range of 86 dB (+20 to −66 dB) is recommended. The gain/attenuation setting of the volume I control block is common for both channels. The volume I control block operates in combination with the loudness control. The filter is linear when the maximum gain for the volume I control (+20 dB) is selected. The filter characteristic increases automatically over a range of 32 dB down to a setting of −12 dB. That means the maximum filter characteristic is obtained at −12 dB setting of volume I. Further reduction of the volume does not further influence the filter characteristic (see Fig.5). The maximum selected filter characteristic is determined by external components. The proposed application gives a maximum boost of 17 dB for bass and 4.5 dB for treble. The loudness may be switched on or off via I2C-bus control (see Table 7). 31 OVR TEA6323T IVL 11 30 IVR ILL 12 29 ILR QSL 13 28 QSR IDL 14 27 IDR i.c. 15 26 Vref ICL 16 25 ICR The volume I control block has an output pin and is followed by the bass control block. An external filter for each channel in combination with internal resistors, provides the frequency response of the bass control (see Fig.3). The adjustable range is between −18 and +18 dB in steps of 1.8 dB at 46 Hz. 24 CAP COM 17 IBL 18 23 IBR i.c. 19 22 i.c. IAL 20 21 IAR Both, loudness and bass control result in a maximum bass boost of 35 dB for low volume settings. MHA257 Fig.2 Pin configuration. The treble control block offers a control range between −12 and +12 dB in steps of 1.5 dB at 15 kHz. The filter characteristic is determined by a single capacitor of 5.6 nF for each channel in combination with internal resistors (see Fig.4). FUNCTIONAL DESCRIPTION The source selector allows either the source selection between the differential stereo input (IAL, IAR and COM) and three stereo inputs, or selection of four stereo inputs and the mono input (COM). The maximum input signal voltage is Vi(rms) = 2 V. The outputs of the source selector and the inputs of the following volume control parts are available at pins 13 and 11 for the left channel and pins 28 and 30 for the right channel. This offers the possibility of interfacing a noise reduction system. The basic step width of treble control is 3 dB. The intermediate steps are obtained by switching 1.5 dB boost and 1.5 dB attenuation steps. The bass and treble control functions can be switched off via I2C-bus. In this event the internal signal flow is disconnected. The connections B2L and B2R are outputs and TL and TR are inputs for inserting an external equalizer. The volume control part is following the source selector. The signal phase from input volume control part to all outputs is 180°. 1995 Dec 20 5 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T The mute function can also be controlled externally. If the mute pin is switched to ground all outputs are muted immediately (except the outputs volume left and right (OVL and OVR) and hardware mute). This mute request overwrites all mute controls via the I2C-bus for the time the pin is held LOW. The hardware mute position is not stored in the TEA6323T. The last section of the circuit is the volume II block. The balance and fader functions are performed using the same control blocks. This is realized by 4 independently controllable attenuators, one for each output. The control range of these attenuators is 55 dB in steps of 1 dB with an additional mute step. The circuit provides 3 mute modes: The mute pin can also be used as output. The mute pin voltage is low when all outputs are in mute position. 1. Zero crossing mode mute via I2C-bus using 2 independent zero crossing detectors (ZCM, see Tables 2 and 9). For the turn on/off behaviour the following explanation is generally valid. To avoid AF output caused by the input signal coming from preceding stages, which produces output during drop of VCC, the mute has to be set, before the VCC will drop. This can be achieved by I2C-bus control or by grounding the MUTE pin. 2. Fast mute via MUTE pin. 3. Fast mute via I2C-bus either by general mute (GMU, see Tables 2 and 9) or volume II block setting (see Table 4). The mute function is performed immediately if ZCM is cleared (ZCM = 0). If the bit is set (ZCM = 1) the mute is activated after changing the GMU bit. The actual mute switching is delayed until the next zero crossing of the audio frequency signal. As the two audio channels (left and right) are independent, two comparators are built-in to control independent mute switches. For use where is no mute in the application before turn off, a supply voltage drop of more than 1 × VBE will result in a mute during the voltage drop. The power supply should include a VCC buffer capacitor, which provides a discharging time constant. If the input signal does not disappear after turn off the input will become audible after certain time. A 4.7 kΩ resistor discharges the VCC buffer capacitor, because the internal current of the IC does not discharge it completely. To avoid a large delay of mute switching when very low frequencies are processed or the output signal amplitude is lower than the DC offset voltage a second I2C-bus transmission is needed. Both transmissions have the same data and the second transmission a delay time of e.g. 100 ms. The first transmission starts the zero cross circuit, but second transmission moves the mute switch immediately if the circuit has no zero cross detected. The hardware mute function is favourable for use in Radio Data System (RDS) applications. The zero crossing mute avoids modulation plops. This feature is an advantage for mute during changing presets and/or sources (e.g. traffic announcement during cassette playback). LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 0 10 V Vn voltage at pins 1, 2 and 5 to 40 to pins 3 and 4 0 VCC V Tamb operating ambient temperature −40 +85 °C Tstg storage temperature −65 +150 °C Ves electrostatic handling note 1 Note 1. Human body model: C = 100 pF; R = 1.5 kΩ; V ≥ 2 kV. Charge device model: C = 200 pF; R = 0 Ω; V ≥ 500 V. 1995 Dec 20 6 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T CHARACTERISTICS VCC = 8.5 V; RS = 600 Ω; RL = 10 kΩ; CL = 2.5 nF; AC coupled; f = 1 kHz; Tamb = 25 °C; gain control Gv = 0 dB; bass linear; treble linear; fader off; balance in mid position; loudness off; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC supply voltage 7.5 8.5 9.5 V ICC supply current − 26 33 mA VDC internal DC voltage at inputs and outputs 3.83 4.25 4.68 V Vref internal reference voltage at pin 26 − 4.25 − V Gv(max) maximum voltage gain 19 20 21 dB Vo(rms) output voltage level for RS = 0 Ω; RL = ∞ Pmax at the power output stage THD ≤ 0.5%; see Fig.10 − 2000 − mV start of clipping THD = 1%; Gv = 3 dB 2300 − − mV RL = 2 kΩ; CL = 10 nF; THD = 1% 2000 − − mV 200 − mV − − Hz Vi(rms) input sensitivity Vo = 2000 mV; Gv = 20 dB − fro roll-off frequency CKIN = 220 nF; CKVL = 220 nF; Zi = Zi(min) low frequency (−1 dB) 60 low frequency (−3 dB) 30 − − Hz high frequency (−1 dB) 20000 − − Hz CKIN = 470 nF; CKVL = 100 nF; Zi = Zi(typ) low frequency (−3 dB) 17 − − Hz 74 80 − dB 0.1 − % αcs channel separation Vi = 2 V; frequency range 250 Hz to 10 kHz THD total harmonic distortion frequency range 20 Hz to 12.5 kHz Vi = 100 mV; Gv = 20 dB − RR 1995 Dec 20 ripple rejection Vi = 1 V; Gv = 0 dB − 0.05 0.1 % Vi = 2 V; Gv = 0 dB − 0.1 − % Vi = 2 V; Gv = −10 dB − 0.1 − % f = 100 Hz 70 76 − dB f = 40 Hz to 12.5 kHz − 66 − dB Vr(rms) < 200 mV 7 Philips Semiconductors Preliminary specification Sound fader control circuit SYMBOL (S+N)/N TEA6323T PARAMETER signal-plus-noise to noise ratio CONDITIONS MIN. TYP. MAX. UNIT − 105 − dB Gv = 0 dB − 95 − dB Gv = 12 dB − 88 − dB Gv = 20 dB − 81 − dB Gv = 0 dB − 90 − dB Gv = 20 dB − 79 − dB 43 53 − dB unweighted; 20 Hz to 20 kHz (RMS); Vo = 2.0 V; see Figs 6 and 7 CCIR468-2 weighted; quasi peak; Vo = 2.0 V differential input CMRR common mode rejection ratio differential stereo input Pno(rms) noise output power (RMS value) only contribution of TEA6323T; power amplifier for 6 W mute position; note 1 − − 10 nW αct crosstalk V bus ( p – p ) 20 log -------------------------- between bus V o ( rms ) note 2 − 110 − dB 25 35 45 kΩ − 105 − dB inputs and signal outputs Source selector Zi input impedance αS input isolation of one selected source to any other input f = 1 kHz f = 12.5 kHz − 95 − dB Vi(rms) maximum input voltage (RMS value) THD < 0.5%; VCC = 8.5 V − 2.15 − V THD < 0.5%; VCC = 7.5 V − 1.8 − V by selection of any stereo inputs − − 10 mV by selection of differential input or mono input − − 20 mV Voffset DC offset voltage at source selector output Zo output impedance − 80 120 Ω RL output load resistance 10 − − kΩ CL output load capacity 0 − 2500 pF Gv voltage gain, source selector − 0 − dB 100 150 200 kΩ Control part (source selector disconnected; source resistance 600 Ω) Zi input impedance volume input input impedance loudness input 25 33 40 kΩ Zo output impedance − 80 120 Ω RL output load resistance 2 − − kΩ CL output load capacity 0 − 10 nF 1995 Dec 20 8 Philips Semiconductors Preliminary specification Sound fader control circuit SYMBOL PARAMETER TEA6323T CONDITIONS Vi(rms) maximum input voltage (RMS value) THD < 0.5% Vno noise output voltage CCIR468-2 weighted; quasi peak CRtot Gstep ∆Ga MIN. TYP. MAX. UNIT − 2.15 − V Gv = 20 dB − 110 220 µV Gv = 0 dB − 33 50 µV Gv = −66 dB − 13 22 µV mute position − 10 − µV total continuous control range − 106 − dB recommended control range − 86 − dB step resolution − 1 − dB step error between any adjoining step − − 0.5 dB attenuator set error Gv = +20 to −50 dB − − 2 dB Gv = −51 to −66 dB − − 3 dB ∆Gt gain tracking error Gv = +20 to −50 dB − − 2 dB MUTEatt mute attenuation see Fig.9 100 110 − dB Voffset DC step offset between any adjoining step Gv = 0 to −66 dB − 0.2 10 mV Gv = 20 to 0 dB − 2 15 mV DC step offset between any step to mute Gv = 0 to −66 dB − − 10 mV Gv = 20 to 0 dB − − 40 mV Gv = 0 to −31 dB; loudness on − − 17 mV Volume I control and loudness CRvol continuous volume control range − 51 − dB Gv voltage gain −31 − +20 dB Gstep step resolution − 1 − dB LBmax maximum loudness boost f = 40 Hz − 17 − dB f = 10 kHz − 4.5 − dB loudness on; referred to loudness off; boost is determined by external components Bass control Gbass Gstep Voffset 1995 Dec 20 bass control, maximum boost f = 46 Hz 16 18 19 dB maximum attenuation f = 46 Hz 16 18 19 dB step resolution (toggle switching) f = 46 Hz − 1.8 − dB step error between any adjoining step f = 46 Hz − − 0.5 dB − − 20 mV DC step offset in any bass position 9 Philips Semiconductors Preliminary specification Sound fader control circuit SYMBOL PARAMETER TEA6323T CONDITIONS MIN. TYP. MAX. UNIT Treble control Gtreble Gstep Voffset treble control, maximum boost f = 15 kHz 11 12 13 dB maximum attenuation f = 15 kHz 11 12 13 dB maximum boost f > 15 kHz − − 15 dB step resolution (toggle switching) f = 15 kHz − 1.5 − dB step error between any adjoining step f = 15 kHz − − 0.5 dB − − 10 mV DC step offset in any treble position Volume II, balance and fader control CR continuous attenuation fader and volume control range 53.5 55 56.5 dB Gstep step resolution − 1 2 dB attenuation set error − − 1.5 dB − − 1.0 V Mute function VmuteLOWI input level for fast mute detection 2.2 − − V VmuteLOWO output level for mute I ≤ 1 mA; CI ≤ 100 pF − − 0.4 V VmuteHIGH pull-up voltage open collector − − VCC V VCCdrop supply drop to VCAP for mute active − −0.7 − V input level for no mute detection Power-on reset (when reset is active the GMU-bit (general mute) is set and the I2C-bus receiver is in reset position) VCC increasing supply voltage start of reset − − 2.5 V end of reset 5.2 6.5 7.2 V decreasing supply voltage start of reset 4.2 5.5 6.2 V Digital part (I2C-bus pins); note 3 ViH HIGH level input voltage 3 − 9.5 V ViL LOW level input voltage −0.3 − +1.5 V IiH HIGH level input current IiL LOW level input current VoL LOW level output voltage VCC = 0 to 9.5 V IL = 3 mA −10 − +10 µA −10 − +10 µA − − 0.4 V Notes to the characteristics 1. The indicated values for output power assume a 6 W power amplifier at 4 Ω with 20 dB gain and a fixed attenuator of 12 dB in front of it. Signal-to-noise ratios exclude noise contribution of the power amplifier. 2. The transmission contains: total initialization with MAD and subaddress for volume and 8 data words, see also definition of characteristics, clock frequency = 50 kHz, repetition burst rate = 400 Hz, maximum bus signal amplitude = 5 V (p-p). 3. The AC characteristics are in accordance with the I2C-bus specification. This specification, “The I2C-bus and how to use it”, can be ordered using the code 9398 393 40011. 1995 Dec 20 10 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T I2C-BUS PROTOCOL I2C-bus format S(1) SLAVE ADDRESS(2) A(3) SUBADDRESS(4) A(3) DATA(5) A(3) P(6) Notes 1. S = START condition. 2. SLAVE ADDRESS (MAD) = 1000 0000. 3. A = acknowledge, generated by the slave. 4. SUBADDRESS (SAD), see Table 1. 5. DATA, see Table 1; if more than 1 byte of DATA is transmitted, then auto-increment of the significant subaddress is performed. 6. P = STOP condition. Table 1 Second byte after MAD MSB FUNCTION LSB BIT 7 6 5 4 3 2(1) 1(1) 0(1) Volume/loudness V 0 0 0 0 0 0 0 0 Fader front right FFR 0 0 0 0 0 0 0 1 Fader front left FFL 0 0 0 0 0 0 1 0 Fader rear right FRR 0 0 0 0 0 0 1 1 Fader rear left FRL 0 0 0 0 0 1 0 0 Bass BA 0 0 0 0 0 1 0 1 Treble TR 0 0 0 0 0 1 1 0 Switch S 0 0 0 0 0 1 1 1 Note 1. Significant subaddress. 1995 Dec 20 11 Philips Semiconductors Preliminary specification Sound fader control circuit Table 2 TEA6323T Definition of third byte after MAD and SAD MSB FUNCTION LSB BIT 7 6 5 4 3 2 1 0 ZCM(1) LOFF(2) V5(3) V4(3) V3(3) V2(3) V1(3) V0(3) Volume/loudness V Fader front right FFR 0 0 FFR5(5) FFR4(5) FFR3(5) FFR2(5) FFR1(5) FFR0(5) Fader front left FFL 0 0 FFL5(6) FFL4(6) FFL3(6) FFL2(6) FFL1(6) FFL0(6) FRR4(7) FRR3(7) FRR2(7) FRR1(7) FRR0(7) Fader rear right FRR 0 0 FRR5(7) Fader rear left FRL 0 0 FRL5(8) FRL4(8) FRL3(8) FRL2(8) FRL1(8) FRL0(8) Bass BA 0 0 0 BA4(9) BA3(9) BA2(9) BA1(9) BA0(9) TR3(10) TR2(10) TR1(10) TR0(10) 0 SC2(12) SC1(12) SC0(12) Treble TR Switch S 0 0 0 TR4(10) GMU(11) 0 0 0 Notes 1. Zero crossing mode. 2. Switch loudness on/off. 3. Volume control. 4. Don’t care bits (logic 1 during testing). 5. Fader control front right. 6. Fader control front left. 7. Fader control rear right. 8. Fader control rear left. 9. Bass control. 10. Treble control. 11. Mute control for all outputs except OVL and OVR (general mute). 12. Source selector control. 1995 Dec 20 12 Philips Semiconductors Preliminary specification Sound fader control circuit Table 3 TEA6323T Volume I setting Gv (dB) DATA V5 V4 V3 V2 V1 V0 Loudness on: the increment of the loudness characteristics is linear at every volume step in the range from +20 to −11 dB +20 1 1 1 1 1 1 +19 1 1 1 1 1 0 +18 1 1 1 1 0 1 +17 1 1 1 1 0 0 +16 1 1 1 0 1 1 +15 1 1 1 0 1 0 +14 1 1 1 0 0 1 +13 1 1 1 0 0 0 +12 1 1 0 1 1 1 +11 1 1 0 1 1 0 +10 1 1 0 1 0 1 +9 1 1 0 1 0 0 +8 1 1 0 0 1 1 +7 1 1 0 0 1 0 +6 1 1 0 0 0 1 +5 1 1 0 0 0 0 +4 1 0 1 1 1 1 +3 1 0 1 1 1 0 +2 1 0 1 1 0 1 +1 1 0 1 1 0 0 0 1 0 1 0 1 1 −1 1 0 1 0 1 0 −2 1 0 1 0 0 1 −3 1 0 1 0 0 0 −4 1 0 0 1 1 1 −5 1 0 0 1 1 0 −6 1 0 0 1 0 1 −7 1 0 0 1 0 0 −8 1 0 0 0 1 1 −9 1 0 0 0 1 0 −10 1 0 0 0 0 1 −11 1 0 0 0 0 0 1995 Dec 20 13 Philips Semiconductors Preliminary specification Sound fader control circuit Gv (dB) TEA6323T DATA V5 V4 V3 V2 V1 V0 Loudness characteristic is constant in a range from −11 dB to −31 dB −12 0 1 1 1 1 1 −13 0 1 1 1 1 0 −14 0 1 1 1 0 1 −15 0 1 1 1 0 0 −16 0 1 1 0 1 1 −17 0 1 1 0 1 0 −18 0 1 1 0 0 1 −19 0 1 1 0 0 0 −20 0 1 0 1 1 1 −21 0 1 0 1 1 0 −22 0 1 0 1 0 1 −23 0 1 0 1 0 0 −24 0 1 0 0 1 1 −25 0 1 0 0 1 0 −26 0 1 0 0 0 1 −27 0 1 0 0 0 0 −28 0 0 1 1 1 1 −29 0 0 1 1 1 0 −30 0 0 1 1 0 1 −31 0 0 1 1 0 0 Repetition of steps in a range from −28 dB to −31 dB −28 0 0 1 0 1 1 −29 0 0 1 0 1 0 −30 0 0 1 0 0 1 −31 0 0 1 0 0 0 −28 0 0 0 1 1 1 −29 0 0 0 1 1 0 −30 0 0 0 1 0 1 −31 0 0 0 1 0 0 −28 0 0 0 0 1 1 −29 0 0 0 0 1 0 −30 0 0 0 0 0 1 −31 0 0 0 0 0 0 1995 Dec 20 14 Philips Semiconductors Preliminary specification Sound fader control circuit Table 4 TEA6323T Volume II setting (fader and balance) DATA FRR5 FRR4 FRR3 FRR2 FRR1 FRR0 FRL5 FRL4 FRL3 FRL2 FRL1 FRL0 FFL5 FFL4 FFL3 FFL2 FFL1 FFL0 FFR5 FFR4 FFR3 FFR2 FFR1 FFR0 0 1 1 1 1 1 1 −1 1 1 1 1 1 0 −2 1 1 1 1 0 1 −3 1 1 1 1 0 0 −4 1 1 1 0 1 1 −5 1 1 1 0 1 0 −6 1 1 1 0 0 1 −7 1 1 1 0 0 0 −8 1 1 0 1 1 1 Gv (dB) −9 1 1 0 1 1 0 −10 1 1 0 1 0 1 −11 1 1 0 1 0 0 −12 1 1 0 0 1 1 −13 1 1 0 0 1 0 −14 1 1 0 0 0 1 −15 1 1 0 0 0 0 −16 1 0 1 1 1 1 −17 1 0 1 1 1 0 −18 1 0 1 1 0 1 −19 1 0 1 1 0 0 −20 1 0 1 0 1 1 −21 1 0 1 0 1 0 −22 1 0 1 0 0 1 −23 1 0 1 0 0 0 −24 1 0 0 1 1 1 −25 1 0 0 1 1 0 −26 1 0 0 1 0 1 −27 1 0 0 1 0 0 −28 1 0 0 0 1 1 −29 1 0 0 0 1 0 −30 1 0 0 0 0 1 −31 1 0 0 0 0 0 −32 0 1 1 1 1 1 −33 0 1 1 1 1 0 −34 0 1 1 1 0 1 1995 Dec 20 15 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T DATA FRR5 FRR4 FRR3 FRR2 FRR1 FRR0 FRL5 FRL4 FRL3 FRL2 FRL1 FRL0 FFL5 FFL4 FFL3 FFL2 FFL1 FFL0 FFR5 FFR4 FFR3 FFR2 FFR1 FFR0 −35 0 1 1 1 0 0 −36 0 1 1 0 1 1 −37 0 1 1 0 1 0 −38 0 1 1 0 0 1 −39 0 1 1 0 0 0 −40 0 1 0 1 1 1 −41 0 1 0 1 1 0 −42 0 1 0 1 0 1 −43 0 1 0 1 0 0 −44 0 1 0 0 1 1 −45 0 1 0 0 1 0 −46 0 1 0 0 0 1 −47 0 1 0 0 0 0 −48 0 0 1 1 1 1 −49 0 0 1 1 1 0 −50 0 0 1 1 0 1 −51 0 0 1 1 0 0 −52 0 0 1 0 1 1 −53 0 0 1 0 1 0 −54 0 0 1 0 0 1 Gv (dB) −55 0 0 1 0 0 0 mute 0 0 0 1 1 1 mute 0 0 0 1 1 0 mute 0 0 0 1 0 1 mute 0 0 0 1 0 0 mute 0 0 0 0 1 1 mute 0 0 0 0 1 0 mute 0 0 0 0 0 1 mute 0 0 0 0 0 0 1995 Dec 20 16 Philips Semiconductors Preliminary specification Sound fader control circuit Table 5 TEA6323T Bass setting DATA Gbass (dB) BA4 BA3 BA2 BA1 BA0 +18.0 1 1 1 1 1 +16.2 1 1 1 1 0 +18.0 1 1 1 0 1 +16.2 1 1 1 0 0 +18.0 1 1 0 1 1 +16.2 1 1 0 1 0 +14.4 1 1 0 0 1 +12.6 1 1 0 0 0 +10.8 1 0 1 1 1 +9.0 1 0 1 1 0 +7.2 1 0 1 0 1 +5.4 1 0 1 0 0 +3.6 1 0 0 1 1 +1.8 1 0 0 1 0 0(1) 1 0 0 0 1 0(2) 1 0 0 0 0 −1.8 0 1 1 1 1 −3.6 0 1 1 1 0 −5.4 0 1 1 0 1 −7.2 0 1 1 0 0 −9.0 0 1 0 1 1 −10.8 0 1 0 1 0 −12.6 0 1 0 0 1 −14.4 0 1 0 0 0 −16.2 0 0 1 1 1 −18.0 0 0 1 1 0 −16.2 0 0 1 0 1 −18.0 0 0 1 0 0 note 3 0 0 0 1 1 note 3 0 0 0 1 0 note 3 0 0 0 0 1 notes 3 and 4 0 0 0 0 0 Notes 1. Recommended data word for step 0 dB. 2. Result of 1.8 dB boost and 1.8 dB attenuation. 3. The last four bass control data words mute the bass response. 4. The last bass control and treble control data words (00000) enable the external equalizer connection. 1995 Dec 20 17 Philips Semiconductors Preliminary specification Sound fader control circuit Table 6 TEA6323T Treble setting DATA Gtreble (dB) TR4 TR3 TR2 TR1 TR0 +12.0 1 1 1 1 1 +10.5 1 1 1 1 0 +12.0 1 1 1 0 1 +10.5 1 1 1 0 0 +12.0 1 1 0 1 1 +10.5 1 1 0 1 0 +12.0 1 1 0 0 1 +10.5 1 1 0 0 0 +9.0 1 0 1 1 1 +7.5 1 0 1 1 0 +6.0 1 0 1 0 1 +4.5 1 0 1 0 0 +3.0 1 0 0 1 1 +1.5 1 0 0 1 0 0(1) 1 0 0 0 1 0(2) 1 0 0 0 0 −1.5 0 1 1 1 1 −3.0 0 1 1 1 0 −4.5 0 1 1 0 1 −6.0 0 1 1 0 0 −7.5 0 1 0 1 1 −9.0 0 1 0 1 0 −10.5 0 1 0 0 1 −12.0 0 1 0 0 0 note 3 0 0 1 1 1 note 3 0 0 1 1 0 note 3 0 0 1 0 1 note 3 0 0 1 0 0 note 3 0 0 0 1 1 note 3 0 0 0 1 0 note 3 0 0 0 0 1 notes 3 and 4 0 0 0 0 0 Notes 1. Recommended data word for step 0 dB. 2. Result of 1.5 dB boost and 1.5 dB attenuation. 3. The last eight treble control data words select treble output. 4. The last treble control and bass control data words (00000) enable the external equalizer connection. 1995 Dec 20 18 Philips Semiconductors Preliminary specification Sound fader control circuit Table 7 TEA6323T Loudness setting Table 9 CHARACTERISTIC DATA LOFF With loudness 0 Linear 1 Table 8 DATA FUNCTION Selected input DATA FUNCTION SC2 SC1 SC0 Stereo inputs IAL and IAR 1 1 1 Stereo inputs IBL and IBR 1 1 0 Stereo inputs ICL and ICR 1 0 1 Stereo inputs IDL and IDR 1 0 0 (Stereo inputs) IAL and IAR 0 1 1 Differential inputs IAL, IAR and COM 0 1 0 No input (input mute) 0 0 1 Mono input COM 0 0 0 1995 Dec 20 Mute mode 19 GMU ZCM Direct mute off 0 0 Mute off delayed until the next zero crossing 0 1 Direct mute 1 0 Mute delayed until the next zero crossing 1 1 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T MED840 20 handbook, full pagewidth Gbass (dB) 10 0 −10 −20 10 10 2 10 3 f (Hz) 10 4 Fig.3 Bass control. MED424 15 handbook, full pagewidth Gtreble (dB) 10 5 0 −5 −10 −15 10 2 10 3 10 4 Fig.4 Treble control. 1995 Dec 20 20 f (Hz) 10 5 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T MED425 handbook,20 full pagewidth Gv (dB) 10 0 −10 −20 −30 −40 10 10 2 10 3 10 4 f (Hz) 10 5 Fig.5 Volume control with loudness (including low roll-off frequency). MED426 100 handbook, full pagewidth S/N (dB) (1) 90 (2) (3) 80 70 60 50 10 −4 10 −3 10 −2 10 −1 1 (1) Vi = 2.0 V. (2) Vi = 0.5 V. (3) Vi = 0.2 V. Fig.6 Signal-to-noise ratio; noise weighted: CCIR468-2, quasi peak. 1995 Dec 20 21 Po (W) 10 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T MED427 110 handbook, full pagewidth S/N (dB) (1) 100 (2) 90 (3) 80 70 60 10 −4 10 −3 10 −2 10 −1 1 Po (W) 10 (1) Unweighted RMS. (2) CCIR468-2 RMS. (3) CCIR468-2 quasi peak. Fig.7 Signal-to-noise ratio; Vi = 2 V; Pmax = 6 W. MHA086 250 handbook, full pagewidth noise (µV) 200 (1) (2) 150 (3) (4) 100 50 0 −70 −50 (1) Symmetrical input; loudness on. (2) Symmetrical input; loudness off. −30 −10 (3) Stereo/mono inputs; loudness on. (4) Stereo/mono inputs; loudness off. Fig.8 Noise output voltage; CCIR468-2, quasi peak 1995 Dec 20 22 10 gain (dB) 30 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T MED429 −60 handbook, full pagewidth (dB) −80 −100 −120 −140 20 50 10 2 200 500 10 3 Fig.9 Muting. 1995 Dec 20 23 2 x 10 3 5 x 10 3 10 4 2 x 10 4 f (Hz) Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T If the 20 dB gain is not required for the maximum volume position, it will be an advantage to use the maximum boost gain and then increased attenuation in the last section, Volume II. Therefore the loudness will be at the correct place and a lower noise and offset voltage will be achieved. POWER STAGE handbook, halfpage TEA6323T G = 20 dB VI(min) = 200 mV Vo = 2 V for P(max) P(max) = 100 W at 4 Ω MHA259 a. POWER STAGE handbook, halfpage TEA6323T G = 26 dB VI(min) = 200 mV Vo = 1 V for P(max) P(max) = 100 W at 4 Ω MHA260 b. a. Gain volume I = 20 dB (Gv(max)); gain volume II = 0 dB; fader and balance range = 55 dB. b. Gain volume I = 20 dB (Gv(max)); gain volume II = −6 dB global setting; fader and balance range now 49 dB, previously 55 dB. Fig.10 Level diagram. 1995 Dec 20 24 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T handbook, full pagewidth VP VCC 8.5 V +8.5 V to oscilloscope 470 µF 4.7 kΩ inputs 38 20 18 5 16 14 6 17 TEA6323T 35 27 25 36 23 21 3 4 24 26 outputs to oscilloscope 4 × 4.7 µF 9 × 220 nF 9 × 600 Ω 47 µF 47 µF 4 × 10 kΩ MHA261 Fig.11 Turn-on/off power supply circuit diagram. MED433 10 handbook, full pagewidth (V) 8 (1) 6 4 (2) 2 0 0 1 2 3 (1) VCC. (2) VO. Fig.12 Turn-on/off behaviour. 1995 Dec 20 25 4 t (s) 5 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T handbook, full pagewidth +5 V 3.4 kΩ 220 nF 100 µF 26 VCC = 8.5 V 13 11 270 nF 270 nF 5.6 nF 9 8 4.7 kΩ 7 38 2 40 SCL 1 SDA 0.1 µF 10 kΩ 3 1000 µF 4 TDA6323T 47 µF Vp 0.2 V (RMS) 24 600 Ω output right output left front and rear input A to D left and right and input mono 47 µF Vo 220 nF 28 30 220 nF 32 270 nF 33 34 5.6 nF 270 nF MHA262 3.4 kΩ Fig.13 Test circuit for power supply ripple rejection (RR). handbook, full pagewidth +5 V 3.4 kΩ 220 nF 100 µF 26 VCC = 8.5 V 470 µF 13 11 270 nF 270 nF 5.6 nF 9 8 4.7 kΩ 7 38 0.1 µF 40 SCL 1 SDA 3 4 Vp 2 47 µF TDA6323T 24 output left output right front and rear input A to D right and left Vi 600 Ω 220 nF input A to D left and right and input mono 47 µF Vo 220 nF 28 30 220 nF 32 270 nF 33 34 5.6 nF 270 nF MHA263 3.4 kΩ Fig.14 Test circuit for channel separation (αcs). 1995 Dec 20 26 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T Loudness filter calculation example Figure 15 shows the basic loudness circuit with an external low-pass filter application. R1 allows an attenuation range of 21 dB while the boost is determined by the gain stage V2. Both result in a loudness control range of +20 to −12 dB. handbook, halfpage Defining fref as the frequency where the level does not change while switching loudness on/off. The external resistor R3 for fref → ∞ can be calculated as CKVL 0 dB 11 V1 R1 33 kΩ Gv ------20 10 R3 = R1 -------------------- . With Gv = −21 dB and R1 = 33 kΩ, G V2 12 v C1 ------20 1 – 10 R3 = 3.2 kΩ is generated. R2 R3 MHA092 For the low-pass filter characteristic the value of the external capacitor C1 can be determined by setting a specific boost for a defined frequency and referring the gain to Gv at fref as indicated above. Gv ------20 ( R1 + R3 ) × 10 – R3 1 --------------------- = ------------------------------------------------------------Gv j ( ωC1 ) ------20 1 – 10 Fig.15 Basic loudness circuit. For example: 3 dB boost at f = 1 kHz Gv = Gv(ref) + 3 dB = −18 dB; f = 1 kHz and C1 = 100 nF. If a loudness characteristic with additional high frequency boost is desired, an additional high-pass section has to be included in the external filter circuit as indicated in the block diagram. A filter configuration that provides AC coupling avoids offset voltage problems. Figure 16 shows an example of the loudness circuit with bass and treble boost. The calculation of this network is numeric. handbook, halfpage 220 nF 0 dB 11 8.2 nF 20 kΩ V1 R1 33 kΩ 12 V2 150 nF R2 2.2 kΩ MHA281 Fig.16 Loudness circuit with bass and treble boost. 1995 Dec 20 27 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T INTERNAL PIN CONFIGURATIONS Values shown in Figs 17 to 29 are typical DC values; VCC = 8.5 V. 5 4.25 V 1 5V 1.8 kΩ 80 Ω MBE911 MHA265 Fig.17 Pin 1: SDA (I2C-bus data). Fig.18 Pins 5, 6, 10, 31, 35, 36: output signals. 8 7 4.25 V 4.25 V 80 Ω 2.4 kΩ MHA264 MHA267 Fig.19 Pins 7 and 34: treble control capacitors. 1995 Dec 20 Fig.20 Pins 8 and 33: bass control capacitor outputs. 28 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T 11 4.25 V 9 4.25 V 4.16 kΩ 150 kΩ 4.25 V MHA268 MHA266 Fig.21 Pins 9 and 32: bass control capacitor inputs. Fig.22 Pins 11 and 30: input volume 1, control part. 13 4.25 V 12 4.25 V 80 Ω 1.12 kΩ MHA269 MHA270 Fig.23 Pins 12 and 29: input loudness, control part. 1995 Dec 20 Fig.24 Pins 13 and 28: output source selector. 29 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T 14 2 4.25 V 1.5 V constant 2.2 V 35 kΩ 4.25 V MHA272 MHA271 Fig.25 Pins 14, 16 to 18, 20, 21, 23, 25, 27: inputs. Fig.26 Pin 2: mute control. + 8.4 V 24 4.7 kΩ 300 Ω + 5 kΩ 4.25 V 26 3.4 kΩ 3.4 kΩ MHA273 Fig.27 Pin 24: filtering for supply; pin 26: reference voltage. apply +8.5 V to this pin 38 40 5V 1.8 kΩ MHA275 MHA274 Fig.29 Pin 40: SCL (I2C-bus clock). Fig.28 Pin 38: supply voltage. 1995 Dec 20 30 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T PACKAGE OUTLINE VSO40: plastic very small outline package; 40 leads SOT158-1 D E A X c y HE v M A Z 40 21 Q A2 A (A 3) A1 θ pin 1 index Lp L 1 detail X 20 w M bp e 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 2.70 0.3 0.1 2.45 2.25 0.25 0.42 0.30 0.22 0.14 15.6 15.2 7.6 7.5 0.762 12.3 11.8 2.25 1.7 1.5 1.15 1.05 0.2 0.1 0.1 0.6 0.3 0.012 0.096 0.017 0.0087 0.61 0.010 0.004 0.089 0.012 0.0055 0.60 0.30 0.29 0.03 0.48 0.46 0.067 0.089 0.059 inches 0.11 0.045 0.024 0.008 0.004 0.004 0.041 0.012 θ 7o 0o Notes 1. Plastic or metal protrusions of 0.4 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-01-24 SOT158-1 1995 Dec 20 EUROPEAN PROJECTION 31 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering Reflow soldering techniques are suitable for all VSO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering techniques can be used for all VSO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. 1995 Dec 20 32 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1995 Dec 20 33 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T NOTES 1995 Dec 20 34 Philips Semiconductors Preliminary specification Sound fader control circuit TEA6323T NOTES 1995 Dec 20 35 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. 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(0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601 Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCD47 © Philips Electronics N.V. 1995 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 513061/1100/01/pp36 Document order number: Date of release: 1995 Dec 20 9397 750 00536