INTEGRATED CIRCUITS DATA SHEET TDA9852 I2C-bus controlled BTSC stereo/SAP decoder and audio processor Preliminary specification Supersedes data of 1996 Feb 28 File under Integrated Circuits, IC02 1997 Mar 11 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 FEATURES • Quasi alignment-free application due to automatic adjustment of channel separation via I2C-bus • High integration level with automatically tuned integrated filters • Input level adjustment I2C-bus controlled • Alignment-free SAP processing GENERAL DESCRIPTION • dbx noise reduction circuit The TDA9852 is a bipolar-integrated BTSC stereo decoder with hi-fi audio processor (I2C-bus controlled) for application in TV sets, VCRs and multimedia. • Power supply • I2C-bus transceiver. Stereo decoder • Stereo pilot PLL circuit with ceramic resonator, automatic adjustment procedure for stereo channel separation, two pilot thresholds selectable via I2C-bus. Audio processor • Selector for internal and external signals (line in) • Automatic volume level control (control range +6 to −15 dB) • Interface for external noise reduction circuits • Volume control (control range +16 to −71 dB) • Special loudness characteristic automatically controlled in combination with volume setting (control range 28 dB) • Audio signal zero crossing detection between any volume step switching • Mute control at audio signal zero crossing • Mute control via I2C-bus. ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION TDA9852 SDIP42 plastic shrink dual in-line package; 42 leads (600 mil) TDA9852H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2 1997 Mar 11 2 SOT270-1 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 LICENSE INFORMATION A license is required for the use of this product. For further information, please contact COMPANY THAT Corporation BRANCH ADDRESS Licensing Operations 734 Forest St. Marlborough, MA 01752 USA Tel.: (508) 229-2500 Fax: (508) 229-2590 Tokyo Office 405 Palm House, 1-20-2 Honmachi Shibuya-ku, Tokyo 151 Japan Tel.: (03) 3378-0915 Fax: (03) 3374-5191 QUICK REFERENCE DATA SYMBOL PARAMETER VCC supply voltage ICC supply current CONDITIONS MIN. 8.0 − TYP. 8.5 MAX. 9.0 UNIT V 75 95 mA 100% modulation L + R; fi = 300 Hz − 250 − mV VoR,L(rms) output signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz − 500 − mV GLA input level adjustment control −3.5 − +4.0 dB αcs stereo channel separation fL = 300 Hz; fR = 3 kHz 25 35 − dB THDL,R total harmonic distortion L + R fi = 1 kHz − 0.2 − % THD < 0.5% Vcomp(rms) input signal voltage (RMS value) VI, O(rms) signal handling (RMS value) 2 − − V AVL control range −15 − +6 dB GC volume control range −71 − +16 dB LB maximum loudness boost fi = 40 Hz − 17 − dB S/N signal-to-noise ratio line out (mono); Vo = 0.5 V (RMS) CCIR noise weighting filter (peak value) − 60 − dB DIN noise weighting filter (RMS value) − 73 − dBA CCIR noise weighting filter (peak value) − 94 − dB DIN noise weighting filter (RMS value) − 107 − dBA S/N signal-to-noise ratio 1997 Mar 11 audio section; Vo = 2 V (RMS); gain = 0 dB 3 C4 CERAMIC RESONATOR MURATA CSB503F58 C2 R1 26 27 (22) (23) C11 Q1 C5 28 (24) 29 30 (25) (26) C7 C20 C16 C28 C8 C10 C12 LOR LIR 32 (28) 33 (29) 36 (32) 34 (30) 35 (31) 5 (44) STEREO DECODER COMP C1 (20) 24 DEMATRIX + LINEOUT SELECT 4 SAP DEMODULATOR (14) 19 C17 (13) (12) 18 17 C18 C19 (11) (9) 16 14 (8) 13 (7) 12 (6) (5) 11 10 LOL (2) 7 EFFECTS SUPPLY LOGIC I2C TRANSCEIVER (3) (19) (21) (1) 8 23 25 6 VOLUME LEFT LOUDNESS CONTROL (17) (18) (43) 4 20 (15) 21 (16) 22 (41) 2 (39) MHA309 n.c. C29 SDA SCL C15 C34 C30 C21 C47 C49 VCC External Input Left (EIL) R5 DGND Preliminary specification Fig.1 Block diagram. AGND R4 TDA9852 handbook, full pagewidth (42) 3 C14 C26 (38) 42 OUTR (40) 1 OUTL OUT LEFT VIL C22 C23 C24 C25 The numbers given in parenthesis refer to the TDA9852H version. OUT RIGHT ZERO CROSSING LIL C27 R7 (4) 9 41 (37) VOLUME RIGHT LOUDNESS CONTROL AUTOMATIC VOLUME AND LEVEL CONTROL STEREO ADJUST DBX (10) 15 R6 INPUT SELECT VIR 40 (36) 38 39 (34) (35) 37 (33) TDA9852 STEREO/ SAP SWITCH INPUT LEVEL ADJUST R3 C9 C6 31 (27) R2 Philips Semiconductors C3 I2C-bus controlled BTSC stereo/SAP decoder and audio processor BLOCK DIAGRAM 1997 Mar 11 External Input Right (EIR) Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 Component list Electrolytic capacitors ±20%; foil or ceramic capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1. COMPONENTS 1997 Mar 11 VALUE TYPE REMARK 63 V C1 10 µF electrolytic C2 470 nF foil C3 4.7 µF electrolytic C4 220 nF foil C5 10 µF electrolytic 63 V; Ileak < 1.5 µA C6 2.2 µF electrolytic 16 V C7 2.2 µF electrolytic 63 V C8 15 nF foil ±5% C9 15 nF foil ±5% C10 2.2 µF electrolytic 16 V 63 V C11 8.2 nF foil or ceramic ±5% SMD 2220/1206 C12 150 nF foil ±5% C14 150 nF foil ±5% C15 100 µF electrolytic 16 V C16 4.7 µF electrolytic 63 V C17 4.7 µF electrolytic 63 V C18 100 nF foil C19 10 µF electrolytic 63 V C20 4.7 µF electrolytic 63 V C21 47 nF foil ±5% C22 1 µF electrolytic 63 V C23 1 µF electrolytic 63 V C24 10 µF electrolytic 63 V ±10% C25 10 µF electrolytic 63 V ±10% C26 2.2 µF electrolytic 16 V C27 2.2 µF electrolytic 63 V C28 4.7 µF electrolytic 63 V ±10% C29 2.2 µF electrolytic 16 V C30 8.2 nF foil or ceramic ±5% SMD 2220/1206 C34 100 µF electrolytic 16 V C47 220 µF electrolytic 25 V C49 100 nF foil or ceramic SMD 1206 R1 2.2 kΩ − R2 20 kΩ − R3 2.2 kΩ − R4 20 kΩ − R5 2.2 kΩ − R6 8.2 kΩ − 5 ±2% Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 COMPONENTS VALUE TYPE REMARK R7 160 Ω − ±2% Q1 CSB503F58 radial leads CSB503JF958 alternative as SMD PINNING PINS SYMBOL DESCRIPTION SDIP42 QFP44 OUTL 1 40 output, left channel LDL 2 41 input loudness, left channel VIL 3 42 input volume, left channel EOL 4 43 output effects, left channel CAV 5 44 automatic volume control capacitor Vref 6 1 reference voltage 0.5VCC LIL 7 2 input line control, left channel AVL 8 3 input automatic volume control, left channel SOL 9 4 output selector, left channel LOL 10 5 output line control, left channel CTW 11 6 capacitor timing wideband for dbx CTS 12 7 capacitor timing spectral for dbx CW 13 8 capacitor wideband for dbx CS 14 9 capacitor spectral for dbx VEO 15 10 variable emphasis output for dbx VEI 16 11 variable emphasis input for dbx CNR 17 12 capacitor noise reduction for dbx CM 18 13 capacitor mute for SAP CDEC 19 14 capacitor DC-decoupling for SAP GND 20 − ground AGND − 15 analog ground DGND − 16 digital ground SDA 21 17 serial data input/output (I2C-bus) SCL 22 18 serial clock input (I2C-bus) VCC 23 19 supply voltage COMP 24 20 composite input signal VCAP 25 21 capacitor for electronic filtering of supply CP1 26 22 capacitor for pilot detector CP2 27 23 capacitor for pilot detector CPH 28 24 capacitor for phase detector CADJ 29 25 capacitor for filter adjustment CER 30 26 ceramic resonator CMO 31 27 capacitor DC-decoupling mono 1997 Mar 11 6 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 PINS SYMBOL DESCRIPTION SDIP42 QFP44 35 31 input automatic volume control, right channel LIR 36 32 input line control, right channel CPS2 37 33 capacitor 2 pseudo function CPS1 38 34 capacitor 1 pseudo function EOR 39 35 output effects, right channel VIR 40 36 input volume, right channel LDR 41 37 input loudness, right channel OUTR 42 38 output, right channel n.c. − 39 not connected 44 CAV handbook, full pagewidth 34 CPS1 AVR 35 EOR output selector, right channel 36 VIR 30 37 LDR 34 38 OUTR SOR 39 n.c. output line control, right channel 40 OUTL capacitor DC-decoupling stereo/SAP 29 41 LDL 28 33 42 VIL 32 43 EOL CSS LOR Vref 1 33 CPS2 LIL 2 32 LIR AVL 3 31 AVR SOL 4 30 SOR LOL 5 29 LOR TDA9852H CTW 6 28 CSS Fig.2 Pin configuration (QFP-version). 1997 Mar 11 7 CP1 22 VCAP 21 23 CP2 COMP 20 VEI 11 VCC 19 24 CPH SCL 18 VEO 10 SDA 17 25 CADJ DGND 16 CS 9 AGND 15 26 CER CDEC 14 CW 8 CM 13 27 CMO CNR 12 CTS 7 MHA696 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 FUNCTIONAL DESCRIPTION Stereo decoder INPUT LEVEL ADJUSTMENT The composite input signal is fed to the input level adjustment stage. The control range is from −3.5 to +4.0 dB in steps of 0.5 dB. The subaddress control 3 of Tables 5 and 6 and the level adjust setting of Table 21 allows an optimum signal adjustment during the set alignment. The maximum input signal voltage is 2 V (RMS). handbook, halfpage OUTL 1 42 OUTR LDL 2 41 LDR VIL 3 40 VIR EOL 4 39 EOR CAV 5 38 CPS1 STEREO DECODER Vref 6 37 CPS2 LIL 7 36 LIR AVL 8 35 AVR SOL 9 34 SOR LOL 10 33 LOR The output signal of the level adjustment stage is coupled to a low-pass filter which suppresses the baseband noise above 125 kHz. The composite signal is then fed into a pilot detector/pilot cancellation circuit and into the MPX demodulator. The main L + R signal passes a 75 µs fixed de-emphasis filter and is fed into the dematrix circuit. The decoded sub-signal L − R is sent to the stereo/SAP switch. To generate the pilot signal the stereo demodulator uses a PLL circuit including a ceramic resonator. The stereo channel separation is adjusted by an automatic procedure to be performed during set production. For a detailed description see Section “Adjustment procedure”. The stereo identification can be read by the I2C-bus (see Table 2). Two different pilot thresholds (data STS = 1; STS = 0) can be selected via the I2C-bus (see Table 19). CTW 11 TDA9852 32 CSS CTS 12 31 CMO CW 13 30 CER CS 14 29 CADJ VEO 15 28 CPH VEI 16 27 CP2 CNR 17 26 CP1 CM 18 25 VCAP SAP DEMODULATOR CDEC 19 24 COMP The composite signal is fed from the output of the input level adjustment stage to the SAP demodulator circuit through a 5fH (fH = horizontal frequency) band-pass filter. The demodulator level is automatically controlled. The SAP demodulator includes internal noise and field strength detectors that mute the SAP output in the event of insufficient signal conditions. The SAP identification signal can be read by the I2C-bus (see Table 2). GND 20 23 VCC SDA 21 22 SCL MHA310 SWITCH The stereo/SAP switch feeds either the L − R signal or the SAP demodulator output signal via the internal dbx noise reduction circuit to the dematrix/switching circuit. Table 12 shows the different switch modes provided at the output pins LOR and LOL. Fig.3 Pin configuration (SDIP-version). 1997 Mar 11 8 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 dbx DECODER EFFECTS The circuit includes all blocks required for the noise reduction system in accordance with the BTSC system specification. The output signal is fed through a 73 µs fixed de-emphasis circuit to the dematrix block. The audio processor section offers the following mode selections: linear stereo, pseudo stereo, spatial stereo and forced mono.The spatial mode provides an antiphase crosstalk of 30% or 52% (switchable via I2C-bus; see Table 10). INTEGRATED FILTERS VOLUME/LOUDNESS The filter functions necessary for stereo and SAP demodulation and part of the dbx filter circuits are provided on-chip using transconductor circuits. The required filter accuracy is attained by an automatic filter alignment circuit. The volume control range is from +16 dB to −71 dB in steps of 1 dB and ends with a mute step (see Table 8). Balance control is achieved by the independent volume control of each channel. The volume control blocks operate in combination with the loudness control. The filter is linear when maximum gain for volume control is selected. The filter characteristic changes automatically over a range of 28 dB down to a setting of −12 dB. At −12 dB volume control the maximum loudness boost is obtained. The filter characteristic is determined by external components. The proposed application provides a maximum boost of 17 dB for bass and 4.5 dB for treble. The loudness may be switched on or off via I2C-bus control (see Table 9). The left and right volume control stages include two independent zero crossing detectors. A change in volume is automatically activated but not executed. The execution is enabled at the next zero crossing of the signal. If a new volume step is activated before the previous one has been processed, the previous value will be executed first, and then the new value will be activated. If no zero crossing occurs the next volume transmission will enforce the last activated volume setting. Audio processor SELECTOR The selector allows selecting either the internal line out signals LOR or LOL (dematrix output) or the external line in signals LIR and LIL and combines the left and right signals in several modes (see Tables 5 and 6 for subaddress and Table 11 for data). The input signal capability of the line inputs (LIR/LIL) is 2 V (RMS). The output of the selector is AC-coupled to the automatic volume level control circuit via pins SOR/SOL and AVR/AVL to avoid offset voltages. AUTOMATIC VOLUME LEVEL CONTROL The automatic volume level stage controls its output voltage to a constant level of typically 200 mV (RMS) from an input voltage range of 0.1 to 1.1 V (RMS). The circuit adjusts variations in modulation during broadcasting and due to changes in the programme material. The function can be switched off. To avoid audible ‘plops’ during the permanent operation of the AVL circuit a soft blending scheme has been applied between the different gain stages. A capacitor (4.7 µF) at pin CAV determines the attack and decay time constants. In addition the ratio of attack and decay time can be changed via I2C-bus (see Table 15). At power on, the discharged 4.7 µF capacitor at CAV must be loaded by the internal decay current. If AVL is chosen, this would result in an attenuated AVL gain for about 10 seconds after power on. This can be speeded up by choosing via I2C-bus an increased charge current (about 10 times higher) for about the first 2 seconds after power on (see Table 6, CCD bit in control 1 and Table 18). 1997 Mar 11 The zero crossing is realized between adjoining steps and between any steps, but not from any step to mute. In this case the GMU bit is needed to use. In case only one channel has to be muted, two steps are necessary. The first step is a transmission of any step to −71 dB and the second step is the −71 dB step to mute mode. The step of −71 dB to mute mode has no zero crossing but this is not relevant. 9 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 • Effects, AVL, loudness off. MUTE • Line out setting bits: STEREO = 1, SAP = 0 (see Table 12) The mute function can be activated independently with last step of volume control at the left or right output. By setting the general mute bit GMU via the I2C-bus all outputs are muted. All channels include an independent zero cross detector. The zero crossing mute feature can be selected via bit TZCM: • Selector setting SC0, SC1, SC2 = 0, 0, 0 (see Table 11) • Start adjustment by transmission ADJ = 1 in register ALI3; the decoder will align itself • After 1 second minimum stop alignment by transmitting ADJ = 0 in register ALI3 read the alignment data by an I2C-bus read operation from ALR1 and ALR2 (see Chapter “I2C-bus protocol”) and store it in a non-volatile memory; the alignment procedure overwrites the previous data stored in ALI1 and ALI2 TZCM = 0: forced mute with direct execution TZCM = 1: execution in time with signal zero crossing. In the zero cross mode a change in the GMU polarity is activated but not executed. The execution is enabled at the next zero crossing of the signal. To avoid a large delay of mute switching, when very low frequencies are processed, or the output signal amplitude is lower than the DC offset voltage, the following I2C-bus transmissions are needed: • Disconnect the capacitors of external inputs from ground. MANUAL ADJUSTMENT a first transmission for mute execution Manual adjustment is necessary when no dual tone generator is available (e.g. for service). a second transmission about 100 ms later, which must switch the zero crossing mode to forced mute (TZCM = 0) • Spectral and wideband data have to be set to 10000 (middle position for adjustment range) • Composite input L = 300 Hz; 14% modulation a third transmission to reactivate the zero crossing mode (TZCM = 1). This transmission can take place immediately, but must follow before the next mute execution. • Adjust channel separation by varying wideband data • Composite input L = 3 kHz; 14% modulation • Adjust channel separation by varying spectral data Adjustment procedure • Iterative spectral/wideband operation for optimum adjustment COMPOSITE INPUT LEVEL ADJUSTMENT • Store data in non-volatile memory. Feed in from FM demodulator the composite signal with 100% modulation (25 kHz deviation) L + R; fi = 300 Hz. Set input level control via I2C-bus monitoring line out (500 mV ±20 mV). Store the setting in a non-volatile memory. TIMING CURRENT FOR RELEASE RATE Due to possible internal and external spreading, the timing current can be adjusted via I2C-bus, see Table 20, as recommended by dbx. AUTOMATIC ADJUSTMENT PROCEDURE • Capacitors of external inputs LIL and LIR must be grounded at EIL and EIR • Composite input signal L = 300 Hz, R = 3.1 kHz, 14% modulation for each channel; volume gain +16 dB via I2C-bus 1997 Mar 11 10 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 Requirements for the composite input signal to ensure correct system performance SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT COMPL+R(rms) composite input level for 100% modulation L + R; 25 kHz deviation; fi = 300 Hz; RMS value measured at COMP 162 250 363 mV ∆COMP composite input level spreading under operating conditions Tamb = −20 to +70 °C; aging; power supply influence −0.5 − +0.5 dB Zo output impedance note 1 − low-ohmic 5 kΩ flf low frequency roll-off 25 kHz deviation L + R; −2 dB − − 5 Hz fhf high frequency roll-off 25 kHz deviation L + R; −2 dB 100 − − kHz THDL,R total harmonic distortion L + R fi = 1 kHz; 25 kHz deviation − − 0.5 % fi = 1 kHz; 125 kHz deviation; note 2 − − 1.5 % critical picture modulation; note 3 44 − − dB with sync only 54 − − dB − − dB S/N signal-to-noise ratio L + R/noise CCIR 468-2 weighted quasi peak; L + R; 25 kHz deviation; fi = 1 kHz; 75 µs de-emphasis αSB side band suppression mono into unmodulated SAP carrier; SAP carrier/side band mono signal: 25 kHz deviation, 46 fi = 1 kHz; side band: SAP carrier frequency ±1 kHz αSP spectral spurious attenuation L + R/spurious 50 Hz to 100 kHz; mainly n × fH; no de-emphasis; L + R; 25 kHz deviation, f = 1 kHz as reference n = 1, 5 35 − − dB n = 4, 6 40 − − dB n = 2, 3 26 − − dB Notes 1. Low-ohmic preferred, otherwise the signal loss and spreading at COMP, caused by Zo and the composite input impedance (see Chapter “Characteristics”, Section “Input level adjustment control”) must be taken into account. 2. In order to prevent clipping at over-modulation (maximum deviation in the BTSC system for 100% modulation is 73 kHz). 3. For example colour bar or flat field white; 100% video modulation. 1997 Mar 11 11 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VCC supply voltage 0 9.5 V Vn voltage of all other pins to pin VCC 0 VCC V Tamb operating ambient temperature −20 +70 °C Tstg storage temperature −65 +150 °C Ves electrostatic handling; note 1 Note 1. Human body model: C = 100 pF; R = 1.5 kΩ; V = 2 kV; Charge device model: C = 200 pF; R = 0 Ω; V = 300 V. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1997 Mar 11 PARAMETER VALUE UNIT SOT270-1 43 K/W SOT307-2 60 K/W thermal resistance from junction to ambient in free air 12 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 CHARACTERISTICS All voltages are measured relative to GND; VCC = 8.5 V; Rs = 600 Ω; RL = 10 kΩ; CL = 2.5 nF; AC-coupled; fi = 1 kHz; Tamb = 25 °C; gain control Gv = 0 dB; balance in mid position; loudness off; see Fig.1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT General VCC supply voltage ICC supply current − 75 95 mA Vref internal reference voltage at pin Vref − 4.25 − V 8.0 8.5 9.0 V Input level adjustment control GLA input level adjustment control −3.5 − +4.0 dB Gstep step resolution − 0.5 − dB Vi(rms) maximum input voltage level (RMS value) 2 − − V Zi input impedance 29.5 35 40.5 kΩ input level adjusted via I2C-bus − (L + R; fi = 300 Hz); monitoring LINE OUT 250 − mV Stereo decoder MPXL+R(rms) input voltage level for 100% modulation L + R; 25 kHz deviation (RMS value) MPXL−R input voltage level for 100% modulation L − R; 50 kHz deviation (peak value) − 707 − mV MPX(max) maximum headroom for L + R, fmod < 15 kHz; THD < 15% L, R 9 − − dB − 50 − mV MPXpilot(rms) nominal stereo pilot voltage level (RMS value) pilot threshold voltage stereo on (RMS value) data STS = 1 − − 35 mV data STS = 0 − − 30 mV SToff(rms) pilot threshold voltage stereo off (RMS value) data STS = 1 15 − − mV Hys hysteresis STon(rms) 10 − − mV − 2.5 − dB 480 500 520 mV fL = 300 Hz; fR = 3 kHz 25 35 − dB fL = 300 Hz; fR = 8 kHz 20 30 − dB fL = 300 Hz; fR = 10 kHz 15 25 − dB data STS = 0 input level adjusted via I2C-bus OUTL+R output voltage level for 100% modulation L + R at LINE OUT (L + R; fi = 300 Hz); monitoring LINE OUT αcs stereo channel separation L/R at LINE OUT 1997 Mar 11 aligned with dual tone 14% modulation for each channel; see Section “Adjustment procedure” in Chapter “Functional description” 13 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor SYMBOL fL, R PARAMETER L, R frequency response TDA9852 CONDITIONS MIN. TYP. MAX. UNIT 14% modulation; fref = 300 Hz L or R fi = 50 Hz to 10 kHz −3 − − dB fi = 12 kHz − −3 − dB THDL,R total harmonic distortion L, R at LINE OUT modulation L or R 1% to 100%; fi = 1 kHz − 0.2 1.0 % S/N signal-to-noise ratio mono mode; CCIR 468-2 weighted; quasi peak; 500 mV output signal 50 60 − dB Stereo decoder, oscillator (VCXO); note 1 fo nominal VCXO output frequency (32fH) with nominal ceramic resonator − 503.5 − kHz fof spread of free-running frequency with nominal ceramic resonator 500.0 − 507.0 kHz ∆fH capture range frequency (nominal pilot) ±190 ±265 − Hz − 150 − mV SAP demodulator; note 2 SAPi(rms) nominal SAP carrier input voltage level (RMS value) SAPon(rms) threshold voltage SAP on (RMS value) − − 85 mV SAPoff(rms) threshold voltage SAP off (RMS value) 35 − − mV SAPhys hysteresis − 2 − dB SAPLEV SAP output voltage level at LINE OUT mode selector in position SAP/SAP; fmod = 300 Hz; 100% modulation − 500 − mV fres frequency response 14% modulation; 50 Hz to 8 kHz; fref = 300 Hz −3 − − dB THD total harmonic distortion fi = 1 kHz − 0.5 2.0 % 1997 Mar 11 15 kHz frequency deviation of intercarrier 14 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor SYMBOL PARAMETER TDA9852 CONDITIONS MIN. TYP. MAX. UNIT LINE OUT at pins LOL and LOR − 500 − mV output headroom 9 − − dB Zo output impedance − 80 120 Ω Vo(rms) nominal output voltage (RMS value) HEADo 100% modulation VO DC output voltage 0.45VCC 0.5VCC RL output load resistance 5 − − kΩ CL output load capacitance − − 2.5 nF αct crosstalk L, R into SAP 100% modulation; fi = 1 kHz; 50 L or R; mode selector switched to SAP/SAP 75 − dB crosstalk SAP into L, R 100% modulation; fi = 1 kHz; SAP; mode selector switched to stereo 50 70 − dB output voltage difference if switched from L, R to SAP 250 Hz to 6.3 kHz − − 3 dB ∆VST-SAP 0.55VCC V dbx noise reduction circuit tadj stereo adjustment time see Section “Adjustment procedure” in Chapter “Functional description” − − 1 s Is nominal timing current for nominal release rate of spectral RMS detector Is can be measured at pin CTS via current meter connected to 1⁄ V 2 CC + 1 V − 24 − µA ∆Is spread of timing current −15 − +15 % − ±30 − % − 1⁄ 3Is − µA wideband − 125 − dB/s spectral − 381 − dB/s Is range timing current range It timing current for release rate of wideband RMS detector Relrate nominal RMS detector release rate 1997 Mar 11 7 steps via I2C-bus nominal timing current and external capacitor values 15 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor SYMBOL PARAMETER TDA9852 CONDITIONS MIN. TYP. MAX. UNIT Circuit section from pins LIL and LIR to pins OUTL and OUTR; note 3 B THD roll-off frequencies total harmonic distortion C6, C7, C10, C26, C27 and C29 = 2.2 µF; Zi = Zi(min) low frequency (−3 dB) − − 20 Hz high frequency (−0.5 dB) 20 − − kHz Vi = 1000 mV; Gv = 0 dB; AVL on − 0.2 0.5 % Vi = 2000 mV; Gv = 0 dB; AVL on − 0.2 0.5 % Vi = 1000 mV; Gv = 0 dB; AVL off − 0.02 − % Vi = 2000 mV; Gv = 0 dB; AVL off − 0.02 − % RR ripple rejection Vr(rms) < 200 mV; fi = 100 Hz 47 50 − dB αct crosstalk between bus inputs and signal outputs notes 4 and 5 − 110 − dB Vno noise output voltage CCIR 468-2 weighted; quasi peak; AVL off; loudness off; Gv = 0 dB − 40 80 µV measured in dBA; AVL off; loudness off; Gv = 0 dB − 8 − µV Vi = 1 V; fi = 1 kHz 75 − − dB Vi = 1 V; fi = 12.5 kHz 75 − − dB αcs channel separation Effect controls αspat1 αspat2 anti-phase crosstalk by spatial effect ϕ phase shift by pseudo-stereo 1997 Mar 11 see Fig.4 16 − 52 − % − 30 − % − − − − Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor SYMBOL PARAMETER TDA9852 CONDITIONS MIN. TYP. MAX. UNIT Automatic volume level control (AVL) Zi input impedance Vi(rms) maximum input voltage (RMS value) Gv gain, maximum boost THD < 0.2% 8.8 11.0 13.2 kΩ 2 tbf − V 5 6 7 dB maximum attenuation 14 15 16 dB Gstep equivalent step width between the input stages (soft switching system) − 1.5 − dB Viop(rms) input level at maximum boost (RMS value) − 0.1 − V input level at maximum attenuation (RMS value) − 1.125 − V Vo(rms) output level in AVL operation (RMS value) see Fig.5 160 200 250 mV VDC OFF DC offset between different gain steps voltage at pin CAV 6.50 to 6.33 V or 6.33 to 6.11 V or 6.11 to 5.33 V or 5.33 to 2.60 V; note 6 − − 6 mV Ratt discharge resistors for attack time constant AT1 = 0; AT2 = 0; note 7 340 420 520 Ω AT1 = 1; AT2 = 0; note 7 590 730 910 Ω AT1 = 0; AT2 = 1; note 7 0.96 1.2 1.5 kΩ AT1 = 1; AT2 = 1; note 7 1.7 2.1 2.6 kΩ normal mode; CCD = 0; note 8 1.6 2.0 2.4 µA − tbf − µA 16 20 24 kΩ Idec charge current for decay time power-on speed-up; CCD = 1; note 8 Selector from pins LOL, LOR, LIL and LIR to pins SOL and SOR Zi input impedance αs input isolation of one selected source to the other input Vi = 1 V; fi = 1 kHz 86 96 − dB Vi = 1 V; fi = 12.5 kHz 80 96 − dB THD < 0.5% 2 2.3 − V Vi(rms) maximum input voltage (RMS value) VDC OFF DC offset voltage at selector output by selection of any inputs − − 25 mV Zo output impedance − 80 120 Ω RL output load resistance 5 − − kΩ CL output load capacitance 0 − 2.5 nF Gv voltage gain, selector − 0 − dB 1997 Mar 11 17 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor SYMBOL PARAMETER TDA9852 CONDITIONS MIN. TYP. MAX. UNIT Audio control part; input pins VIL and VIR to pins OUTX and OUTS Zi volume input impedance 8.0 10.0 12.0 kΩ Zo output impedance − 80 120 Ω RL output load resistance 5 − − kΩ CL output load capacitance 0 − 2.5 nF Vi(rms) maximum input voltage (RMS value) THD < 0.5% 2.0 2.15 − V Vno noise output voltage CCIR 468-2 weighted; quasi peak Gc Gstep ∆Ga Gv = 16 dB − 110 220 µV Gv = 0 dB − 33 50 µV mute position − 10 − µV maximum boost − 16 − dB maximum attenuation − 71 − dB step resolution − 1 − dB step error between adjoining step − − 0.5 dB Gv = +16 to −50 dB − − 2 dB Gv = −51 to −71 dB − − 3 dB Gv = +16 to −50 dB − − 2 dB total continuous control range attenuator set error ∆GL gain tracking error αm mute attenuation 80 − − dB VDC OFF DC step offset between any adjacent step Gv = +16 to 0 dB − 0.2 10.0 mV Gv = 0 to −71 dB − − 5 mV DC step offset between any step to mute Gv = +16 to +1 dB − 2 15 mV Gv = 0 to −71 dB − 1 10 mV fi = 40 Hz − 17 − dB fi = 10 kHz − 4.5 − dB −12 − +16 − VCAP − 0.7 − V increasing supply voltage − − 2.5 V decreasing supply voltage 4.2 5 5.8 V increasing supply voltage 5.2 6 6.8 V Loudness control part LB LG maximum loudness boost loudness on; referred to loudness off; boost is determined by external components; see Fig.6 loudness control range Muting at power supply drop for OUTR and OUTS VCC-DROP supply drop for mute active Power-on reset; note 9 VRESET(STA) start of reset voltage VRESET(END) end of reset voltage 1997 Mar 11 18 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor SYMBOL PARAMETER TDA9852 CONDITIONS MIN. TYP. MAX. UNIT Digital part (I2C-bus pins); note 10 VIH HIGH level input voltage 3 − VCC VIL LOW level input voltage −0.3 − +1.5 V IIH HIGH level input current −10 − +10 µA IIL LOW level input current −10 − +10 µA VOL LOW level output voltage − − +0.4 V IIL = 3 mA V Notes to the characteristics 1. The oscillator is designed to operate together with MURATA resonator CSB503F58. Change of the resonator supplier is possible, but the resonator specification must be close to CSB503F58. 2. The internal SAP carrier level is determined by the composite input level and the level adjustment gain. 3. Frequency range 20 Hz to 20 kHz; select in to input line control; effects: linear stereo. V bus(p-p) 4. Crosstalk: 20 log --------------------V o(rms) 5. The transmission contains: a) Total initialization with MAD and SAD for volume and 11 DATA words, see also definition of characteristics b) Clock frequency = 50 kHz c) Repetition burst rate = 400 Hz d) Maximum bus signal amplitude = 5 V (p-p). 6. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, −6 dB and −15 dB. 7. Attack time constant = CAV × Ratt. 8. –G2 –G1--------- --------20 20 C AV × 0.76 V 10 – 10 Decay time = ------------------------------------------------------------------------------I dec Example: CAV = 4.7 µF; Idec = 2 µA; G1 = −9 dB; G2 = +6 dB → decay time results in 4.14 s. 9. When reset is active the GMU-bit (general mute) and the LMU-bit (LINE OUT mute) is set and the I2C-bus receiver is in the reset position. 10. The AC characteristics are in accordance with the I2C-bus specification. The maximum clock frequency is 100 kHz. Information about the I2C-bus can be found in the brochure “The I2C-bus and how to use it” (order number 9398 393 40011). 1997 Mar 11 19 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 I2C-BUS PROTOCOL I2C-bus format to read (slave transmits data) S Table 1 SLAVE ADDRESS R/W A DATA MA DATA Explanation of I2C-bus format to read (slave transmits data) NAME DESCRIPTION S START condition; generated by the master Standard SLAVE ADDRESS (MAD) 101 101 1 R/W 1 (read); generated by the master A acknowledge; generated by the slave DATA slave transmits an 8-bit data word MA acknowledge; generated by the master P STOP condition; generated by the master Table 2 P Definition of the transmitted bytes after read condition MSB FUNCTION LSB BYTE D7 D6 D5 D4 D3 D2 D1 D0 Alignment read 1 ALR1 Y SAPP STP A14 A13 A12 A11 A10 Alignment read 2 ALR2 Y SAPP STP A24 A23 A22 A21 A20 Table 3 Function of the bits in Table 2 BITS FUNCTION STP stereo pilot identification (stereo received = 1) SAPP SAP pilot identification (SAP received = 1) A1X to A2X stereo alignment read data A1X for wideband expander A2X for spectral expander Y indefinite The master generates an acknowledge when it has received the first data word ALR1, then the slave transmits the next data word ALR2. Afterwards the master generates an acknowledge, then the slave begins transmitting the first data word ALR1 etc. until the master generates no acknowledge and transmits a STOP condition. 1997 Mar 11 20 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 I2C-bus format to write (slave receives data) S SLAVE ADDRESS Table 4 R/W A SUBADDRESS A DATA A P Explanation of I2C-bus format to write (slave receives data) NAME DESCRIPTION S START condition Standard SLAVE ADDRESS (MAD) 101 101 1 R/W 0 (write) A acknowledge; generated by the slave SUBADDRESS (SAD) see Table 5 DATA see Table 6 P STOP condition If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress and auto-increment of subaddress in accordance with the order of Table 5 is performed. Table 5 Subaddress second byte after MAD MSB FUNCTION LSB REGISTER D7 D6 D5 D4 D3 D2 D1 D0 Volume right VR 0 0 0 0 0 0 0 0 Volume left VL 0 0 0 0 0 0 0 1 Control 1 (note 1) CON1 0 0 0 0 0 1 0 1 Control 2 CON2 0 0 0 0 0 1 1 0 Control 3 CON3 0 0 0 0 0 1 1 1 Alignment 1 ALI1 0 0 0 0 1 0 0 0 Alignment 2 ALI2 0 0 0 0 1 0 0 1 Alignment 3 ALI3 0 0 0 0 1 0 1 0 Note 1. In auto-increment mode it is necessary to insert 3 dummy data words between volume left and control 1. Table 6 Definition of third byte, third byte after MAD and SAD MSB FUNCTION LSB REGISTER D7 D6 D5 D4 D3 D2 D1 D0 Volume right VR 0 VR6 VR5 VR4 VR3 VR2 VR1 VR0 Volume left VL 0 VL6 VL5 VL4 VL3 VL2 VL1 VL0 Control 1 CON1 GMU AVLON LOFF CCD 0 SC2 SC1 SC0 Control 2 CON2 SAP STEREO TZCM 1 LMU EF2 EF1 EF0 Control 3 CON3 0 0 0 0 L3 L2 L1 L0 Alignment 1 ALI1 0 0 0 A14 A13 A12 A11 A10 Alignment 2 ALI2 STS 0 0 A24 A23 A22 A21 A20 Alignment 3 ALI3 ADJ AT1 AT2 0 1 TC2 TC1 TC0 1997 Mar 11 21 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor Table 7 TDA9852 Function of the bits in Table 6 BITS FUNCTION VR0 to VR6 volume control right VL0 to VL6 volume control left GMU mute control for all outputs (generate mute) AVLON AVL on/off CCD increased AVL decay current on/off LOFF switch loudness on/off SC0 to SC2 selection between line in and line out STEREO, SAP mode selection for line out TZCM zero cross mode in mute operation (right and left output stage) LMU mute control for line out EF0 to EF2 selection between mono, stereo linear, spatial stereo and pseudo mode L0 to L3 input level adjustment ADJ stereo adjustment on/off A1X to A2X stereo alignment data A1X for wideband expander A2X for spectral expander AT1 and AT2 attack time at AVL TC0 to TC2 timing current alignment data STS stereo level switch Table 8 Volume setting DATA FUNCTION Gv (dB) V6 V5 V4 V3 V2 V1 V0 16 1 1 1 1 1 1 1 15 1 1 1 1 1 1 0 14 1 1 1 1 1 0 1 13 1 1 1 1 1 0 0 12 1 1 1 1 0 1 1 11 1 1 1 1 0 1 0 10 1 1 1 1 0 0 1 9 1 1 1 1 0 0 0 8 1 1 1 0 1 1 1 7 1 1 1 0 1 1 0 6 1 1 1 0 1 0 1 5 1 1 1 0 1 0 0 4 1 1 1 0 0 1 1 3 1 1 1 0 0 1 0 2 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1997 Mar 11 22 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor FUNCTION Gv (dB) TDA9852 DATA V6 V5 V4 V3 V2 V1 V0 0 1 1 0 1 1 1 1 −1 1 1 0 1 1 1 0 −2 1 1 0 1 1 0 1 −3 1 1 0 1 1 0 0 −4 1 1 0 1 0 1 1 −5 1 1 0 1 0 1 0 −6 1 1 0 1 0 0 1 −7 1 1 0 1 0 0 0 −8 1 1 0 0 1 1 1 −9 1 1 0 0 1 1 0 −10 1 1 0 0 1 0 1 −11 1 1 0 0 1 0 0 −12 1 1 0 0 0 1 1 −13 1 1 0 0 0 1 0 −14 1 1 0 0 0 0 1 −15 1 1 0 0 0 0 0 −16 1 0 1 1 1 1 1 −17 1 0 1 1 1 1 0 −18 1 0 1 1 1 0 1 −19 1 0 1 1 1 0 0 −20 1 0 1 1 0 1 1 −21 1 0 1 1 0 1 0 −22 1 0 1 1 0 0 1 −23 1 0 1 1 0 0 0 −24 1 0 1 0 1 1 1 −25 1 0 1 0 1 1 0 −26 1 0 1 0 1 0 1 −27 1 0 1 0 1 0 0 −28 1 0 1 0 0 1 1 −29 1 0 1 0 0 1 0 −30 1 0 1 0 0 0 1 −31 1 0 1 0 0 0 0 −32 1 0 0 1 1 1 1 −33 1 0 0 1 1 1 0 −34 1 0 0 1 1 0 1 −35 1 0 0 1 1 0 0 −36 1 0 0 1 0 1 1 −37 1 0 0 1 0 1 0 −38 1 0 0 1 0 0 1 1997 Mar 11 23 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 DATA FUNCTION Gv (dB) V6 V5 V4 V3 V2 V1 V0 −39 1 0 0 1 0 0 0 −40 1 0 0 0 1 1 1 −41 1 0 0 0 1 1 0 −42 1 0 0 0 1 0 1 −43 1 0 0 0 1 0 0 −44 1 0 0 0 0 1 1 −45 1 0 0 0 0 1 0 −46 1 0 0 0 0 0 1 −47 1 0 0 0 0 0 0 −48 0 1 1 1 1 1 1 −49 0 1 1 1 1 1 0 −50 0 1 1 1 1 0 1 −51 0 1 1 1 1 0 0 −52 0 1 1 1 0 1 1 −53 0 1 1 1 0 1 0 −54 0 1 1 1 0 0 1 −55 0 1 1 1 0 0 0 −56 0 1 1 0 1 1 1 −57 0 1 1 0 1 1 0 −58 0 1 1 0 1 0 1 −59 0 1 1 0 1 0 0 −60 0 1 1 0 0 1 1 −61 0 1 1 0 0 1 0 −62 0 1 1 0 0 0 1 −63 0 1 1 0 0 0 0 −64 0 1 0 1 1 1 1 −65 0 1 0 1 1 1 0 −66 0 1 0 1 1 0 1 −67 0 1 0 1 1 0 0 −68 0 1 0 1 0 1 1 −69 0 1 0 1 0 1 0 −70 0 1 0 1 0 0 1 −71 0 1 0 1 0 0 0 Mute 0 1 0 0 1 1 1 1997 Mar 11 24 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor Table 9 TDA9852 Loudness setting Table 11 Selector setting CHARACTERISTIC DATA LOFF With loudness 0 Linear 1 Table 10 Effects setting DATA FUNCTION EF2 EF1 DATA FUNCTION(1) SC2 SC1 SC0 Inputs LOR and LOL 0 0 0 Inputs LOR and LOR 0 0 1 Inputs LOL and LOL 0 1 0 Inputs LOL and LOR 0 1 1 EF0 Inputs LIR and LIL 1 0 0 1 0 1 Stereo linear on 0 0 0 Inputs LIR and LIR Pseudo on 0 0 1 Inputs LIL and LIL 1 1 0 Spatial stereo; 30% anti-phase crosstalk 0 1 0 Inputs LIL and LIR 1 1 1 Spatial stereo; 50% anti-phase crosstalk 0 1 1 Forced mono 1 1 1 Note 1. Input connected to outputs SOR and SOL. Table 12 Switch setting at line out LINE OUT SIGNALS AT LOL LOR DATA TRANSMISSION STATUS INTERNAL SWITCH, READABLE BITS: STP, SAPP SETTING BITS STEREO SAP SAP SAP SAP received 1 1 Mute mute no SAP received 1 1 Left right STEREO received 1 0 Mono mono no STEREO received 1 0 Mono SAP SAP received 0 1 Mono mute no SAP received 0 1 Mono mono independent 0 0 Table 13 Zero cross detection setting FUNCTION DATA TZCM Direct mute control 0 Mute control delayed until the next zero crossing 1 Table 14 Mute setting FUNCTION DATA GMU FUNCTION DATA LMU Forced mute at OUTR, OUTL and OUTS 1 forced mute at LOR and LOL 1 Audio processor controlled outputs 0 stereo processor controlled outputs 0 1997 Mar 11 25 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 Table 15 AVL attack time Table 21 Level adjust setting DATA GL (dB) FUNCTION DATA L3 L2 L1 L0 +4.0 1 1 1 1 0 +3.5 1 1 1 0 1 +3.0 1 1 0 1 1 +2.5 1 1 0 0 +2.0 1 0 1 1 +1.5 1 0 1 0 DATA +1.0 1 0 0 1 0 +0.5 1 0 0 0 1 0.0 0 1 1 1 −0.5 0 1 1 0 −1.0 0 1 0 1 DATA −1.5 0 1 0 0 Automatic volume control off 0 −2.0 0 0 1 1 Automatic volume control on 1 −2.5 0 0 1 0 −3.0 0 0 0 1 −3.5 0 0 0 0 AT1 AT2 Ratt = 420 Ω 0 0 Ratt = 730 Ω 1 Ratt = 1200 Ω 0 Ratt = 2100 Ω 1 Table 16 ADJ bit setting FUNCTION Stereo decoder operation mode Auto adjustment of channel separation Table 17 AVLON bit setting FUNCTION Table 18 CCD bit setting FUNCTION DATA Load current for normal AVL decay time 0 Increased load current 1 Table 19 STS bit setting (pilot threshold stereo on) FUNCTION DATA STon ≤ 35 mV 1 STon ≤ 30 mV 0 Table 20 Timing current setting FUNCTION IS RANGE DATA TC2 TC1 TC0 +30% 1 0 0 +20% 1 0 1 +10% 1 1 0 Nominal 0 1 1 −10% 0 1 0 −20% 0 0 1 −30% 0 0 0 1997 Mar 11 26 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 Table 22 Alignment data for expander in read register ALR1 and ALR2 and in write register ALI1 and ALI2 DATA FUNCTION Gain increase Nominal gain Gain decrease 1997 Mar 11 D4 AX4 D3 AX3 D2 AX2 D1 AX1 D0 AX0 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 0 1 0 1 1 0 0 0 1 0 1 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 27 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 MHA311 0 handbook, full pagewidth (1) phase (degree) (2) −100 (3) −200 −300 −400 10 102 103 104 f (Hz) 105 (1) see Table 23. (2) see Table 23. (3) see Table 23. Fig.4 Pseudo (phase in degrees) as a function of frequency (left output). Table 23 Explanation of curves in Fig.4 CURVE CAPACITANCE AT PIN CPS1 (nF) CAPACITANCE AT PIN CPS2 (nF) EFFECT 1 15 15 normal 2 5.6 47 intensified 3 5.6 68 more intensified 1997 Mar 11 28 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 MHA312 300 7 handbook, full pagewidth Vo(rms) (mV) VCAV (V) (1) 6 250 (2) 5 200 4 (3) 160 3 2 100 10−2 (1) VCAV (2) Vo max(rms) (3) Vo min(rms) 1 10−1 1 VI(rms) (V) 10 AVL measured at pin EOL/EOR. Y1 axis output level in AVL operation with typically 200 mV. Y2 axis VCAV DC voltage at pin CAV corresponds with typical gain steps in range of +6 to −15 dB. Fig.5 Automatic level control diagram. MHA313 25 16 14 15 9 4 5 −1 −6 −5 −11 −16 −15 −21 −26 −25 −31 −36 −35 10 102 103 f (Hz) Fig.6 Volume control with loudness (including low roll-off frequency). 1997 Mar 11 29 104 parameter: volume gain setting (dB) VdB (VQX 0) (dB) handbook, full pagewidth Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 INTERNAL PIN CONFIGURATIONS + 1 4.25 V 2 80 Ω 4.25 V + 1.33 kΩ MHA315 MHA314 Fig.7 Pins OUTL, SOL, SOR and OUTR. 3 Fig.8 Pins LDL and LDR. 4.25 V 4 + + 4.25 V 10.58 kΩ 4.8 kΩ 15 kΩ 6.8 kΩ MHA317 MHA316 Fig.9 Pins VIL and VIR. Fig.10 Pins EOL and EOR. 6 + 5 + 3.4 kΩ 3.4 kΩ MHA318 MHA319 Fig.11 Pin CAV. 1997 Mar 11 Fig.12 Pin Vref. 30 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 8 7 4.25 V 1 + 4.25 V + 2 3 20 kΩ 20 kΩ 1.75 kΩ MHA320 8 MHA321 Fig.13 Pins LIL and LIR. + 10 Fig.14 Pins AVL and AVR. 4.25 V 11 + 5 kΩ MHA323 MHA322 Fig.15 Pins LOL and LOR. 13 Fig.16 Pins CTW and CTS. 4.25 V + 15 + 6 kΩ MHA325 MHA324 Fig.17 Pins CW and CS. 1997 Mar 11 Fig.18 Pin VEO. 31 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 16 17 4.25 V + + 600 Ω 10 kΩ MHA327 MHA326 Fig.19 Pin VEI. + Fig.20 Pin CNR. 18 19 4.25 V + 20 kΩ 20 kΩ MHA328 Fig.21 Pin CM. Fig.22 Pin CDEC. 21 5 V 22 1.8 kΩ 5V 1.8 kΩ MHA331 MHA330 Fig.23 Pin SDA. 1997 Mar 11 Fig.24 Pin SCL. 32 MHA329 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 24 4.25 V + 23 apply +8.5 V to this pin + MHA332 30 kΩ Fig.25 Pin VCC. MHA333 Fig.26 Pin COMP. 25 + 26 4.25 V + 4.7 kΩ 300 Ω 3.5 kΩ 5 kΩ MHA335 MHA334 Fig.27 Pin VCAP. + 27 Fig.28 Pin CP1. 4.25 V 28 4.25 V + 8.5 kΩ 12 kΩ MHA336 10 kΩ Fig.29 Pin CP2. 1997 Mar 11 10 kΩ Fig.30 Pin CPH. 33 MHA337 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 30 29 + + 3 kΩ MHA339 MHA338 Fig.31 Pin CADJ. Fig.32 Pin CER. 38 31 4.25 V + + 10 kΩ 15 kΩ 10 kΩ MHA341 MHA340 Fig.33 Pins CMO and CSS. 1997 Mar 11 Fig.34 Pins CPS1 and CPS2. 34 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 PACKAGE OUTLINES seating plane SDIP42: plastic shrink dual in-line package; 42 leads (600 mil) SOT270-1 ME D A2 L A A1 c e Z b1 (e 1) w M MH b 22 42 pin 1 index E 1 21 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.08 0.51 4.0 1.3 0.8 0.53 0.40 0.32 0.23 38.9 38.4 14.0 13.7 1.778 15.24 3.2 2.9 15.80 15.24 17.15 15.90 0.18 1.73 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 90-02-13 95-02-04 SOT270-1 1997 Mar 11 EUROPEAN PROJECTION 35 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 10 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT307-2 1997 Mar 11 EUROPEAN PROJECTION 36 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 °C. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). WAVE SOLDERING Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. If wave soldering cannot be avoided, the following conditions must be observed: The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). REPAIRING SOLDERED JOINTS During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. QFP REFLOW SOLDERING A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Reflow soldering techniques are suitable for all QFP packages. REPAIRING SOLDERED JOINTS The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9398 510 63011). 1997 Mar 11 Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 37 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Mar 11 38 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 NOTES 1997 Mar 11 39 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA53 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547047/1200/02/pp40 Date of release: 1997 Mar 11 Document order number: 9397 750 01766