INTEGRATED CIRCUITS DATA SHEET TDA8421 Hi-fi stereo audio processor; I2C bus Product specification File under Integrated Circuits, IC02 May 1988 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 GENERAL DESCRIPTION The TDA8421 is a monolithic bipolar integrated stereo sound circuit with a loudspeaker channel (CH1) and a headphone channel (CH2), digital controlled via the I2C bus, for application in hi-fi audio and television sound. Features • Input selector • Mode selector • Loudspeaker channel (CH1); with volume control, balance control and mute • Headphone channel (CH2); with volume control, balance control and mute • Pseudo stereo and spatial function • Bass and treble control • Electrostatic discharge protection diodes QUICK REFERENCE DATA PARAMETER SYMBOL MIN. TYP. MAX. UNIT 7,5 12 14 V Supply voltage (pin 4) VCC Input signal handling VI 2 − − V Vi − 200 − mV (S+N)/N − 90 − dB Total harmonic distortion THD − 0,05 − % Channel separation α − 75 − dB Volume control range CH1 G −62 − 16 dB Treble control range G −12 − 12 dB Bass control range G −12 − 15 dB Volume control range CH2 G −62 − 0 dB Input sensitivity full power at the output stage Signal plus noise-to-noise ratio PACKAGE OUTLINE 28-lead dual in-line; plastic (SOT117); SOT 117-1; 1996 november 19. May 1988 2 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus * These values are dependent on the required frequency response and effect. Fig.1 Block diagram. TDA8421 May 1988 3 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 PINNING Fig.2 Pinning diagram. FUNCTIONAL DESCRIPTION Input selector The input to channel 1 (CH1) and channel 2 (CH2) is determined by the input selector. The selection is made from the following AF input signals: • IN1 L (pin 26); IN1 R (pin 28) or • IN2 L (pin 1); IN2 R (pin 3) Where IN1 is an internal input signal and IN2 an external input signal. Mode selector For each channel (CH1 and CH2) there is a mode selector which selects between stereo, sound A and sound B in the event of bilingual transmission. Both mode selectors can be controlled independently. May 1988 4 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 Headphone channel (CH2) Bias and power supply Volume control and balance The TDA8421 includes a bias and power supply stage, which generates a voltage of 1⁄2 VCC with a low output impedance and injector currents for the logic part. The stages for volume control for CH2 consist of two parts for left and right. In each part the gain can be adjusted between 0 and −62 dB in steps of 2 dB. An additional step allows an attenuation of ≥ 90 dB. Both parts can be controlled independently over the whole range, which allows the balance to be varied by controlling the volume of left and right. Power-on reset The on-chip power-on reset circuit sets the mute bit to active, which mutes both the loudspeaker channel (CH1) and the headphone channel (CH2). The muting can be switched by transmission of the mute bit. Loudspeaker channel (CH1) I2C bus receiver and data handling Volume control and balance Bus specification The loudspeaker channel (CH1) also consists of two parts for volume control (left and right). In each part the gain can be adjusted between + 16 dB and −62 dB in steps of 2 dB. An additional step allows an attenuation of ≥ 90 dB. Both parts can be controlled independently over the whole range, which allows the balance to be varied by controlling the volume of left and right. The TDA8421 is controlled via the 2-wire I2C bus by a microcomputer. The two wires (SDA - serial data, SCL serial clock) carry information between the devices connected to the bus. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor. When the bus is free both lines are HIGH. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The set up and hold times are specified in AC CHARACTERISTICS. Stereo/pseudo stereo/spatial stereo mode It is possible to select three modes. Stereo, pseudo or spatial stereo. The pseudo stereo mode receives mono transmissions and the stereo and spatial stereo mode receives stereo transmissions. A HIGH-to-LOW transition of the SDA line while SCL is HIGH is defined as a start condition. A LOW-to-HIGH transition of the SDA line while SCL is HIGH is defined as a stop condition. The bus receiver will be reset by the reception of a start condition. The bus is considered to be busy after the start condition. The bus is considered to be free again after a stop condition. Bass control The bass control stage can be switched from an emphasis of 15 dB to an attenuation of 12 dB for low frequencies in steps of 3 dB. Treble control The treble control stage can be switched from + 12 dB to −12 dB in steps of 3 dB. Module address Data transmission to the TDA8421 starts with the module address MAD. Fig.3 TDA8421 module address. The module address is determined by pin 16. When connected to ground MAD = 0; when connected to VCC MAD = 1. Thus two TDA8421s can be selected within a system. May 1988 5 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 Subaddress After the module address byte a second byte is used to select the functions for both channels: • CH1 - Volume left, volume right, bass, treble and switch functions • CH2 - Volume left, volume right and switch functions The subaddress SAD is stored within the TDA8421. Table 1 defines the coding of the second byte after the module address MAD. Table 1 Second byte after module address MAD 128 64 32 16 8 4 2 1 MSB FUNCTION volume left CH1 CH2 LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 volume right 0 0 0 0 0 0 0 1 bass 0 0 0 0 0 0 1 0 treble 0 0 0 0 0 0 1 1 switch functions 0 0 0 0 1 0 0 0 volume left 0 0 0 0 0 1 0 0 volume right 0 0 0 0 0 1 0 1 switch functions 0 0 0 0 1 1 0 0 subaddress SAD Definition of 3rd byte A third byte is used to transmit data to the TDA8421. Table 2 defines the coding of the third byte after module address MAD and subaddress SAD. Table 2 Third byte after module address MAD and subaddress SAD MSB FUNCTION volume left CH1 CH2 LSB 7 VL1 1 6 1 5 V05 4 V04 3 V03 2 V02 1 V01 0 V00 volume right VR1 1 1 V15 V14 V13 V12 V11 V10 bass BA 1 1 1 1 BA3 BA2 BA1 BA0 treble TR 1 1 1 1 TR3 TR2 TR1 TR0 switch functions S1 1 1 MU EFL STL ML1 ML0 IS volume left VL2 1 1 V25 V24 V23 V22 V21 V20 volume right VR2 1 1 V35 V34 V33 V32 V31 V30 switch functions S2 1 1 1 1 EXS MH1 MH0 1 May 1988 6 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 Table 4 Truth tables Mode selectors Truth tables for the switch functions Table 3 CH1 Input selector mode function IN1 IN2 Table 5 ML1 MH0 MH1 IS stereo 1 1 1 1 0 sound A 1 0 1 0 1 sound B 0 1 0 1 ---------- 0 0 0 0 Stereo/pseudo stereo/spatial stereo choise ML0 CH2 Table 6 STL Mute EFL mute MU spatial 1 1 active; automatic stereo 1 0 after POR(1) 1 not active 0 pseudo 0 1 ----------- 0 0 Notes 1. Attenuation ≥ 90 dB; POR = Power-On Reset. Table 7 Output for external switch EXSN EXS ground 1 open collector 0 Truth tables for the volume base and treble controls. Table 8 Volume control CH1 V×5 CH2 V×4 V×3 V×2 V×1 V×0 16 0 1 1 1 1 1 1 14 −2 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ −46 −62 1 0 0 0 0 0 −48 ≤−90 0 1 1 1 1 1 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ −62 ≤−90 0 1 1 0 0 0 ≤−90 ≤−90 0 1 0 1 1 1 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ≤−90 ≤−90 0 0 0 0 0 0 Note 1. The values of CH1 and CH2 are in 2 dB/step measured in dBs. May 1988 7 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus Table 9 TDA8421 Bass control 3dB/STEP (dB) BA3 BA2 BA1 BA0 15 1 1 1 1 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 15 1 0 1 1 12 1 0 1 0 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0 0 1 1 0 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- −12 0 0 1 0 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- −12 0 0 0 0 TR2 TR1 TR0 Table 10 Treble control 3dB/STEP (dB) TR3 12 1 1 1 1 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 12 1 0 1 0 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0 0 1 1 0 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- −12 0 0 1 0 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- −12 0 0 0 0 May 1988 8 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 Sequence of data transmission After a power-on reset all eight functions have to be adjusted with eight data transmissions. It is recommended that data information for switch functions in CH1 are transmitted last because all functions have to be adjusted when the muting is switched off. The sequence of transmission of other data information is not critical. The order of data transmission is shown in Figures 4 and 5. The number of data transmissions is unrestricted but before each data byte the module address MAD and the correct subaddress SAD is required. Fig.4 Data transmission after a power-on reset. Fig.5 Data transmission except after power-on reset. May 1988 9 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) PARAMETER SYMBOL MIN. MAX. UNIT VCC 0 16 V pins 2, 6, 8 to 10, 19 to 21, 23 to 25, 27 Vcap 0 VCC V pin 13 VSDA 0 VCC V pin 14 VSCL 0 VCC V pin 15 VEXSN 0 VCC V pin 16 VMAD 0 VCC V VI, VO 0 VCC V IO − 45 mA Ptot − 1350 mW Tamb 0 70 °C Storage temperature range Tstg −25 150 °C Electrostatic handling(1) ±VESD − 2000 V Supply voltage Voltage range at pins for external capacitors Voltage range at pins 1, 3, 7, 11, 18, 22, 26, 28 Output current at pins 7, 11, 18, 22 Total power dissipation at Tamb < 70 °C Operating ambient temperature range Note 1. Equivalent to discharging a 100 pF capacitor through a 1,5 kΩ resistor. May 1988 10 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 DC CHARACTERISTICS VCC = 12 V; Tamb = 25 °C; unless otherwise specified PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 7,5 12 14 V ICC − 42 55 mA VI 5,4 6,0 6,6 V VIH 3,0 − VCC V input voltage LOW VIL 0 − 1,5 V input current HIGH IIH − − 1,0 µA input current LOW IIL − 1 10 µA input voltage HIGH VIH 3,0 − VCC V input voltage LOW VIL −0,3 − 1,5 V input current HIGH IIH − − 1,0 µA input current LOW IIL − 1 10 µA VO 5,4 1⁄ 2 VCC 6,6 V pins 6 to 10; 19 to 21; 23 to 25 Vcap.n − 1⁄ 2 VCC − V pin 2 Vcap.2 − VCC−0,1 − V Output voltage HIGH VEXSNH − − 16 V Output voltage LOW VEXSNL − − 0,3 V Supply voltage (pin 4) Supply current at VCC = 12 V Internal input voltage IN1 L,R (pins 26,28) IN2 L,R (pins 1,3) DC voltage internally generated; capacitive coupling recommended MAD (pin 16) input voltage HIGH SDA; SCL (pins 13 and 14) Output voltage at CH1 (pins 11 and 18); CH2 (pins 7 and 22) pins with external capacitors External switch (pin 15) at IEXSN = 1 mA May 1988 11 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 AC CHARACTERISTICS VCC = 12 V; bass/treble in linear position; pseudo and spatial stereo off; RL > 10 kΩ; CL < 100 pF; Tamb = 25 °C unless otherwise specified. PARAMETER SYMBOL MIN. TYP. MAX. UNIT I2C bus timing (see Fig.6) SDA, SCL (pin 13 and 14) Clock frequency range fSCL 0 − 100 kHz The HIGH period of the clock tHIGH 4 − − µs The LOW period of the clock tLOW 4,7 − − µs SCL rise time tr − − 1 µs SCL fall time tf − − 0,3 µs Set-up time for start condition tSU;STA 4,7 − − µs Hold time for start condition tHD; STA 4 − − µs Set-up time for stop condition tSU; STO 4,7 − − µs tBUF 4,7 − − µs tSU; DAT 250 − − ns Vi(rms) 2 − − V Rn-5 35 50 − kΩ f 20 − 20 000 Hz Time bus must be free before a new transmission can start Set-up time DATA Input signals IN1 L (pin 26) IN1 R (pin 28) IN2 L (pin 1) IN2 R (pin 3) Input signal handling (r.m.s. value) at Vu = −4 dB; THD ≤ 0,5% Input resistance Frequency response (−0,5 dB) bass and treble in linear position; stereo mode; effects off May 1988 12 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus PARAMETER TDA8421 SYMBOL MIN. TYP. MAX. UNIT LOUDSPEAKER CHANNEL OUTPUTS CH1 LEFT (pin 18); CH1 RIGHT (pin 11) Output voltage range (r.m.s. value) at THD ≤ 0,5% Vo(rms) 2 − − V Load resistance RL 10 − − kΩ Output impedance ZO − − 100 Ω gain = 16 dB Vn − 90 − µV gain = 0 dB Vn − 20 40 µV gain = ≤ −90 dB Vn − 15 − µV (f = 20 Hz to 12,5 kHz) for Vi(rms) = 0,5 V; gain = + 16 dB to −30 dB THD − 0,05 0,2 % for Vi(rms) = 1,0 V; gain = +2 dB to −30 dB THD − 0,07 0,2 % for Vi(rms) = 2,0 V; gain = −4 dB to −30 dB THD − 0,1 − % αcr − 75 − dB RR100 − 50 − dB αL − 110 − dB Noise level weighted according to CCIR468-2 Total harmonic distortion Channel separation at 10 kHz gain = 0 dB Ripple rejection (gain = 0 dB; bass and treble in linear position) fripple = 100 Hz Crosstalk attenuation from logic inputs to AF outputs (gain = 0 dB; bass and treble in linear position) VOLUME CONTROL For truth table see Table 8 May 1988 13 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus PARAMETER TDA8421 SYMBOL MIN. TYP. MAX. UNIT Loudspeaker channel (CH1) Control range at f = 1 kHz maximum voltage gain (16 dB step) Gmax 15 − − dB minimum voltage gain (−62 dB step) Gmin −60 − − dB last position Goff −80 −85 − dB mute position Gmute −85 −90 − dB Gstep − 2 − dB/step gain from 16 dB to −30 dB ∆G − − 0,5 dB gain from −30 dB to −62 dB ∆G − − 1 dB G 11 12 13 dB G 11 12 13 dB Gstep − 3 − dB/step G 14 15 16 dB G 11 12 13 dB Gstep − 3 − dB/step α − 50 − % Resolution Gain difference between left and right AF channel (note 1) TREBLE CONTROL (CH1) For truth table see Table 10 Control range for C10-5; C19-5 = 5,6 nF Maximum emphasis at 15 kHz with respect to linear position Maximum attenuation at 15 kHz with respect to linear position Resolution BASS CONTROL For truth table see Table 9 Control range for C8-9; C20-21 = 33 nF Maximum emphasis at 40 kHz with respect to linear position Maximum attenuation at 40 kHz with respect to linear position Resolution SPATIAL AND PSEUDO FUNCTION Spatial: Antiphase crosstalk Pseudo: Phase shift (see Fig.15) May 1988 14 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus PARAMETER TDA8421 SYMBOL MIN. TYP. MAX. UNIT HEADPHONE CHANNEL OUTPUTS CH2 LEFT (pin 22); CH2 RIGHT (pin 7) Output voltage range (r.m.s. value) at THD ≤ 0,5% Vo(rms) 2 − − V Load resistance RL 10 − − kΩ Output impedance ZO − − 100 Ω (weighted according to CCIR468-2) gain = 0 dB Vn − 15 − µV gain = 16 dB Vn − 12 25 µV gain = ≤ −90 dB Vn − 10 − µV for Vi(rms) = 0,2 V; gain = 0 dB to −30 dB THD − 0,01 0,2 % for Vi(rms) = 1,0 V; gain = 0 dB to −30 dB THD − 0,1 − % THD − 0,3 − % αcr − 75 − dB RR100 − 50 − dB αL − 110 − dB α 65 70 − dB α 95 100 − dB Noise level Total harmonic distortion (f = 20 Hz to 12,5 kHz) for Vi(rms) = 2,0 V gain = −4 dB to −30 dB Channel separation at 10 kHz gain = 0 dB Ripple rejection (gain = 0 dB; bass and treble in linear position) fripple = 100 Hz Crosstalk attenuation from logic inputs to AF outputs (gain = 0 dB; bass and treble in linear position) Crosstalk between any input/output f = 100 Hz to 12,5 kHz Crosstalk IN1/IN2 gain = 0 dB; RG = 0 May 1988 15 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus PARAMETER TDA8421 SYMBOL MIN. TYP. MAX. UNIT Headphone channel (CH2) Control range maximum voltage gain (0 dB step) Gmax −1 − − dB minimum voltage gain (−62 dB step) Gmin −57 − − dB last position Goff −80 −85 − dB mute position Gmute −85 −90 − dB Gstep − 2 − dB/step gain from 0 dB to −40 dB ∆G − − 0,5 dB gain from −40 dB to −62 dB ∆G − − 2 dB Resolution Gain difference between left and right AF channel (note 1) Note to the AC characteristics 1. Balance is realized via software by different volume settings in both channels. May 1988 16 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 tSU; STA = start code set-up time tHD; STA = start code hold time tSU; STO = stop code set-up time tBUF = BUS free time tSU; DAT = data set-up time tHD; DAT = DATA hold time Fig.6 Timing requirements for I 2 C bus. Fig.7 May 1988 Distortion loudspeaker channel CH1 as a function of the output voltage with gain as parameter. Fig.8 17 Distortion loudspeaker channel CH1 as a function of the output voltage with input voltage as parameter. Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 Fig.9 Channel separation loudspeaker channel CH1 as a function of frequency. Fig.10 Signal-to-noise ratio as a function of output power. Input voltage Vi = 0,5 V; according to CCIR; quasi peak; Po = 15 W. May 1988 18 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 Fig.11 Crosstalk 2-tone mode as a function of frequency. CH1: mode AA, Gain + 16 dB; CH2: mode BB, Gain 0 dB. Signal input RIGHT; input LEFT to ground, measured at output CH1. Fig.12 Crosstalk between IN1 and IN2 as a function of frequency; measured at output CH1; RG = 0. a) Gain = + 16 dB; Vi = 200 mV. b) Gain = 0 dB; Vi = 1 V. May 1988 19 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 Fig.13 Bass and treble tone control. Cbass = 33 nF, Ctreble = 5,6 nF. Fig.14 Bass and treble tone control. Cbass = 68 nF, Ctreble = 3.9 nF. May 1988 20 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 CURVE Fig.15 Pseudo (phase) as a function of frequency CH 1 left. May 1988 21 PIN 24 (nF) PIN (nF) EFFECT 1 15 15 normal 2 5,6 47 intensified 3 5,6 68 more intensified Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 Fig.16 Test and application circuit diagram. May 1988 22 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 Fig.17 Turn-on/off power supply circuit diagram. Fig.18 Turn-on behaviour; C = 2,2 µF; RL = 10 kΩ. Fig.19 Turn-off behaviour; without modulation. Fig.20 Turn-off behaviour; with modulation (shaded area). May 1988 ICC = 45 mA; Iload = 259 mA; ton = 2,64 ms; toff = 102 ms. 23 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 Fig.21 Level diagram loudspeaker channel CH1 with Vi(min) = 200 mV; Vo = 1,25 for Pmax. Fig.22 Level diagram headphone channel CH2 with Vi = 200 mV; Vo = 200 mV for Pmax. May 1988 24 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 PACKAGE OUTLINE seating plane handbook, full pagewidthdual in-line package; 28 leads (600 mil) DIP28: plastic SOT117-1 ME D A2 L A A1 c e Z w M b1 (e 1) b MH 15 28 pin 1 index E 1 14 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.1 0.51 4.0 1.7 1.3 0.53 0.38 0.32 0.23 36.0 35.0 14.1 13.7 2.54 15.24 3.9 3.4 15.80 15.24 17.15 15.90 0.25 1.7 inches 0.20 0.020 0.16 0.066 0.051 0.020 0.014 0.013 0.009 1.41 1.34 0.56 0.54 0.10 0.60 0.15 0.13 0.62 0.60 0.68 0.63 0.01 0.067 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT117-1 051G05 MO-015AH May 1988 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-14 25 Philips Semiconductors Product specification Hi-fi stereo audio processor; I2C bus TDA8421 with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. May 1988 26