INTEGRATED CIRCUITS DATA SHEET TDA4681 Video processor with automatic cut-off and white level control Product specification Supersedes data of April 1993 File under Integrated Circuits, IC02 1997 Mar 04 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4681 FEATURES • Operates from an 8 V DC supply • Black level clamping of the colour difference, luminance and RGB input signals with coupling-capacitor DC level storage • Two fully-controlled, analog RGB inputs, selected either by fast switch signals or via I2C-bus GENERAL DESCRIPTION • Saturation, contrast and brightness adjustment via I2C-bus The TDA4681 is a monolithic integrated circuit with a colour difference interface for video processing in TV receivers. Its primary function is to process the luminance and colour difference signals from multistandard colour decoders, TDA4555, TDA4650/T, TDA4655/T or TDA4657, Colour Transient Improvement (CTI) IC, TDA4565, Picture Signal Improvement (PSI) IC, TDA4670 or from a feature module. • Same RGB output black levels for Y/CD and RGB input signals • Timing pulse generation from either a 2 or 3-level sandcastle pulse for clamping, horizontal and vertical synchronization, cut-off and white level timing pulses • Automatic cut-off control with picture tube leakage current compensation The required input signals are: • Luminance and negative colour difference signals • Software-based automatic white level control or fixed white levels via I2C-bus • 2 or 3-level sandcastle pulse for internal timing pulse generation • Cut-off and white level measurement pulses in the last 4 lines of the vertical blanking interval (I2C-bus selection for PAL, SECAM, or NTSC, PAL-M) • I2C-bus data and clock signals for microcontroller control. • Increased RGB signal bandwidths for progressive scan and 100 Hz operation (selected via I2C-bus) Two sets of analog RGB colour signals can also be inserted, e.g. one from a peritelevision connector and the other from an on-screen display generator; both inputs are fully-controlled internally. The TDA4681 includes full I2C-bus control of all parameters and functions with automatic cut-off and white level control of the picture tube cathode currents. It provides RGB output signals for the video output stages. • Two switch-on delays to prevent discolouration before steady-state operation • Average beam current and peak drive limiting • PAL/SECAM or NTSC matrix selection via I2C-bus • Three adjustable reference voltage levels (via I2C-bus) for automatic cut-off and white level control There is a very similar IC available, TDA4680. The only differences are in the NTSC matrix. • Emitter-follower RGB output stages to drive the video output stages • Hue control output for the TDA4555, TDA4650/T, TDA4655/T or TDA4657. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA4681 TDA4681WP 1997 Mar 04 DIP28 PLCC28 DESCRIPTION VERSION plastic dual in-line package; 28 leads (600 mil) SOT117-1 plastic leaded chip carrier; 28 leads SOT261-2 2 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4681 QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VP supply voltage (pin 5) 7.2 8.0 8.8 V IP supply current (pin 5) − 85 − mA V8(p-p) luminance input (peak-to-peak value) − 0.45 − V V6(p-p) −(B − Y) input (peak-to-peak value) − 1.33 − V V7(p-p) −(R − Y) input (peak-to-peak value) − 1.05 − V V14 3-level sandcastle pulse H+V − 2.5 − V H − 4.5 − V BK − 8.0 − V H+V − 2.5 − V BK − 4.5 − V − 0.7 − V 2-level sandcastle pulse Vi(p-p) RGB input signals at pins 2, 3, 4, 10, 11 and 12 (peak-to-peak value) Vo(b-w) RGB outputs at pins 24, 22 and 20 (black-to-white value) − 2.0 − V Tamb operating ambient temperature 0 − 70 °C 1997 Mar 04 3 4 1 2 3 4 G2 B2 6 −(B − Y) R2 7 FSW2 8 12 B1 Y 11 −(R − Y) 10 R1 G1 13 14 sandcastle pulse FSW1 28 27 SCL I2C-bus SDA B G R FAST SIGNAL SOURCE SWITCH, BLANKING 1 FSDIS2, FSON2, FSDIS1, FSON1 SATOF I2C-bus data and control signals PAL/SECAM, NTSC MATRIX NMEN SANDCASTLE BK PULSE H+V DETECTOR (H) TDA4681 R B G R BRIGHTNESS ADJUST, G BLANKING 2, MEASUREMENT B PULSES Fig.1 Block diagram. SATURATION AND CONTRAST ADJUST 4 x 6-BIT DACs PEAK DRIVE AND AVERAGE BEAM CURRENT LIMITING 6-BIT DAC 9 WHITE POINT ADJUST 3 x 6-BIT DACs 3 x 6-BIT REFERENCE REGISTERS, DAC R B G B 21 G 23 CUT-OFF ADJUST, OUTPUT STAGES R 25 BCOF B G MED703 RGB outputs average beam current cut-off storage 20 22 24 15 peak drive limiting storage 16 RC leakage storage R RW cut-off control 17 18 white level 19 control 3 x 2-BIT WHITE LEVEL REGISTERS AND PONRES WHITE LEVEL AND CUT-OFF COMPARATORS RAR leakage, cut-off and white level current input Video processor with automatic cut-off and white level control VP = 8 V 5 SUPPLY B G R Y-MATRIX timing pulses TIMING GENERATOR 1st AND 2nd SWITCH-ON DELAYS A05 to A00, A15 to A10, A25 to A20, A35 to A30 AA5 to AA0 A45 to A40, A55 to A50, A65 to A60 BCOF, FSBL, FSWL, WPEN, VBW2, VBW1, VBW0 SC5 DELOF 2 x 8-BIT CONTROL REGISTERS BREN I2C-BUS TRANSCEIVER A75 to A70, A85 to A80, A95 to A90 PONRES, CB0 and CB1, CG0 and CG1, CR0 and CR1 handbook, full pagewidth 1997 Mar 04 26 hue control voltage Philips Semiconductors Product specification TDA4681 BLOCK DIAGRAM Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4681 PINNING SYMBOL PIN DESCRIPTION SYMBOL PIN DESCRIPTION CPDL 16 storage capacitor for peak drive limiting FSW2 1 fast switch 2 input R2 2 red input 2 G2 3 green input 2 CL 17 storage capacitor for leakage current B2 4 blue input 2 WI 18 white level measurement input VP 5 supply voltage CI 19 cut-off measurement input 20 blue output −(B − Y) 6 colour difference input −(B − Y) BO −(R − Y) 7 colour difference input −(R − Y) CB 21 blue cut-off storage capacitor Y 8 luminance input GO 22 green output 23 green cut-off storage capacitor 24 red output GND 9 ground CG R1 10 red input 1 RO G1 11 green input 1 CR 25 red cut-off storage capacitor 26 hue control output B1 12 blue input 1 HUE FSW1 13 fast switch 1 input SDA 27 I2C-bus serial data input/output SC 14 sandcastle pulse input SCL 28 I2C-bus serial clock input BCL 15 average beam current limiting input G2 3 26 HUE B2 4 25 CR VP 5 24 RO −(B − Y) 6 23 CG −(R − Y) 7 TDA4681 22 GO Y 8 21 CB GND 9 20 BO 26 HUE 27 SDA 27 SDA 2 28 SCL R2 1 FSW2 28 SCL 2 R2 1 3 G2 FSW2 4 B2 handbook, halfpage VP 5 25 CR −(B − Y) 6 24 RO −(R − Y) 7 23 CG Y 8 22 GO TDA4681WP GND 9 21 CB 19 CI B1 12 17 CL FSW1 13 16 CPDL 15 BCL SC 14 WI 18 G1 11 CL 17 18 WI CPDL 16 G1 11 BCL 15 20 BO SC 14 R1 10 FSW1 13 19 CI B1 12 R1 10 MED705 MED704 Fig.2 Pin configuration (DIP-version). 1997 Mar 04 Fig.3 Pin configuration (PLCC-version). 5 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4681 I2C-BUS PROTOCOL I2C-BUS RECEIVER (MICROCONTROLLER WRITE MODE) Control Each transmission to/from the I2C-bus transceiver consists of at least three bytes following the START bit. Each byte is acknowledged by an acknowledge bit immediately following each byte. The first byte is the Module Address (MAD) byte, also called the slave address byte. This consists of the module address, 1000100 for the TDA4681, plus the R/W bit (see Fig.4). When the TDA4681 is a slave receiver (R/W = 0) the module address byte is 10001000 (88H). When the TDA4681 is a slave transmitter (R/W = 1) the module address byte is 10001001 (89H). The I2C-bus transmitter/receiver provides the data bytes to select and adjust the following functions and parameters: • Brightness adjust • Saturation adjust • Contrast adjust • Hue control voltage • RGB gain adjust • RGB reference voltage levels • Peak drive limiting The length of a data transmission is unrestricted, but the module address and the correct subaddress must be transmitted before the data byte(s). The order of data transmission is shown in Figs 5 and 6. Without auto-increment (BREN = 0 or 1) the module address (MAD) byte is followed by a SubAddress (SAD) byte and one data byte only (see Fig.5). • Selection of the vertical blanking interval and measurement lines for cut-off and white level control according to transmission standard • Selects either 3-level or 2-level (5 V) sandcastle pulse • Enables/disables input clamping pulse delay • Enables/disables white level control • Enables cut-off control; enables output clamping • Enables/disables full screen white level • Enables/disables full screen black level • Selects either PAL/SECAM or NTSC matrix • Enables saturation adjust; enables nominal saturation • Enables/disables synchronization of the execution of I2C-bus commands with the vertical blanking interval • Reads the result of the comparison of the nominal and actual RGB signal levels for automatic white level control. I2C-bus transmitter/receiver and data transfer I2C-BUS SPECIFICATION The I2C-bus is a bidirectional, two-wire, serial data bus for intercommunication between ICs in a system. The microcontroller transmits/receives data from the I2C-bus transceiver in the TDA4681 over the serial data line SDA (pin 27) synchronized by the serial clock line SCL (pin 28). Both lines are normally connected to a positive voltage supply through pull-up resistors. Data is transferred when the SCL line is LOW. When SCL is HIGH the serial data line SDA must be stable. A HIGH-to-LOW transition of the SDA line when SCL is HIGH is defined as a START bit. A LOW-to-HIGH transition of the SDA line when SCL is HIGH is defined as a STOP bit. Each transmission must start with a START bit and end with a STOP bit. The bus is busy after a START bit and is only free again after a STOP bit has been transmitted. 1997 Mar 04 6 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control handbook, full pagewidth TDA4681 MSB 1 LSB 0 0 0 1 0 0 module address X ACK R/W MED696 Fig.4 The module address byte. handbook, full pagewidth STA MAD SAD STO MED697 START condition data byte STOP condition Fig.5 Data transmission without auto-increment (BREN = 0 or 1). handbook, full pagewidth STA MAD SAD STO MED698 START condition STOP condition data byte data bytes Fig.6 Data transmission with auto-increment (BREN = 0). 1997 Mar 04 7 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4681 WPEN (White Pulse Enable): AUTO-INCREMENT 0 = white measuring pulse disabled The auto-increment format enables quick slave receiver initialization by one transmission, when the I2C-bus control bit BREN = 0 (see control register bits of Table 1). If BREN = 1 auto-increment is not possible. 1 = white measuring pulse enabled. BREN (Buffer Register Enable): 0 = new data is executed as soon as it is received If the auto-increment format is selected, the MAD byte is followed by a SAD byte and by the data bytes of consecutive subaddresses (see Fig.6). 1 = data is stored in buffer registers and is transferred to the data registers during the next vertical blanking interval. All subaddresses from 00H to 0FH are automatically incremented, the subaddress counter wraps round from 0FH to 00H. Reserved subaddresses 0BH, 0EH and 0FH are treated as legal but have no effect. Subaddresses outside the range 00H and 0FH are not acknowledged by the device and neither auto-increment nor any other internal operation takes place (for versions V1 to V5 subaddresses outside the range 00H and 0FH are acknowledged but neither auto-increment nor any other internal operation takes place). The I2C-bus transceiver does not accept any new data until this data is transferred into the data registers. DELOF (Delay Off) delays the leading edge of clamping pulses: 0 = delay enabled 1 = delay disabled. SC5 (SandCastle 5 V): 0 = 3-level sandcastle pulse Subaddresses are stored in the TDA4681 to address the following parameters and functions (see Table 1): 1 = 2-level (5 V) sandcastle pulse. • Brightness adjust CONTROL REGISTER 2 • Saturation adjust FSON2 (Fast Switch 2 ON) • Contrast adjust FSDIS2 (Fast Switch 2 Disable) • Hue control voltage FSON1 (Fast Switch 1 ON) • RGB gain adjust • RGB reference voltage levels FSDIS1 (Fast Switch 1 Disable) • Peak drive limiting adjust The RGB input signals are selected by FSON2 and FSON1 or FSW2 and FSW1: • Control register functions. • FSON2 has priority over FSON1 The data bytes D7 to D0 (see Table 1) provide the data of the parameters and functions for video processing. • FSW2 has priority over FSW1 CONTROL REGISTER 1 • FSDIS1 and FSDIS2 disable FSW1 and FSW2 (see Table 3). VBWx (Vertical Blanking Window): BCOF (Black level Control Off): 0 = automatic cut-off control enabled x = 0, 1 or 2. VBWx selects the vertical blanking interval and positions the measurement lines for cut-off and white level control. 1 = automatic cut-off control disabled; RGB outputs are clamped to fixed DC levels. FSBL (Full Screen Black Level): The actual lines in the vertical blanking interval after the start of the vertical pulses selected as measurement lines for cut-off and white level control are shown in Table 2. 0 = normal mode 1 = full screen black level (cut-off measurement level during full field). The standards marked with (*) are for progressive line scan at double line frequency (2fL), i.e. approximately 31 kHz. FSWL (Full Screen White Level): 0 = normal mode NMEN (NTSC Matrix Enable): 1 = full screen white level (white measurement level during full field). 0 = PAL/SECAM matrix 1 = NTSC matrix. 1997 Mar 04 8 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control SATOF (Saturation control Off): TDA4681 2-BIT WHITE LEVEL ERROR SIGNAL (see Table 4) 0 = saturation control enabled CB1, CB0 = 2-bit white level of the blue channel. 1 = saturation control disabled, nominal saturation enabled. CG1, CG0 = 2-bit white level of the green channel. CR1, CR0 = 2-bit white level of the red channel. I2C-BUS TRANSMITTER (MICROCONTROLLER READ MODE) As an I2C-bus transmitter, R/W = 1, the TDA4681 sends a data byte from the status register to the microcontroller. The data byte consists of the following bits: PONRES, CB1, CB0, CG1, CG0, CR1, CR0 and 0, where PONRES is the most significant bit. PONRES (Power On Reset) monitors the state of TDA4681’s supply voltage: 0 = normal operation 1 = supply voltage has dropped below approximately 6.0 V (usually occurs when the TV receiver is switched on or the supply voltage was interrupted). When PONRES changes state from a logic LOW to a logic HIGH all data and function bits are set to logic LOW. Table 1 Subaddress (SAD) and data bytes; note 1 SAD (HEX) MSB D7 D6 D5 D4 D3 D2 D1 D0 Brightness 00 0 0 A05 A04 A03 A02 A01 A00 Saturation 01 0 0 A15 A14 A13 A12 A11 A10 Contrast 02 0 0 A25 A24 A23 A22 A21 A20 Hue control voltage 03 0 0 A35 A34 A33 A32 A31 A30 Red gain 04 0 0 A45 A44 A43 A42 A41 A40 Green gain 05 0 0 A55 A54 A53 A52 A51 A50 Blue gain 06 0 0 A65 A64 A63 A62 A61 A60 Red level reference 07 0 0 A75 A74 A73 A72 A71 A70 Green level reference 08 0 0 A85 A84 A83 A82 A81 A80 Blue level reference 09 0 0 A95 A94 A93 A92 A91 A90 Peak drive limit 0A 0 0 AA5 AA4 AA3 AA2 AA1 AA0 FUNCTION LSB Reserved 0B X X X X X X X X Control register 1 0C SC5 DELOF BREN WPEN NMEN VBW2 VBW1 VBW0 Control register 2 0D SATOF FSWL FSBL BCOF FSDIS2 FSON2 FSDIS1 FSON1 Reserved 0E X X X X X X X X Reserved 0F X X X X X X X X Note 1. X = don’t care. 1997 Mar 04 9 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control Table 2 TDA4681 Cut-off and white level measurement lines; notes 1 to 3 VBW2 VBW1 VBW0 R G B WHITE STANDARD 0 0 0 19 20 21 22 PAL/SECAM 0 0 1 16 17 18 19 NTSC/PAL M 0 1 0 22 23 24 25 PAL/SECAM (EB) 1 0 0 38, 39 40, 41 42, 43 44, 45 PAL*/SECAM* 1 0 1 32, 33 34, 35 36, 37 38, 39 NTSC*/PAL M* 1 1 0 44, 45 46, 47 48, 49 50, 51 PAL*/SECAM* (EB) Notes 1. The line numbers given are those of the horizontal pulse counts after the start of the vertical component of the sandcastle pulse. 2. * line frequency of approximately 31 kHz. 3. (EB) is extended blanking. Table 3 Signal input selection by the fast source switches; notes 1 to 4 I2C-BUS CONTROL BITS ANALOG SWITCH SIGNALS FSON2 FSDIS2 FSON1 FSDIS1 L L L L L L L H L L H X L H L L FSW2 (PIN 1) FSW1 (PIN 13) L L L H H X L X H X L X H X X L X H L H L H X X L H H X X X H X X X X X Notes 1. H: logic HIGH implies that the voltage >0.9 V. 2. L: logic LOW implies that the voltage <0.4 V. 3. X = don’t care. 4. ON indicates the selected input signal. 1997 Mar 04 10 INPUT SELECTED RGB2 RGB1 Y/CD ON ON ON ON ON ON ON ON ON ON ON ON Philips Semiconductors Product specification Video processor with automatic cut-off and white level control Table 4 TDA4681 2-bit white level error signals; bits CX1 and CX0 CX1 CX0 INTERPRETATION 0 0 RAR (Reset-After-Read): no new measurements since last read 1 0 actual (measured) white level less than the tolerance range 1 1 actual (measured) white level within the tolerance range 0 1 actual (measured) white level greater than the tolerance range LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VP supply voltage (pin 5) − 8.8 V Vi input voltage (pins 1 to 8, 10 to 13, 16, 21, 23 and 25) −0.1 +VP V input voltage (pins 14, 15, 18 and 19) −0.7 VP + 0.7 V input voltage (pins 27 and 28) −0.1 +8.8 V Iav average current (pins 20, 22 and 24) +4 −10 mA IM peak current (pins 20, 22 and 24) +4 −20 mA I18 input current 0 2 mA I26 output current +0.5 −8 mA Tstg storage temperature −20 +150 °C Tamb operating ambient temperature 0 70 °C Ptot total power dissipation SOT117-1 − 1.2 W SOT261-2 − 1.0 W 1997 Mar 04 11 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4681 CHARACTERISTICS All voltages are measured in test circuit of Fig.10 with respect to GND (pin 9); VP = 8.0 V; Tamb = 25 °C; nominal signal amplitudes (black-to-white) at output pins 24, 22 and 20; nominal settings of brightness, contrast, saturation and white level control; without beam current or peak drive limiting; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply (pin 5) VP supply voltage 7.2 8.0 8.8 V IP supply current − 85 110 mA notes 1 and 2 − 1.33 − V Colour difference inputs [−(B − Y): pin 6; −(R − Y): pin 7] V6(p-p) −(B − Y) input (peak-to-peak value) V7(p-p) −(R − Y) signal (peak-to-peak value) notes 1 and 2 − 1.05 − V V6,7 internal DC bias voltage at black level clamping − 3.1 − V I6,7 input current during line scan − − 0.15 µA at black level clamping 100 − − µA 10 − − MΩ R6,7 AC input resistance Luminance/sync (VBS; Y: pin 8) Vi(p-p) luminance input voltage at pin 8 (peak-to-peak value) note 2 − 0.45 − V V8(bias) internal DC bias voltage at black level clamping − 3.1 − V I8 input current during line scan − − 0.15 µA at black level clamping 100 − − µA 10 − − MΩ − 0.7 − V R8 AC input resistance RGB input 1 (R1: pin 10; G1: pin 11; B1: pin 12) Vi(p-p) input voltage at pins 10, 11 and 12 (peak-to-peak value) note 2 V10/11/12(bias) internal DC bias voltage at black level clamping − 5.4 − V I10/11/12 during line scan − − 0.15 µA at black level clamping 100 − − µA 10 − − MΩ R10/11/12 input current AC input resistance RGB input 2 (R2: pin 2, G2: pin 3, B2: pin 4) Vi(p-p) input voltage at pins 2, 3 and 4 (peak-to-peak value) note 2 − 0.7 − V V2/3/4 internal DC bias voltage at black level clamping − 5.4 − V I2/3/4 input current during line scan − − 0.15 µA at black level clamping 100 − − µA 10 − − MΩ R2/3/4 1997 Mar 04 AC input resistance 12 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control SYMBOL PARAMETER TDA4681 CONDITIONS MIN. TYP. MAX. UNIT Fast signal switch FSW1 (pin 13) to select Y, CD or R1, G1, B1 inputs (control bits: see Table 3) V13 voltage to select Y and CD − − 0.4 V voltage range to select R1, G1, B1 0.9 − 5.0 V R13 internal resistance to ground − 4.0 − kΩ ∆t difference between transit times for signal switching and signal insertion − − 10 ns Fast signal switch FSW2 (pin 1) to select Y, CD/R1, G1, B1 or R2, G2, B2 inputs (control bits: see Table 3) voltage to select Y, CD/R1, G1, B1 − − 0.4 V voltage to select R2, G2, B2 0.9 − 5.0 V R1 internal resistance to ground − 4.0 − kΩ ∆t difference between transit times for signal switching and signal insertion − − 10 ns V1 Saturation adjust [acts on internal RGB signals under I2C-bus control; subaddress 01H (bit resolution 1.5% of maximum saturation); data byte 3FH for maximum saturation, data byte 23H for nominal saturation and data byte 00H for minimum saturation] ds saturation below maximum at 23H − 5 − dB at 00H; f = 100 kHz − 50 − dB Contrast adjust [acts on internal RGB signals under I2C-bus control; subaddress 02H (bit resolution 1.5% of maximum contrast); data byte 3FH for maximum contrast, data byte 2CH for nominal contrast and data byte 00H for minimum contrast] dc contrast below maximum at 2CH − 3 − dB at 00H − 22 − dB Brightness adjust [acts on internal RGB signals under I2C-bus control; subaddress 00H (bit resolution 1.5% of brightness range); data byte 3FH for maximum brightness, data byte 27H for nominal brightness and data byte 00H for minimum brightness] dbr black level shift of nominal signal amplitude referred to cut-off measurement level at 3FH − 30 − % at 00H − −50 − % White potentiometers [under I2C-bus control; subaddresses 04H (red), 05H (green) and 06H (blue); data byte 3FH for maximum gain; data byte 22H for nominal gain and data byte 00H for minimum gain]; note 3 ∆Gv 1997 Mar 04 relative to nominal gain increase of AC gain at 3FH − 60 − % decrease of AC gain at 00H − 60 − % 13 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control SYMBOL PARAMETER TDA4681 CONDITIONS MIN. TYP. MAX. UNIT RGB outputs (pins 24, 22 and 20; positive going output signals and no peak drive limitation; subaddress 0AH = 3FH); note 4 nominal output signals (black-to-white value) − 2.0 − V maximum output signals (black-to-white value) 3.2 − − V ∆Vo spread between RGB output signals − − 10 % Vo(min) minimum output voltages − − 0.8 V Vo(max) maximum output voltages 6.8 − − V V24,22,20 voltage of cut-off measurement line 2.3 2.5 2.7 V Iint internal current sources − 5.0 − mA Ro output resistance − 65 110 Ω Vo(b-w) output clamping; BCOF = 1 Frequency response fres frequency response of Y path (from pin 8 to pins 24, 22 and 20) f = 10 MHz − − 3 dB frequency response of CD path (from pins 7 to 24 and 6 to 20) f = 8 MHz − − 3 dB frequency response of RGB1 path (from pins 10 to 24, 11 to 22 and 12 to 20) f = 10 MHz − − 3 dB frequency response of RGB2 path (from pins 2 to 24, 3 to 22 and 4 to 20) f = 10 MHz − − 3 dB for horizontal and vertical blanking pulses 2.0 2.5 3.0 V for horizontal pulses (line count) 4.0 4.5 5.0 V for burst key pulses 6.3 − VP + 0.7 V for horizontal and vertical blanking pulses 2.0 2.5 3.0 for burst key pulses 4.0 4.5 VP + 0.7 V Sandcastle pulse detector (pin 14) CONTROL BIT SC5 = 0; 3-LEVEL; notes 5 and 6 V14 sandcastle pulse voltage CONTROL BIT SC5 = 1; 2-LEVEL; note 5 V14 1997 Mar 04 sandcastle pulse voltage 14 V Philips Semiconductors Product specification Video processor with automatic cut-off and white level control SYMBOL PARAMETER TDA4681 CONDITIONS MIN. TYP. MAX. UNIT GENERAL I14 input current V14 < 0.5 V −100 − − µA td leading edge delay of the clamping pulse control bit DELOF = 0 − 1.5 − µs control bit DELOF = 1 − 0 − µs required burst key pulse time control bit DELOF = 0; normally used with fL 3 − − µs control bit DELOF = 1; normally used with 2fL 1.5 − − µs 4 − 29 − 8 − 57 − tBK npulse required horizontal or burst key pulses e.g. at interlace scan during vertical blanking interval (VBW2 = 0) e.g. at progressive line scan (VBW2 = 1) Average beam current limiting (pin 15); note 7 Vc(15) contrast reduction starting voltage − 4.0 − V ∆Vc(15) voltage difference for full contrast reduction − −2.0 − V Vbr(15) brightness reduction starting voltage − 2.5 − V ∆Vbr(15) voltage difference for full brightness reduction − −1.6 − V Peak drive limiting voltage [pin 16; internal peak drive limiting level (Vpdl) acts on RGB outputs under I2C-bus control; subaddress 0AH]; note 8 V20,22,24 I16 RGB output voltages at 00H − − 3.0 V at 3FH 6.5 − − V − −1 − µA charge current − 5 − mA V16 internal voltage limitation 4.5 − − V Vc(16) contrast reduction starting voltage − 4.0 − V ∆Vc(16) voltage difference for full contrast reduction − −2.0 − V Vbr(16) brightness reduction starting voltage − 2.5 − V ∆Vbr(16) voltage difference for full brightness reduction − −1.6 − V discharge current 1997 Mar 04 during peak white 15 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control SYMBOL PARAMETER TDA4681 CONDITIONS MIN. TYP. MAX. UNIT Automatic cut-off and white level control (pins 19 and 18); notes 9 to 11; see Fig.8 V19 permissible voltage (also during scanning period) − − VP − 1.4 V I19 output current − − −140 µA input current 150 − − µA 0.5 − additional input current only during warming up − V24,22,20 warming up amplitude (under I2C-bus control; subaddress 0AH) switch-on delay 1 − Vpdl − 0.7 − V V19(th) voltage threshold for picture tube cathode warming up switch-on delay 1 − 5.0 − V Vref internally controlled voltage during leakage measurement period − 3.0 − V mA DATA BYTE 07H FOR RED REFERENCE LEVEL, DATA BYTE 08H FOR GREEN REFERENCE LEVEL AND DATA BYTE 09H FOR BLUE REFERENCE LEVEL ∆V19 difference between VMEAS (cut-off or 3FH (maximum VMEAS) 1.5 white level measurement voltage) and 20H (nominal VMEAS) − Vref 00H (minimum VMEAS) − − − V 1.0 − V − 0.5 V I18 input current white level measurement − − 800 µA R18 internal resistance to Vref; I18 ≤ 800 µA − 100 − Ω ∆V19 white level register (measured value within tolerance range) white level measurement − 250 − mV Storage of cut-off control voltage/output clamping voltage (pins 25, 23 and 21) I21,23,25 charge and discharge currents during cut-off measurement lines − 0.3 − mA input currents of storage inputs outside measurement time − − 0.1 µA charge and discharge currents during leakage measurement period − 0.4 − mA leakage current outside time LM − − 0.1 µA − − 3.0 V Storage of leakage information (pin 17) I17 V17 voltage for reset to switch-on below I2C-bus control; subaddress 03H; data byte 3FH for maximum voltage; data byte 20H for Hue control (under nominal voltage and data byte 00H for minimum voltage); note 12 V26 output voltage at 3FH 4.8 − − V at 20H − 3.0 − V at 00H Iint 1997 Mar 04 current of the internal current source at pin 26 16 − − 1.0 V 500 − − µA Philips Semiconductors Product specification Video processor with automatic cut-off and white level control SYMBOL PARAMETER TDA4681 CONDITIONS MIN. TYP. MAX. UNIT I2C-bus transceiver clock SCL (pin 28) fSCL input frequency range 0 − 100 kHz VIL LOW level input voltage − − 1.5 V VIH HIGH level input voltage 3.0 − 6.0 V IIL LOW level input current −10 − − µA IIH HIGH level input current − − 10 µA tL clock pulse LOW 4.7 − − µs tH clock pulse HIGH 4.0 − − µs tr rise time − − 1.0 µs tf fall time − − 0.3 µs − − 1.5 V V28 = 0.4 V I2C-bus transceiver data input/output SDA (pin 27) VIL LOW level input voltage VIH HIGH level input voltage IIL LOW level input current IIH HIGH level input current V27 = 0.4 V 3.0 − 6.0 V −10 − − µA − − 10 µA IOL LOW level output current 3.0 − − mA tr rise time − − 1.0 µs tf fall time − − 0.3 µs tSU;DAT data set-up time 0.25 − − µs V27 = 0.4 V Notes to the characteristics 1. The values of the −(B − Y) and −(R − Y) colour difference input signals are for a 75% colour-bar signal. 2. The pins are capacitively coupled to a low ohmic source, with a recommended maximum output impedance of 600 Ω. 3. The white potentiometers affect the amplitudes of the RGB output signals including the white measurement pulses. 4. The RGB outputs at pins 24, 22 and 20 are emitter followers with current sources. 5. Sandcastle pulses are compared with internal threshold voltages independent of VP. The threshold voltages separate the components of the sandcastle pulse. The particular component is generated when the voltage on pin 14 exceeds the defined internal threshold voltage. The internal threshold voltages (control bit SC5 = 0) are: 1.5 V for horizontal and vertical blanking pulses 3.5 V for horizontal pulses 6.0 V for the burst key pulse. The internal threshold voltages (control bit SC5 = 1) are: 1.5 V for horizontal and vertical blanking pulses 3.5 V for the burst key pulse. 6. A sandcastle pulse with a maximum voltage equal to (VP + 0.7 V) is obtained by limiting a 12 V sandcastle pulse. 7. Average beam current limiting reduces the contrast, at minimum contrast it reduces the brightness. 8. Peak drive limiting reduces the RGB outputs by reducing the contrast, at minimum contrast it reduces the brightness. The maximum RGB outputs are determined via the I2C-bus under subaddress 0AH. When an RGB output exceeds the maximum voltage, peak drive limiting is delayed by one horizontal line. 1997 Mar 04 17 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4681 9. The vertical blanking interval is defined by a vertical pulse which contains 4 (8) or more horizontal pulses; it begins with the start of the vertical pulse and ends with the end of the white measuring line. If the vertical pulse is longer than the selected vertical blanking window the blanking period ends with the end of the complete line after the end of the vertical pulse. The counter cycle time is 31 (63) horizontal pulses. If the vertical pulse contains more than 29 (57) horizontal pulses, the black level storage capacitors will be discharged while all signals are blanked. During leakage current measurement, the RGB channels are blanked to ultra-black level. During cut-off measurement one channel is set to the measurement pulse level, the other channels are blanked to ultra-black. Since the brightness adjust shifts the colour signal relative to the black level, the brightness adjust is disabled during the vertical blanking interval (see Figs 7 and 8). 10. During picture cathode warming up (first switch-on delay) the RGB outputs (pins 24, 22 and 20) are blanked to the ultra-black level during line scan. During the vertical blanking interval a white-level monitor pulse is fed out on the RGB outputs and the cathode currents are measured. When the voltage threshold on pin 19 is greater than 5.0 V, the monitor pulse is switched off and cut-off and white level control are activated (second switch-on delay). As soon as cut-off control stabilizes, RGB output blanking is removed. 11. Range of cut-off measurement level at the RGB outputs is 1 to 5 V. The recommended value is 3 V. 12. The hue control output at pin 26 is an emitter follower with current source. Table 5 Demodulator axes and amplification factors PARAMETER NTSC PAL (B − Y)* demodulator axis 0° 0° (R − Y)* demodulator axis 95° 90° (R − Y)* amplification factor 1.59 1.14 (B − Y)* amplification factor 2.03 2.03 Table 6 PAL/SECAM and NTSC matrix; notes 1 and 2 MATRIX NMEN PAL/SECAM 0 NTSC 1 Notes 1. PAL/SECAM signals are matrixed by the equation: VG − Y = −0.51VR − Y − 0.19VB − Y NTSC signals are matrixed by the equations (hue phase shift of −5 degrees): VR − Y* = 1.39VR − Y − 0.07VB − Y; VG − Y* = −0.46VR − Y − 0.15VB − Y; VB − Y* = VB − Y In the matrix equations: VR − Y and VB − Y are conventional PAL demodulation axes and amplitudes at the output of the NTSC demodulator. VG − Y*, VR − Y* and VB − Y* are the NTSC modified colour difference signals; this is equivalent to the demodulator axes and amplification factors shown in Table 5. VG − Y* = −0.33VR − Y* − 0.17VB − Y*. 2. The vertical blanking interval is selected via the I2C-bus (see Table 2 and Fig.8). Vertical blanking is determined by the vertical component of the sandcastle pulse; this vertical component has priority when it is longer than the vertical blanking interval of the transmission standard. 1997 Mar 04 18 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4681 handbook, full pagewidth MED701 (1) white measurement level for green signal (2) cut-off measurement level for green signal ultra-black level (1) Maximum brightness. (2) Nominal brightness. Fig.7 Cut-off and white level measurement pulses. 621 622 623 624 625 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vertical flyback 850 µs V component of the sandcastle pulse PAL, SECAM LM (leakage current measurement time) vertical blanking interval, 22 complete lines MR MG MB WR WG WB V component of the sandcastle pulse LM NTSC, PAL M vertical blanking interval, 19 complete lines MR MG MB WR WG WB cut-off and white level measurement pulses V component of the sandcastle pulse LM vertical blanking interval, 25 complete lines dbook, full pagewidth PAL, SECAM (with increased vertical blanking interval) MR MG MB WR WG WB Fig.8 Leakage current, cut-off and white level current measurement timing diagram. 1997 Mar 04 19 MED702 1997 Mar 04 1 28 CL 20 CL + 3 26 ESD protection diode on all pins except pins 5, 9, 27 and 28 2 27 CL 4 25 MR 5 CL zener diode protection for pins 27 and 28 (version V6) + 24 6 23 handbook, full pagewidth 7 CL 8 21 MB 20 9 TDA4681 Fig.9 Internal circuits. CL MG 22 CL 10 19 CL HE 11 reference WM 18 CL LM 12 17 13 16 14 MED706 15 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4681 INTERNAL PIN CONFIGURATION 1997 Mar 04 21 75 Ω 4.7 kΩ 75 Ω 220 µF 22 µH 75 Ω 75 Ω 75 Ω 75 Ω 1N4148 75 Ω 75 Ω −(R − Y) Y 10 nF 47 nF B1 10 nF 14 13 12 11 BR1(1) 1N4148 1N4148 SC 22 23 24 25 26 27 28 15 16 17 18 19 20 21 TDA4681 10 9 8 7 6 5 4 3 2 1 10 kΩ BCL 22 µF 1 µF CPDL 2.2 kΩ(2) 330 nF 1 nF 220 nF 220 nF 220 nF CL WI CI Bo CB Go CG Ro CR HUE SDA 100 Ω SCL 100 Ω Fig.10 Test and application circuit. 3.9 kΩ 3.9 kΩ 1N4148 G1 10 nF FSW1 R1 10 nF GND −(B − Y) 10 nF B2 10 nF VP G2 10 nF 10 nF R2 10 nF FSW2 82 kΩ SCL SDA hue BZX79 C6V2 10 9 8 7 6 5 4 3 2 1 MED707 CON2 CI Bo Go Ro GND +12 V 200 V Video processor with automatic cut-off and white level control (1) Insert link BR1 if average beam current is not required. (2) Value depends on video output current stages and picture tube. beam current VP = 8 V SC FSW1 B1 G1 R1 Y −(R − Y) −(B − Y) B2 G2 R2 FSW2 handbook, full pagewidth Philips Semiconductors Product specification TDA4681 TEST AND APPLICATION INFORMATION Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4681 PACKAGE OUTLINES seating plane handbook, full pagewidthdual in-line package; 28 leads (600 mil) DIP28: plastic SOT117-1 ME D A2 L A A1 c e Z w M b1 (e 1) b MH 15 28 pin 1 index E 1 14 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.1 0.51 4.0 1.7 1.3 0.53 0.38 0.32 0.23 36.0 35.0 14.1 13.7 2.54 15.24 3.9 3.4 15.80 15.24 17.15 15.90 0.25 1.7 inches 0.20 0.020 0.16 0.066 0.051 0.020 0.014 0.013 0.009 1.41 1.34 0.56 0.54 0.10 0.60 0.15 0.13 0.62 0.60 0.68 0.63 0.01 0.067 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT117-1 051G05 MO-015AH 1997 Mar 04 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-14 22 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4681 PLCC28: plastic leaded chip carrier; 28 leads SOT261-2 eE eE y X A 19 25 18 26 bp b1 ZE w M 28 1 E HE pin 1 index e A A4 A1 12 4 β k1 (A 3) k 5 11 Lp v M A ZD e detail X D B HD v M B 0 5 10 mm scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) k1 max. Lp v w y 0.51 1.44 1.02 0.18 0.18 0.10 Z D(1) Z E (1) max. max. UNIT A A1 min. A3 A4 max. bp b1 mm 4.57 4.19 0.51 0.25 3.05 0.53 0.33 0.81 0.66 0.180 0.020 0.01 0.165 0.12 0.430 0.430 0.495 0.495 0.048 0.057 0.021 0.032 0.456 0.456 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.390 0.390 0.485 0.485 0.042 0.040 0.013 0.026 0.450 0.450 inches D (1) E (1) e eD eE HD HE k 11.58 11.58 10.92 10.92 12.57 12.57 1.22 1.27 11.43 11.43 9.91 9.91 12.32 12.32 1.07 2.16 β 2.16 45 o Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-25 SOT261-2 1997 Mar 04 EUROPEAN PROJECTION 23 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4681 Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). WAVE SOLDERING DIP Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. • The package footprint must incorporate solder thieves at the downstream corners. • The longitudinal axis of the package footprint must be parallel to the solder flow. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. REPAIRING SOLDERED JOINTS Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. PLCC REPAIRING SOLDERED JOINTS REFLOW SOLDERING Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). 1997 Mar 04 24 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control TDA4681 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Mar 04 25 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control NOTES 1997 Mar 04 26 TDA4681 Philips Semiconductors Product specification Video processor with automatic cut-off and white level control NOTES 1997 Mar 04 27 TDA4681 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547047/1200/01/pp28 Date of release: 1997 Mar 04 Document order number: 9397 750 01398