INTEGRATED CIRCUITS DATA SHEET TDA4672 Picture Signal Improvement (PSI) circuit with enhanced peaking function Product specification Supersedes data of August 1993 File under Integrated Circuits, IC02 1996 Dec 11 Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function TDA4672 FEATURES • Luminance signal delay from 20 ns to 1100 ns (minimum step 45 ns) • Selectable luminance signal peaking with symmetrical overshoots • Selectable 2.6 or 5 MHz peaking centre frequency and degree of peaking from −6 dB to +9 dB in 16 steps of 1 dB each GENERAL DESCRIPTION The TDA4672 delays the luminance signal. The luminance signal can also be improved by peaking and noise reduction (coring). • Selectable noise reduction by coring • Selectable 5 or 12 V sandcastle input voltage • All controls selected via the I2C-bus • Timing pulse generation for clamping and delay time control synchronized by sandcastle pulse • Automatic luminance signal delay correction using a control loop • Luminance input signal clamping with coupling capacitor • 4.5 to +8.8 V supply voltage • Minimum of external components. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. VP supply voltage (pin 1) 4.5 5 IP(tot) total supply current 26 td(Y) Y signal delay time 20 Vi(Y)(p-p) composite Y input signal (peak-to-peak value, pin 16) GY Tamb MAX. UNIT 8.8 V 37 46 mA − 1130 ns − 450 640 mV voltage gain of Y channel − −1 − dB operating ambient temperature 0 − 70 °C ORDERING INFORMATION TYPE NUMBER TDA4672 1996 Dec 11 PACKAGE NAME DIP18 DESCRIPTION plastic dual in-line package; 18 leads (300 mil) 2 VERSION SOT102-1 1996 Dec 11 3 100 nF 100 nF 100 nF −(B − Y) −(R − Y) Y 7 3 14 13 16 17 Vref BK, H + V 450 ns Vref 180 ns BLACK LEVEL CLAMP BK SANDCASTLE PULSE DETECTOR BLACK LEVEL CLAMP 180 ns DELAY TIME CONTROL Vref I2C-BUS 2 90 ns Y delay 100 nF 8 90 ns CTI on/off 5 18 n.c. BLACK LEVEL CLAMP 2.6 MHz 5 MHz 2.6 MHz 5 MHz peaking frequency 100 ns 90 ns coring on/off TDA4672 +1 −0.5 −0.5 + I2C-BUS + Y 100 nF 6 −(B − Y) 4 −(R − Y) 12 11 MED756 I2C-BUS PEAKING CORING Vref 100 nF 15 Vref GENERATION CORING degree of peaking 1 VP = 5 to 8 V Picture Signal Improvement (PSI) circuit with enhanced peaking function Fig.1 Block diagram. 45 ns control signal 100 ns sandcastle 5 V/12 V VREF 10 SCL I2C-BUS RECEIVER 9 SDA handbook, full pagewidth sandcastle pulse Philips Semiconductors Product specification TDA4672 BLOCK DIAGRAM Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function TDA4672 PINNING SYMBOL PIN DESCRIPTION VP 1 positive supply voltage CDL 2 capacitor of delay time control Vi(R − Y) 3 ±(R − Y) colour-difference input signal; note 1 Vo(R − Y) 4 ±(R − Y) colour-difference output signal; note 1 n.c. 5 not connected Vo(B − Y) 6 ±(B − Y) colour-difference output signal; note 2 Vi(B − Y) 7 ±(B − Y) colour-difference input signal; note 2 GND2 8 ground 2 (0 V) SDA 9 I2C-bus serial data input/output SCL 10 I2C-bus serial clock input CCOR 11 coring capacitor VoY 12 delayed luminance output signal CCLP1 13 black level clamping capacitor 1 CCLP2 14 black level clamping capacitor 2 Cref 15 capacitor of reference voltage ViY 16 luminance input signal SAND 17 sandcastle pulse input GND1 18 ground 1 (0 V) handbook, halfpage 1 18 GND1 CDL 2 17 SAND Vi(R − Y) 3 16 ViY Vo(R − Y) 4 15 Cref n.c. 5 TDA4672 14 CCLP2 13 CCLP1 Vo(B − Y) 6 Vi(B − Y) 7 12 VoY GND2 8 11 CCOR SDA 9 10 SCL MED757 Fig.2 Pin configuration. Notes 1. Pin 3 is connected directly to pin 4. 2. Pin 7 is connected directly to pin 6. 1996 Dec 11 VP 4 Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function The peaking section uses a transversal filter circuit with selectable centre frequencies of 2.6 and 5.0 MHz. FUNCTIONAL DESCRIPTION The TDA4672 contains luminance signal processing. The luminance signal section comprises a variable, integrated luminance delay line with luminance signal peaking and noise reduction by coring. It provides selectable degrees of peaking from −6 to +9 dB and noise reduction by coring, which attenuates the high-frequency noise introduced by peaking. The output buffer stage ensures a low-ohmic Video Blanking Synchronization (VBS) output signal on pin 12 (<160 Ω). The gain of the luminance signal path from pin 16 to pin 12 is unity. All functions and parameters are controlled via the I2C-bus. Y-signal path An oscillation signal of the delay time control loop is present on output pin 12 instead of the VBS signal. It is present during the vertical blanking interval of the burst key pulses in lines 16 (330) to 18 (332). This sync should not be applied for synchronization. The video and blanking signal is AC-coupled to the input pin 16. Its black porch is clamped to a DC reference voltage to ensure the correct operating range of the luminance delay stage. The luminance delay line consists of all-pass filter sections with delay times of 45, 90, 100, 180 and 450 ns (see Fig.1). The luminance signal delay is controlled via the I2C-bus in steps of 45 ns in the range of 20 to 1100 ns, this ensures that the maximum delay difference between the luminance and colour-difference signals is ±22.5 ns. Colour-difference signal paths The colour-difference input signals (on pins 3 and 7) are connected directly to the output pins. This is for compatibility with other Philips Semiconductors PSI-circuits. An automatic luminance delay time adjustment in an internal control loop (with the horizontal frequency as a reference) is used to correct changes in the delay time, due to component tolerances. The control loop is automatically enabled between the burst key pulses of lines 16 (330) and 17 (331) during the vertical blanking interval. The control voltage is stored in the capacitor CDL connected to pin 2. 1996 Dec 11 TDA4672 5 Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function TDA4672 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). GND1 and GND2 are connected together. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VP supply voltage (pin 1) 0 8.8 V VI input voltage (pins 2 to 7 and pins 11 to 16) −0.1 VP V V9,10 input voltage at pins 9 and 10 −0.1 +8.8 V V17 input voltage at pin 17 −0.1 +12 V I8-18 current between pins 8 and 18 − ±20 mA I3-4 current between pins 3 and 4 − ±4 mA I6-7 current between pins 6 and 7 − ±4 mA Ptot total power dissipation 0 0.97 W Tstg storage temperature −25 +150 °C Tamb operating ambient temperature 0 70 °C VESD electrostatic handling − +250 V − −500 V − ±500 V note 1 for pin 17 for other pins Note 1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER VALUE UNIT 82 K/W thermal resistance from junction to ambient in free air CHARACTERISTICS VP = 5 V; nominal video amplitude VVB = 315 mV; tH = 64 µs; tBK = 4 µs (burst key); Tamb = 25 °C and measurements taken in Fig.4; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VP supply voltage (pin 1) 4.5 5 8.8 V IP(tot) total supply current 26 37 46 mA Vi(Y)(p-p) VBS input signal on pin 16 (peak-to-peak value) − 450 640 mV V16 black level clamping voltage I16 input current Y-signal path − 3.1 − V during clamping ±95 − ±190 µA outside clamping − − ±0.1 µA R16 input resistance C16 input capacitance td(Y)(max) maximum Y delay time set via I2C-bus minimum Y delay time I2C-bus td(Y)(min) 1996 Dec 11 outside clamping set via 6 5 − − MΩ − 3 10 pF 1070 1100 1130 ns − 20 − ns Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function SYMBOL ∆td(Y) PARAMETER TDA4672 CONDITIONS I2C-bus minimum delay step set via group delay time difference f = 0.5 to 5 MHz; maximum delay MIN. TYP. MAX. UNIT 40 45 50 ns − 0 ±25 ns 185 215 245 ns td(peak) minimum delay time for peaking GY VBS signal gain measured on output pin 12 (composite signal, peak-to-peak value) V12/V16; f = 500 kHz; maximum delay −2 −1 0 dB I12 output current (emitter-follower with constant current source) source current −1 − − mA sink current 0.4 − − mA − − 160 Ω f = 0.5 to 3 MHz −2 −1 0 dB f = 0.5 to 5 MHz −4 −3 −1 dB R12 output resistance f frequency response for LIN signal linearity for maximum delay αmin/αmax; note 1 video contents of 315 mV (p-p) VVBS = 450 mV (p-p) 0.85 − − − video contents of 450 mV (p-p) VVBS = 640 mV (p-p) 0.60 − − − fC1; LCF-bit = 0 4.5 5 5.5 MHz fC2; LCF-bit = 1 2.3 2.6 2.9 MHz from − −6 − dB to − +9 − dB each step − 1 − dB − − − % Luminance peaking, selected via I2C-bus fpeak Vpeak peaking frequency peaking amplitude for grade of peaking (fC amplitude over 0.5 MHz amplitude) Y delay = 215 ns; peaking delay only selectable values no limitation of peaking Vn(rms) noise voltage on pin 12 (RMS value) without peaking; f = 0 to 5 MHz − − 1 mV COR coring of peaking (coring part referred to 315 mV) COR-bit = 1 − 20 − % 1996 Dec 11 7 Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function SYMBOL PARAMETER TDA4672 CONDITIONS MIN. TYP. MAX. UNIT Sandcastle pulse, input voltage selectable via I2C-bus V17 R17 input voltage threshold for H and V sync SC5-bit = 0 (+12 V) 1.1 1.5 1.9 V input voltage threshold for burst SC5-bit = 0 (+12 V) 5.5 6.5 7.5 V input voltage threshold for H and V sync SC5-bit = 1 (+5 V) 1.1 1.5 1.9 V input voltage threshold for burst SC5-bit = 1 (+5 V) 3.0 3.5 4.0 V input resistance +12 V input level 30 40 50 kΩ +5 V input level 15 20 25 kΩ − 4 8 pF C17 input capacitance tBK burst key pulse width 3.0 4.0 4.6 µs td leading edge delay for clamping pulse referenced to tBK − 1 − µs np number of required burst key pulses vertical blanking interval note 2 4 − 31 − I2C-bus control, SDA and SCL VIH HIGH level input voltage on pins 9 and 10 3 − 5 V VIL LOW level input voltage on pins 9 and 10 0 − 1.5 V I9,10 input current on pins 9 and 10 − − ±10 µA Vo(ACK) output voltage at acknowledge on Io(ACK) = 3 mA pin 9 − − 0.4 V Io(ACK) output current at acknowledge on sink current pin 9 3 − − mA Notes 1. αmin: minimum differential voltage gain of the luminance video signal; αmax: maximum differential voltage gain of the luminance video signal. 2. A number of more than 31 burst key pulses repeats the counter cycle of delay time control. 1996 Dec 11 8 Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function TDA4672 I2C-BUS FORMAT S(1) SLAVE ADDRESS(2) ACK(3) SUBADDRESS(4) ACK(3) DATA(5) P(6) Notes 1. S = START condition. 2. SLAVE ADDRESS = 1000 100X. 3. ACK = acknowledge, generated by the slave. 4. SUBADDRESS = subaddress byte, see Table 1. 5. DATA = data byte, see Table 1. 6. P = STOP condition. 7. X = read/write control bit. X = 0, order to write (the circuit is slave receiver). X = 1, order to read (the circuit is slave transmitter). If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed. I2C-bus transmission; see Table 2 Table 1 DATA FUNCTION SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 DL3 DL2 DL1 DL0 Y delay/SC 00010000 0 SC5 0 DL4 Peaking and coring 00010001 COR PEAK LCF 0 Table 2 PCON3 PCON2 PCON1 PCON0 Function of the bits DATA LOGIC 1 LOGIC 0 45 ns 0 ns DL1 90 ns 0 ns DL2 180 ns 0 ns DL3 180 ns 0 ns DL4 450 ns 0 ns DL0 FUNCTION set delay in luminance channel SC5 select sandcastle pulse voltage +5 V +12 V LCF set peaking frequency response 2.6 MHz 5.0 MHz PEAK set peaking delay active (190 ns) inactive COR set coring control active inactive PCONx set peaking amplification 1996 Dec 11 see Table 3 9 Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function Table 3 TDA4672 Peaking amplification PCON3 PCON2 PCON1 PCON0 GRADE OF PEAKING (dB) 1 1 1 1 −6 1 1 1 0 −5 1 1 0 1 −4 1 1 0 0 −3 1 0 1 1 −2 1 0 1 0 −1 1 0 0 1 0 1 0 0 0 +1 0 1 1 1 +2 0 1 1 0 +3 0 1 0 1 +4 0 1 0 0 +5 0 0 1 1 +6 0 0 1 0 +7 0 0 0 1 +8 0 0 0 0 +9 Remarks to the subaddress bytes Subaddresses 00H to 0FH are reserved for colour decoders and RGB processors. Subaddresses 10 and 11 only are acknowledged. General call address is not acknowledged. Power-on reset: D7 to D1 bits of data bytes are set to logic 0, D0 bit is set to logic 1. 1996 Dec 11 10 1996 Dec 11 11 VP GND 1 18 3 CD input CDL + + CD output 4 7 CD input CD output + 6 Fig.3 Internal circuit. n.c. 5 14 15 TDA4672 CCLP2 Cref + GND 8 13 CCLP1 + + + SDA 9 10 MED759 + 11 12 SCL CCOR Y output Picture Signal Improvement (PSI) circuit with enhanced peaking function 2 all input and output pins except pins 9, 10 and 17 16 + Y input 17 handbook, full pagewidth SC Philips Semiconductors Product specification TDA4672 INTERNAL CIRCUITRY Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function TDA4672 TEST AND APPLICATION INFORMATION handbook, full pagewidth SDA I2C-bus SCL CCOR 0.1 µF (VBS) VoY CCLP1 0.1 µF CCLP2 SDA 10 9 11 8 12 7 13 6 GND2 Vi(B − Y) 14 TDA4672 5 Vo(B − Y) n.c. 0.1 µF Cref 15 4 16 3 17 2 0.1 µF (VBS) sandcastle pulse input ViY 0.1 µF SAND GND1 1 18 Vo(R − Y) Vi(R − Y) CDL VP 0.1 µF +5 V 47 µF 15 Ω MED758 VB Fig.4 Test and application circuit. 1996 Dec 11 12 Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function TDA4672 PACKAGE OUTLINE DIP18: plastic dual in-line package; 18 leads (300 mil) SOT102-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 10 18 pin 1 index E 1 9 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.7 1.40 1.14 0.53 0.38 1.40 1.14 0.32 0.23 21.8 21.4 6.48 6.20 2.54 7.62 3.9 3.4 8.25 7.80 9.5 8.3 0.254 0.85 inches 0.19 0.020 0.15 0.055 0.044 0.021 0.015 0.055 0.044 0.013 0.009 0.86 0.84 0.26 0.24 0.10 0.30 0.15 0.13 0.32 0.31 0.37 0.33 0.01 0.033 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 93-10-14 95-01-23 SOT102-1 1996 Dec 11 EUROPEAN PROJECTION 13 Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function TDA4672 with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1996 Dec 11 14 Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function NOTES 1996 Dec 11 15 TDA4672 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1200/03/pp16 Date of release: 1996 Dec 11 Document order number: 9397 750 01473