74HC423; 74HCT423 Dual retriggerable monostable multivibrator with reset Rev. 03 — 24 July 2008 Product data sheet 1. General description 74HC423; 74HCT423 are high-speed Si-gate CMOS devices that are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC423; 74HCT423 dual retriggerable monostable multivibrator with reset has two methods of output pulse width control. 1. The minimum pulse width is essentially determined by the selection of an external resistor (REXT) and capacitor (CEXT), see Section 12.1. 2. Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired. When nRD is LOW, it forces the nQ output LOW, the nQ output HIGH and also inhibits the triggering. Figure 10 and Figure 11 illustrate pulse control by reset. The nA and nB inputs’ Schmitt trigger action makes them highly tolerant to slower input rise and fall times. The 74HC423; 74HCT423 are identical to the 74HC123; 74HCT123 except that they cannot be triggered via the reset input. 2. Features n n n n n n DC triggered from active HIGH or active LOW inputs Retriggerable for very long pulses up to 100% duty factor Direct reset terminates output pulse Schmitt-trigger action on all inputs except for the reset input Complies with JEDEC standard no. 7A ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Specified from −40 °C to +85 °C and from −40 °C to +125 °C 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 −40 °C to +125 °C 74HCT423BQ DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1 quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm 74HCT423DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HCT423PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HC423N 74HCT423N 74HC423D 74HCT423D 74HC423BQ 4. Functional diagram 14 15 S 13 Q 1A 1B 1RD 4 Q 2 1Q RD 6 3 5 Q 2RD 1Q T S 2B 1REXT/CEXT 1 7 2A 1CEXT 2CEXT 2REXT/CEXT 2Q 9 T 12 Q 10 2Q RD 11 001aah796 Fig 1. Functional Diagram 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 2 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset 14 15 CX RCX 1 1CEXT 14 2CEXT S Q 1 1A Q 2 1B 10 2B 1Q 13 2Q 5 RD 1Q 6 7 Fig 2. CX RCX 9 4 5 & 10 2Q 12 11 3 1RD 11 2RD R 7 T 9 2A 4 6 3 2REXT/CEXT & 2 1REXT/CEXT 15 13 12 R 001aah797 001aah798 Logic symbol Fig 3. IEC Logic symbol REXT/CEXT VCC Q RD Q R CL CL VCC VCC R CL 001aah799 CL A CL B Fig 4. Logic diagram 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 3 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset 5. Pinning information 5.1 Pinning 1 1A terminal 1 index area 74HC423 74HCT423 16 VCC 74HC423 74HCT423 4 13 1Q 2 15 1REXT/CEXT 1RD 3 14 1CEXT 1Q 4 13 1Q 2Q 5 12 2Q 2CEXT 6 11 2RD 9 14 1CEXT 1Q 1B 8 15 1REXT/CEXT 3 16 VCC 2REXT/CEXT 7 10 2B 2A 2 1 GND 8 9 GND 1B 1RD 1A 2Q 5 2CEXT 6 2REXT/CEXT 7 2A 12 2Q VCC (1) 11 2RD 10 2B 001aah784 Transparent top view 001aah785 (1) The die substrate is attached to this pad using a conductive die attach material. It cannot be used as supply pin or input Fig 5. Pin configuration DIP16, SO16 and (T)SSOP16 Fig 6. Pin configuration DHVQFN16 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 2A 1, 9 trigger input (negative edge triggered) 1B, 2B 2, 10 trigger input (positive edge triggered) 1RD, 2RD 3, 11 direct reset (active LOW) 1Q, 2Q 4, 12 output (active LOW) GND 8 ground (0 V) 1Q, 2Q 13, 5 output (active HIGH) 1CEXT, 2CEXT 14, 6 external capacitor connection 1REXT/CEXT, 2REXT/CEXT 15, 7 external resistor/capacitor connection VCC 16 supply voltage 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 4 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset 6. Functional description Function table[1] Table 3. Input Output nRD nA nB nQ nQ L X X L H H[2] H[2] X H X L[2] X X L L[2] H L ↑ H ↓ H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition; = one HIGH level output pulse; = one LOW level output pulse. [2] If the monostable multivibrator was triggered before this condition was established, the pulse will continue as programmed. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +7 V IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] - ±20 mA IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] - ±20 mA IO output current −0.5 V < VO < VCC + 0.5 V - ±25 mA ICC supply current - 50 mA IGND ground current −50 - mA Tstg storage temperature total power dissipation Ptot −65 +150 °C DIP16 package [2] - 750 mW SO16, SSOP16, TSSOP16 and DHVQFN16 packages [3] - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP16 packages: above 70 °C the value of Ptot derates linearly at 12 mW/K. [3] For SO16 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K; For SSOP16 and TSSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K; For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K. 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 5 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC423 Min Typ 74HCT423 Max Min Typ 6.0 Unit Max VCC supply voltage 2.0 5.0 4.5 5.0 VI input voltage 0 - VCC 0 - VCC 5.5 V V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature −40 - +125 −40 - ∆t/∆V input transition rise and fall rate °C +125 VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V 74HC423 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = −4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V VI = VIH or VIL IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 74HC_HCT423_3 Product data sheet µA © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 6 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol CI Parameter 25 °C Conditions input capacitance −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 3.5 - - - - - pF 74HCT423 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = −20 µA 4.4 4.5 - 4.4 - 4.4 - V IO = −4.0 mA 3.98 4.32 - 3.84 - 3.7 - V - 0 0.1 - 0.1 - 0.1 V - 0.15 0.26 - 0.33 - 0.4 V VOL LOW-level output VI = VIH or VIL; VCC = 4.5 V voltage IO = 20 µA IO = 4.0 mA II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1.0 - ±1.0 µA ICC supply current VI = VCC or GND; VCC = 5.5 V; IO = 0 A - - 8.0 - 80 - 160 µA ∆ICC additional supply current per input pin; VI = VCC − 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A - 35 126 - 158 - 172 µA - 50 180 - 225 - 245 µA - 3.5 - - - - - pF nA, nB inputs nRD input CI input capacitance 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 7 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; test circuit see Figure 12. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to Unit +125 °C Min Typ Max Min Max Min Max VCC = 2.0 V - 80 255 - 320 - 385 ns VCC = 4.5 V - 29 51 - 64 - 77 ns VCC = 5.0 V; CL = 15 pF - 25 - - - - - ns - 23 43 - 54 - 65 ns VCC = 2.0 V - 66 215 - 270 - 325 ns VCC = 4.5 V - 24 43 - 54 - 65 ns VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns - 19 37 - 46 - 55 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 100 11 - 125 - 150 - ns VCC = 4.5 V 20 4 - 25 - 30 - ns VCC = 6.0 V 17 3 - 21 - 26 - ns VCC = 2.0 V 100 17 - 125 - 150 - ns VCC = 4.5 V 20 6 - 25 - 30 - ns VCC = 6.0 V 17 5 - 21 - 26 - ns VCC = 2.0 V 100 14 - 125 - 150 - ns VCC = 4.5 V 20 5 - 25 - 30 - ns VCC = 6.0 V 17 4 - 21 - 26 - ns - 450 - - - - - µs 74HC423 tpd propagation delay nA or nB to nQ or nQ; REXT = 5 kΩ; CEXT = 0 pF; see Figure 7 [1] VCC = 6.0 V nRD to nQ or nQ; see Figure 7 [1] VCC = 6.0 V tt tW transition time pulse width [2] see Figure 7 nA input LOW; see Figure 7 and Figure 8 nB input HIGH; see Figure 7 and Figure 8 nRD input LOW; see Figure 7 and Figure 8 nQ HIGH or nQ LOW; VCC = 5.0 V; REXT = 10 kΩ; CEXT = 100 nF; see Figure 7 and Figure 8 trtrig retrigger time nQ HIGH or nQ LOW; VCC = 5.0 V; REXT = 5 kΩ; CEXT = 0 pF; VI = GND to VCC; see Figure 7 and Figure 8 [3] - 75 - - - - - ns nA or nB input; VCC = 5.0 V; REXT = 5 kΩ; CEXT = 0 pF; see Figure 10 [4] - 110 - - - - - ns 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 8 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset Table 7. Dynamic characteristics …continued GND = 0 V; test circuit see Figure 12. Symbol Parameter 25 °C Conditions Min REXT external timing VCC = 2.0 V; see Figure 8 resistor VCC = 5.0 V Typ −40 °C to +85 °C −40 °C to Unit +125 °C Max Min Max Min Max 10 - 1000 - - - - kΩ 2 - 1000 - - - - kΩ CEXT external timing VCC = 5.0 V; see Figure 8 capacitor [5] CPD power dissipation capacitance [6] - 54 - - - - - pF VCC = 4.5 V [1] - 30 51 - 64 - 77 ns VCC = 5.0 V; CL = 15 pF [1] - 26 - - - - - ns [1] - 26 48 - 60 - 72 ns VCC = 4.5 V [1] - 26 48 - 60 - 72 ns VCC = 5.0 V; CL = 15 pF [1] - 22 - - - - - ns per package; VI = GND to VCC no limits pF 74HCT423 tpd propagation delay nA or nB to nQ or nQ; REXT = 5 kΩ; CEXT = 0 pF; see Figure 7 nRD to nQ or nQ; REXT = 5 kΩ; CEXT = 0 pF; see Figure 7 [2] tt transition time VCC = 4.5 V; Figure 7 - 7 15 - 19 - 22 ns tW pulse width trigger pulse; nA input LOW; VCC = 4.5 V; see Figure 7 and Figure 10 20 5 - 25 - 30 - ns trigger pulse; nB input HIGH; VCC = 4.5 V; see Figure 7 and Figure 10 20 5 - 25 - 30 - ns reset pulse; nRD input LOW; VCC = 4.5 V; see Figure 7 and Figure 11 20 7 - 25 - 30 - ns - 450 - - - - - µs - 75 - - - - - ns - 110 - - - - - ns 2 - 1000 - - - - kΩ output pulse; nQ HIGH or nQ LOW; VCC = 5.0 V; REXT = 10 kΩ; CEXT = 100 nF; see Figure 7, Figure 10 and Figure 11 output pulse; nQ HIGH or nQ LOW; VCC = 5.0 V; REXT = 5 kΩ; CEXT = 0 pF; VI = GND to VCC − 1.5 V; see Figure 7, Figure 10 and Figure 11 trtrig retrigger time REXT external timing VCC = 5.0 V; see Figure 8 resistor CEXT external timing VCC = 5.0 V; see Figure 8 capacitor [3] nA or nB input; VCC = 5.0 V; REXT = 5 kΩ; CEXT = 0 pF; see Figure 10 [5] 74HC_HCT423_3 Product data sheet no limits pF © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 9 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset Table 7. Dynamic characteristics …continued GND = 0 V; test circuit see Figure 12. 25 °C Symbol Parameter Conditions CPD per package; VI = GND to VCC − 1.5 V [1] power dissipation capacitance [6] Min Typ - 56 −40 °C to +85 °C −40 °C to Unit +125 °C Max Min Max Min Max - - - - - pF tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] For other REXT and CEXT combinations see Figure 8. If CEXT > 10 pF, the next formula is valid: tW = K × REXT × CEXT (typ.), where: tW = output pulse width in ns; REXT = external resistor in kΩ; CEXT = external capacitor in pF; K = 0.55 for VCC = 2.0 V and 0.45 for VCC = 5.0 V; see Figure 9. Inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is 7 pF. [4] The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT. The output pulse width will only be extended when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time. If CEXT > 10 pF, the next formula (at VCC = 5.0 V) for the set-up time of a retrigger pulse is valid: trtrig = 30 + 0.19 × REXT × CEXT0.9 + 13 × REXT1.05 (typ.); where: trtrig = retrigger time in ns; CEXT = external capacitor in pF; REXT = external resistor in kΩ. Inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is 7 pF. [5] When the device is powered-up, initiate the device via a reset pulse, when CEXT < 50 pF. [6] CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo); where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑ (CL × VCC2 × fo) = sum of outputs. 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 10 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset 11. Waveforms VI nB input VM GND tW VI VM nA input GND tW tW VI VM nRD input GND tPLH tPLH VOH tPHL (reset) tPLH tPLH (reset) tPHL VY Q output VM VX VOL tW tTLH tPHL tTHL tPHL VOH VY Q output VM VX VOL tW tTHL tTLH 001aah911 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Pulse widths, propagation delays from inputs (nA, nB, nRD) to outputs (nQ, nQ) and output transition times Table 8. Measurement points Type Input Output VI VM VM VX VY 74HC423 VCC 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT423 3V 1.3 V 1.3 V 0.1VCC 0.9VCC 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 11 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset 001aaa611 106 001aaa612 0.8 tW (ns) 'K' factor (1) 105 0.6 (2) (3) 104 0.4 (4) 103 0.2 102 10 1 10 102 0 104 103 CEXT (pF) 0 2 4 6 8 VCC (V) VCC = 5.0 V and Tamb = 25 °C. External capacitance = 10 nF, external resistance = 10 kΩ to 100 kΩ and Tamb = 25 °C. (1) REXT = 100 kΩ. (2) REXT = 50 kΩ. (3) REXT = 10 kΩ. (4) REXT = 2 kΩ. Fig 8. Typical output pulse width as a function of the external capacitor values Fig 9. Typical ‘K’ factor nB input tW nA input t rt tW nQ output tW tW tW mna521 nRD = HIGH. Fig 10. Output pulse control using retrigger pulse (trtrig) 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 12 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset nB input nRD input tW nQ output tW tW mna522 nA = LOW. Fig 11. Output pulse control using reset input nRD VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 12. Test circuit for measuring switching times Table 9. Test data Supply Input VCC VI tr, tf Load CL 2.0 V to 6.0 V VCC 6 ns 15 pF, 50 pF 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 13 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset 12. Application information 12.1 Timing component connections The basic output pulse width is essentially determined by the values of the external timing components REXT and CEXT. (1) CEXT REXT VCC GND nCEXT 8 14 (6) nREXT/CEXT 15 (7) 13 (5) 423 nA nB nQ 1 (9) 2 (10) 4 (12) nQ 3 (11) nRD 001aah917 (1) For minimum noise generation it is recommended that the nCEXT pins (6, 14) are connected to ground externally to the GND pin (8). Fig 13. Timing component connections 12.1.1 Minimum monostable pulse width To set the minimum pulse width, when CEXT < 10 nF, see Figure 8 and when CEXT > 10 nF, the output pulse width is defined as: tW = 0.45 × REXT × CEXT (typ.), where: tW = pulse width in µs; REXT = external resistor in kΩ; CEXT = external capacitor in nF. 12.2 Power-up considerations When the monostable is powered-up it may produce an output pulse, with a pulse width defined by the values of REXT and CEXT, this output pulse can be eliminated using the circuit shown in Figure 14. 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 14 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset CEXT REXT VCC GND nCEXT nREXT/CEXT 8 14 (6) 15 (7) 13 (5) 423 nA nB nQ 1 (9) 2 (10) 4 (12) nQ 3 (11) nRD VCC RESET 001aah918 Fig 14. Power-up output pulse elimination circuit 12.3 Power-down considerations A large capacitor CEXT may cause problems when powering-down the monostable due to the capacitor’s stored energy. When a system containing this device is powered-down or a rapid decrease of VCC to zero occurs, the monostable may sustain damage, due to the capacitor discharging through the input protection diodes. To avoid this possibility, use a damping diode DEXT preferably a germanium or Schottky type diode able to withstand large current surges and connect as shown in Figure 15. DEXT CEXT REXT VCC GND nCEXT nREXT/CEXT 8 14 (6) 15 (7) 13 (5) 423 nA nB nQ 1 (9) 2 (10) 4 (12) nQ 3 (11) 001aah919 nRD Fig 15. Power-down protection circuit 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 15 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 16. Package outline SOT38-4 (DIP16) 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 16 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 17. Package outline SOT109-1 (SO16) 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 17 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 18. Package outline SOT763-1 (DHVQFN16) 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 18 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 19. Package outline SOT338-1 (SSOP16) 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 19 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 20. Package outline SOT403-1 (TSSOP16) 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 20 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT423_3 20080724 Product data sheet - Modifications: 74HC_HCT423_CNV_2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. • Figure 4 “Logic diagram”, Figure 13 “Timing component connections” and Figure 15 “Power-down protection circuit” redrawn. • • • • Section 10 “Dynamic characteristics” CPD values added. Section 3 “Ordering information”, Section 5 “Pinning information”and Section 13 “Package outline”, added type numbers 74HC423BQ and 74HCT423BQ (DHVQFN16 package). Figure 12 “Test circuit for measuring switching times” added. Section 12.1 “Timing component connections” moved to Section 12. Section 14 “Abbreviations” added. 19980708 Product specification 74HC_HCT423_3 Product data sheet 74HC_HCT423_CNV_2 • - - © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 21 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT423_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 July 2008 22 of 23 74HC423; 74HCT423 NXP Semiconductors Dual retriggerable monostable multivibrator with reset 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 12.1 12.1.1 12.2 12.3 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 14 Timing component connections . . . . . . . . . . . 14 Minimum monostable pulse width. . . . . . . . . . 14 Power-up considerations . . . . . . . . . . . . . . . . 14 Power-down considerations . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information. . . . . . . . . . . . . . . . . . . . . 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 24 July 2008 Document identifier: 74HC_HCT423_3