INTEGRATED CIRCUITS 74F676 16-bit serial/parallel-in, serial-out shift register (3-State) Product specification IC15 Data Handbook 1989 Apr 18 Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) FEATURES 74F676 PIN CONFIGURATION • 16-bit parallel-to-serial conversion • 16-bit serial-in, serial-out • Chip select control • Power supply current 48mA typical • Shift frequency 110MHz tyical • Available in 300mil-wide 24-pin Slim DIP package DESCRIPTION The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the mode (M) input is High, information present on the parallel data (D0–D15) inputs is entered on the falling edge of the clock pulse (CP) input signal. When M is Low, data is shifted out of the most significant bit position while information present on the serial (SI) input shifts into the least significant bit position. A High signal on the chip select (CS) input prevents both parallel and serial operations. CS 1 24 VCC CP 2 23 D15 NC 3 22 D14 SI 4 21 D13 M 5 20 D12 SO 6 19 D11 D0 7 18 D10 D1 8 17 D9 D2 9 16 D8 D3 10 15 D7 D4 11 14 D6 GND 12 13 D5 SF01209 The 16 bit shift register operates in one of three modes, as indicated in the shift register Function Table. Hold: A High signal on the Chip Select (CS) input prevents clocking and data is stored in the 16 registers. Serial load: Data present on the SI pin shifts into the register on the falling edge of CP. Data enters the Q0 position and shifts toward Q15 on successive clocks finally appearing on the SO pin. Parallel load: Data present on D0–D15 is entered into the register on the falling edge of CP. The SO output represents the Q15 register output. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F676 110MHz 48mA ORDERING INFORMATION To prevent false clocking, CP must be Low during a Low-to-High transition of CS. DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG DWG # 24-Pin Plastic Slim DIP (300mil) N74F676N SOT222-1 24-Pin Plastic SOL N74F676D SOT137-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0–D15 Parallel data inputs 1.0/1.0 20µA/0.6mA SI Serial data input 1.0/1.0 20µA/0.6mA CS Chip Select input (active Low) 1.0/1.0 20µA/0.6mA CP Clock Pulse input (active falling edge) 1.0/1.0 20µA/0.6mA M Mode select input 1.0/1.0 20µA/0.6mA SO Serial data output 50/33 1mA/20mA NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state. 1990 Apr 18 2 853–0284 99394 Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) LOGIC SYMBOL 4 7 8 74F676 LOGIC DIAGRAM 9 10 11 13 14 15 16 17 18 19 20 21 22 CP 23 CS M 2 1 5 SI D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 1 SI CS D0 2 CP 5 M 4 CP 7 D 8 D Q CP SO D1 Q CP VCC = Pin 24 GND = Pin 12 6 SF01210 D2 9 Q D LOGIC SYMBOL (IEEE/IEC) CP D3 10 Q D SRG16 5 0 M 1 1 CP D4 11 Q D & C3/1 2 7 0 2 CP D5 2, 3D 13 Q D 8 CP 9 D6 10 14 D 15 D Q 11 CP 13 14 D7 Q 15 CP 16 17 D8 16 D 17 D 18 D 19 D Q 18 CP 19 20 D9 Q 21 22 CP 23 6 2, 3D 4 D10 Q 1, 3D CP SF01211 D11 Q CP FUNCTION TABLE D12 CONTROL INPUTS CS H L X ↓ = = = = M X X Hold L L ↓ Shift/Serial load Q D OPERATING MODE CP H CP D13 21 Q D CP L H ↓ Parallel load High voltage level Low voltage level Don’t care High-to-Low transition of clock input 1990 Apr 18 20 D14 22 Q D CP 23 D15 VCC = Pin 24 GND = Pin 12 3 D 6 Q SO SF01212 Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) 74F676 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V VCC Supply voltage –0.5 to +7.0 VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5.0 mA VOUT Voltage applied to output in High output state –0.5 to +VCC V IOUT Current applied to output in Low output state 40 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL LIMITS PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 V VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range 70 °C V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL PARAMETER TEST CONDITIONSNO TAG MIN VOH O High level output voltage High-level VOL O Low level output voltage Low-level VIK Input clamp voltage II Input current at maximum input voltage IIH IIL VCC = MIN,, VIL = MAX,, VIH = MIN, IOH = MAX ±10%VCC 2.5 ±5%VCC 2.7 ±10%VCC TYP NO TAG UNIT MAX V 3.4 V 0.30 0.50 V 0.30 0.50 V –0.73 –1.2 V VCC = MAX, VI = 7.0V 100 µA High-level input current VCC = MAX, VI = 2.7V 20 µA Low-level input current VCC = MAX, VI = 0.5V –0.6 mA –150 mA 72 mA VCC = MIN,, VIL = MAX,, VIH = MIN, IOL = MAX currentNO TAG IOS Short-circuit output ICC Supply current (total) ±5%VCC VCC = MIN, II = IIK VCC = MAX VCC = MAX –60 48 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value under the recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS should be performed last. 1990 Apr 18 4 Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) 74F676 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω TEST CONDITION PARAMETER MIN TYP fMAX Maximum clock frequency Waveform NO TAG 100 110 tPLH tPHL Propagation delay CP to SO Waveform NO TAG 4.5 5.0 8.0 7.0 MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX 90 11.0 12.5 4.5 5.0 MHz 12.0 13.5 ns ns AC SETUP REQUIREMENTS LIMITS S O SYMBOL Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω S CO O TEST CONDITION PARAMETER MIN TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX ts(H) ts(L) Setup time, High or Low SI to CP Waveform 2 4.0 4.0 4.0 4.0 ns ns th(H) th(L) Hold time, High or Low SI to CP Waveform 2 4.0 4.0 4.0 4.0 ns ns ts(H) ts(L) Setup time, High or Low Dn to CP Waveform 2 3.0 3.0 3.0 3.0 ns ns th(H) th(L) Hold time, High or Low Dn to CP Waveform 2 4.0 4.0 4.0 4.0 ns ns ts(H) ts(L) Setup time, High or Low M to CP Waveform 2 8.0 8.0 8.0 8.0 ns ns th(H) th(L) Hold time, High or Low M to CP Waveform 2 2.0 2.0 2.0 2.0 ns ns ts(L) Setup time, Low CS to CP Waveform 2 10.0 10.0 ns th(H) Hold time, High CS to CP Waveform 2 10.0 10.0 ns tw(H) tw(L) CP Pulse width, High or Low Waveform NO TAG 4.0 6.0 4.0 6.0 ns ns AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX CP Dn, CS, M, SI VM VM tw(L) VM ts(H) VM th(H) VM VM ts(L) th(L) tw(H) tPHL tPLH CP SO VM VM VM SF01213 SF01214 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency 1990 Apr 18 VM VM Waveform 2. Setup and Hold Times 5 Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) 74F676 TEST CIRCUIT AND WAVEFORM VCC NEGATIVE PULSE VIN tw 90% VM D.U.T. RT CL RL AMP (V) VM 10% VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% Test Circuit for Totem-Pole Outputs 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 1990 Apr 18 6 Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) DIP24: plastic dual in-line package; 24 leads (300 mil) 1989 Apr 18 7 74F676 SOT222-1 Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) SO24: plastic small outline package; 24 leads; body width 7.5 mm 1989 Apr 18 8 74F676 SOT137-1 Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) NOTES 1989 Apr 18 9 74F676 Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) 74F676 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 10 Date of release: 10-98 397-750-05173