INTEGRATED CIRCUITS 74F194 4-bit bidirectional universal shift register Product specification IC15 Data Handbook 1989 Apr 04 Philips Semiconductors Product specification 4-bit bidirectional universal shift register FEATURES 74F194 PIN CONFIGURATION • Shift right and shift left capability • Synchronous parallel and serial data transfer • Easily expanded for both serial and parallel operation • Asynchronous Master Reset • Hold (do nothing) mode MR 1 16 VCC DSR 2 15 Q0 D0 3 14 Q1 D1 4 13 Q2 D2 5 12 Q3 D3 6 11 CP DSL 7 10 S1 GND 8 9 S0 DESCRIPTION The functional characteristics of the 74F194 4-Bit Bidirectional Shift Register are indicated in the Logic Diagram and Function Table. The register is fully synchronous, with all operations taking place in less than 9ns (typical) for 74F, making the device especially useful for implementing very high speed CPUs, or for memory buffer registers. SF00167 The 74F194 design has special logic features which increase the range of application. The synchronous operation of the device is determined by two Mode Select inputs, S0 and S1. As shown in the Mode Select-Function Table, data can be entered and shifted from left to right (shift right, Q0→Q1, etc.), or right to left (shift left, Q3→Q2, etc.), or parallel data can be entered, loading all 4 bits of the register simultaneously. When both S0 and S1 are Low, existing data is retained in a hold (do nothing) mode. The first and last stages provide D-type Serial Data inputs (DSR, DSL) to allow multistage shift right or shift left data transfers without interfering with parallel load operation. Mode Select and data inputs on the 74F194 are edge-triggered, responding only to the Low-to-High transition of the Clock (CP). Therefore, the only timing restriction is that the Mode Select and selected data inputs must be stable one setup time prior to the Low-to-High transition of the clock pulse. Signals on the Mode Select, Parallel Data (D0–D3) and Serial Data (DSR, DSL) can change when the clock is in either state, provided only the recommended setup and hold times, with respect to the clock rising edge, are observed. The four Parallel Data inputs (D0–D3) are D-type inputs. Data appearing on (D0–D3) inputs when S0 and S1 are High is transferred to the Q0–Q3 outputs respectively, following the next Low-to-High transition of the clock. When Low, the asynchronous Master Reset (MR) overrides all other input conditions and forces the Q outputs Low. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F194 150MHz 33mA ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG DWG # 16-pin plastic DIP N74F194N SOT38-4 16-pin plastic SO N74F194D SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Parallel data inputs 1.0/1.0 20µA/0.6mA DSR Serial data input (Shift Right) 1.0/1.0 20µA/0.6mA DSL Serial data input (Shift Left) 1.0/1.0 20µA/0.6mA Mode Select inputs 1.0/1.0 20µA/0.6mA CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA MR Asynchronous master Reset input (Active Low) 1.0/1.0 20µA/0.6mA Data outputs 50/33 1.0mA/20mA D0–D3 S0, S1 Q0–Q3 DESCRIPTION NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. April 4, 1989 2 853–0354 96224 Philips Semiconductors Product specification 4-bit bidirectional universal shift register LOGIC SYMBOL IEC/IEEE SYMBOL 2 DSR 3 D0 4 D1 5 D2 6 7 D3 DSL S0 10 S1 11 CP 1 MR SRG8 1 R 9 0 10 1 11 9 M 0 3 C4 1 → /2 ← Q0 VCC = Pin 24 GND = Pin 12 74F194 15 Q1 14 Q2 13 Q3 12 2 1, 4D 3 3, 4D 15 4 3, 4D 14 5 3, 4D 13 6 3, 4D 7 12 2, 4D SF00168 SF00169 LOGIC DIAGRAM S1 S0 DSL D3 10 9 7 S 6 CP R Q3 5 Q2 4 Q1 2 CP 15 Q0 RD 1 11 VCC = Pin 24 GND = Pin 12 April 4, 1989 Q0 CP R MR Q1 RD S DSR 14 CP R 3 Q2 RD S D0 13 CP R D1 Q3 RD S D2 12 SF00170 3 Philips Semiconductors Product specification 4-bit bidirectional universal shift register 74F194 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES CP MR S1 S0 DSR DSL Dn Q0 Q1 Q2 Q3 X L X X X X X L L L L Reset (clear) X H l l X X X q0 q1 q2 q3 Hold (do nothing) ↑ H h l X l X q1 q2 q3 L ↑ H h l X h X q1 q2 q3 H ↑ H l h l X X L q0 q1 q2 ↑ H l h h X X H q0 q1 q2 ↑ H h h X X dn d0 d1 d2 d3 Shift left Shift right Parallel load H = High voltage level h = High voltage level one setup time prior to Low-to-High clock transition L = Low voltage level l = Low voltage level one setup time prior to Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition. ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 40 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range +70 °C April 4, 1989 0 4 V V Philips Semiconductors Product specification 4-bit bidirectional universal shift register 74F194 DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER UNIT ±10%VCC 2.5 ±5%VCC 2.7 VCC = MIN, VIL = MAX ±10%VCC 0.30 0.50 VIH = MIN, IOL = MAX ±5%VCC 0.30 0.50 –0.73 –1.2 V VCC = MAX, VI = 7.0V 100 µA VCC = MAX, VI = 2.7V 20 µA VOL O Low level output voltage Low-level VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage IIH High-level input current IIL Low-level input current VCC = MAX, VI = 0.5V IOS Short-circuit output current4 VCC = MAX Supply current MAX VIH = MIN, IOH = MAX High level output voltage3 High-level ICC TYP2 MIN VCC = MIN, VIL = MAX VOH O (total)5 LIMITS TEST CONDITIONS1 V 3.4 –60 VCC = MAX 33 V –0.6 mA –150 mA 46 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Output High state will change to Low stat if an external voltage of less than 0.0V is applied. 4. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 5. With all outputs open, Di inputs grounded and a 4.5V applied to S0, S1, MR and the serial inputs, ICC is tested with a momentary ground, then 4.5V applied to CP. AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER VCC = +5.0V Tamb = +25°C CL = 50pF, RL = 500Ω TEST CONDITION MIN TYP VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MAX MIN UNIT MAX fMAX Maximum clock frequency Waveform 1 105 150 tPLH tPHL Propagation delay CP to Qn Waveform 1 3.5 3.5 5.2 5.5 7.0 7.0 3.5 3.5 90 8.0 8.0 MHz ns tPHL Propagation delay MR to Qn Waveform 2 4.5 8.6 12.0 4.5 14.0 ns TEST CONDITION VCC = +5.0V Tamb = +25°C CL = 50pF, RL = 500Ω AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER MIN TYP MAX VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MIN UNIT MAX tS(H) tS(L) Setup time, High or Low Dn, DSL, DSR to CP Waveform 3 4.0 4.0 4.0 4.0 ns th(H) th(L) Hold time, High or Low Dn, DSL, DSR to CP Waveform 3 0 0 1.0 1.0 ns tS(H) tS(L) Setup time, High or Low Sn to CP Waveform 3 8.0 8.0 9.0 8.0 ns th(H) th(L) Hold time, High or Low Sn to CP Waveform 3 0 0 0 0 ns tW(H) CP Pulse width, High Waveform 1 5.0 5.5 ns tW(L) MR Pulse width, Low Waveform 2 5.0 5.0 ns tREC Recovery time, MR to CP Waveform 2 7.0 8.0 ns April 4, 1989 5 Philips Semiconductors Product specification 4-bit bidirectional universal shift register 74F194 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. MR 1/fMAX CP VM VM VM tw(L) VM tREC VM CP tw(H) tPLH tPHL Qn VM tPHL VM VM Qn VM SF00171 SF00158 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency Dn, DSR, DSL S0, S1 VM VM VM VM ts(H) th(H) ts(L) th(L) CP VM Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time VM SF00172 Waveform 3. Setup and Hold Times TIMING DIAGRAM Typical Clear, Load, Shift-Right, Shift-Left and Inhibit Sequence CP S0 S1 MR SERIAL DATA INPUTS DSR DSL D0 PARALLEL DATA INPUTS H D1 L D2 H D3 L Q0 Q1 OUTPUTS Q2 Q3 SHIFT RIGHT CLEAR SHIFT LEFT INHIBIT CLEAR LOAD SF00173 April 4, 1989 6 Philips Semiconductors Product specification 4-bit bidirectional universal shift register 74F194 TEST CIRCUIT AND WAVEFORMS VCC VIN tw 90% NEGATIVE PULSE VM D.U.T. RT CL RL AMP (V) VM 10% VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 April 4, 1989 7 Philips Semiconductors Product specification 4-bit bidirectional universal shift register DIP16: plastic dual in-line package; 16 leads (300 mil) 1989 Apr 04 8 74F194 SOT38-4 Philips Semiconductors Product specification 4-bit bidirectional universal shift register SO16: plastic small outline package; 16 leads; body width 3.9 mm 1989 Apr 04 9 74F194 SOT109-1 Philips Semiconductors Product specification 4-bit bidirectional universal shift register 74F194 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. 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