74AUP1G86 Low-power 2-input EXCLUSIVE-OR gate Rev. 02.00 — 16 May 2006 Product data sheet 1. General description The 74AUP1G86 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G86 provides the single 2-input EXCLUSIVE-OR function. 2. Features ■ Wide supply voltage range from 0.8 V to 3.6 V ■ High noise immunity ■ Complies with JEDEC standards: ◆ JESD8-12 (0.8 V to 1.3 V) ◆ JESD8-11 (0.9 V to 1.65 V) ◆ JESD8-7 (1.2 V to 1.95 V) ◆ JESD8-5 (1.8 V to 2.7 V) ◆ JESD8-B (2.7 V to 3.6 V) ■ ESD protection: ◆ HBM JESD22-A114-C Class 3A. Exceeds 5000 V ◆ MM JESD22-A115-A exceeds 200 V ◆ CDM JESD22-C101-C exceeds 1000 V ■ Low static power consumption; ICC = 0.9 µA (maximum) ■ Latch-up performance exceeds 100 mA per JESD 78 Class II ■ Inputs accept voltages up to 3.6 V ■ Low noise overshoot and undershoot < 10 % of VCC ■ IOFF circuitry provides partial Power-down mode operation ■ Multiple package options ■ Specified from −40 °C to +85 °C and −40 °C to +125 °C 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate 3. Ordering information Table 1: Ordering information Type number Package Temperature range Name Description Version 74AUP1G86GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74AUP1G86GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 74LVC1G86GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2: Marking Type number Marking code 74AUP1G86GW pH 74AUP1G86GM pH 74AUP1G86GF pH 5. Functional diagram 1 2 B A Y 1 4 =1 2 4 mna039 mna038 Fig 1. Logic symbol Fig 2. IEC logic symbol B Y A mna040 Fig 3. Logic diagram 74AUP1G86_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 2 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate 6. Pinning information 6.1 Pinning 74AUP1G86 74AUP1G86 B 1 A 2 GND 3 5 VCC B 1 6 VCC A 2 5 n.c. GND 4 Y 3 4 74AUP1G86 Y 001aaf042 Fig 4. Pin configuration SOT353-1 (TSSOP5) Fig 5. Pin configuration SOT886 (XSON6) 1 6 VCC A 2 5 n.c. GND 3 4 Y 001aaf043 Transparent top view Transparent top view 001aaf041 B Fig 6. Pin configuration SOT891 (XSON6) 6.2 Pin description Table 3: Pin description Symbol Pin Description TSSOP5 XSON6 B 1 1 data input B A 2 2 data input A GND 3 3 ground (0 V) Y 4 4 data output Y n.c. - 5 not connected VCC 5 6 supply voltage 7. Functional description Table 4: Function table [1] Input Output A B Y L L L L H H H L H H H L [1] H = HIGH voltage level; L = LOW voltage level. 74AUP1G86_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 3 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Min Max Unit −0.5 +4.6 V - −50 mA −0.5 +4.6 V - −50 mA active mode [1] −0.5 VCC + 0.5 V Power-down mode [1] −0.5 +4.6 V - ±20 mA VO < 0 V IO output current VO = 0 V to VCC ICC quiescent supply current - +50 mA IGND ground current - −50 mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 250 mW Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V −40 +125 °C 0 200 ns/V Tamb ambient temperature ∆t/∆V input transition rise and fall rate VCC = 0.8 V to 3.6 V 74AUP1G86_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 4 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 °C VIH VIL VOH VOL HIGH-state input voltage LOW-state input voltage HIGH-state output voltage LOW-state output voltage VCC = 0.8 V 0.70 × VCC - - V VCC = 0.9 V to 1.95 V 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30 × VCC V VCC = 0.9 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V IO = −1.1 mA; VCC = 1.1 V 0.75 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.11 - V VI = VIH or VIL - IO = −1.9 mA; VCC = 1.65 V 1.32 - - V IO = −2.3 mA; VCC = 2.3 V 2.05 - - V IO = −3.1 mA; VCC = 2.3 V 1.9 - - V IO = −2.7 mA; VCC = 3.0 V 2.72 - - V IO = −4.0 mA; VCC = 3.0 V 2.6 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V VI = VIH or VIL IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.1 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.2 µA ∆IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.2 µA ICC quiescent supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 µA ∆ICC additional quiescent supply VI = VCC − 0.6 V; IO = 0 A; current VCC = 3.3 V - - 40 µA CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 0.8 - pF CO output capacitance VO = GND; VCC = 0 V - 1.7 - pF 74AUP1G86_2 Product data sheet [1] © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 5 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC = 0.8 V Typ Max Unit 0.70 × VCC - - V VCC = 0.9 V to 1.95 V 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30 × VCC V VCC = 0.9 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V Tamb = −40 °C to +85 °C VIH VIL VOH VOL HIGH-state input voltage LOW-state input voltage HIGH-state output voltage LOW-state output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V IO = −1.1 mA; VCC = 1.1 V 0.7 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.03 - - V IO = −1.9 mA; VCC = 1.65 V 1.30 - - V IO = −2.3 mA; VCC = 2.3 V 1.97 - - V IO = −3.1 mA; VCC = 2.3 V 1.85 - - V IO = −2.7 mA; VCC = 3.0 V 2.67 - - V IO = −4.0 mA; VCC = 3.0 V 2.55 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V VI = VIH or VIL IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V - - 0.45 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V IO = 4.0 mA; VCC = 3.0 V - - ±0.5 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.5 µA ∆IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.6 µA ICC quiescent supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 µA ∆ICC additional quiescent supply VI = VCC − 0.6 V; IO = 0 A; current VCC = 3.3 V - - 50 µA 74AUP1G86_2 Product data sheet [1] © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 6 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC = 0.8 V Typ Max Unit 0.75 × VCC - - V VCC = 0.9 V to 1.95 V 0.70 × VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.25 × VCC V VCC = 0.9 V to 1.95 V - - 0.30 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V Tamb = −40 °C to +125 °C HIGH-state input voltage VIH LOW-state input voltage VIL VOH HIGH-state output voltage LOW-state output voltage VOL VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.11 - - V IO = −1.1 mA; VCC = 1.1 V 0.6 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 0.93 - - V IO = −1.9 mA; VCC = 1.65 V 1.17 - - V IO = −2.3 mA; VCC = 2.3 V 1.77 - - V IO = −3.1 mA; VCC = 2.3 V 1.67 - - V IO = −2.7 mA; VCC = 3.0 V 2.40 - - V IO = −4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - 0.33 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.41 VI = VIH or VIL V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V - - 0.50 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V IO = 4.0 mA; VCC = 3.0 V - - ±0.75 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.75 µA ∆IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.75 µA ICC quiescent supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 µA ∆ICC additional quiescent supply VI = VCC − 0.6 V; IO = 0 A; current VCC = 3.3 V - - 75 µA [1] [1] One input at VCC − 0.6 V, other input at VCC or GND. 74AUP1G86_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 7 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate 11. Dynamic characteristics Table 8: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol Parameter Conditions Min Typ - [1] Max Unit 21.2 - ns 2.3 5.9 13.1 ns 1.8 4.1 7.7 ns Tamb = 25 °C; CL = 5 pF tPHL, tPLH see Figure 7 HIGH-to-LOW and LOW-to-HIGH VCC = 0.8 V propagation delay A or B to Y VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V 1.5 3.3 5.9 ns VCC = 2.3 V to 2.7 V 1.2 2.6 4.4 ns VCC = 3.0 V to 3.6 V 1.0 2.3 4.0 ns - 24.7 - ns 2.6 6.8 14.8 ns 2.2 4.8 8.7 ns Tamb = 25 °C; CL = 10 pF tPHL, tPLH HIGH-to-LOW and see Figure 7 LOW-to-HIGH VCC = 0.8 V propagation delay A or B to Y VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V 1.8 3.9 6.7 ns VCC = 2.3 V to 2.7 V 1.5 3.1 5.2 ns VCC = 3.0 V to 3.6 V 1.3 2.9 4.8 ns - 28.2 - ns 3.0 7.6 16.5 ns 2.4 5.3 9.6 ns Tamb = 25 °C; CL = 15 pF tPHL, tPLH HIGH-to-LOW and see Figure 7 LOW-to-HIGH VCC = 0.8 V propagation delay A or B to Y VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V 2.1 4.4 7.5 ns VCC = 2.3 V to 2.7 V 1.8 3.6 5.9 ns VCC = 3.0 V to 3.6 V 1.6 3.3 5.4 ns - 38.5 - ns 3.9 9.9 21.5 ns 3.2 6.9 12.5 ns Tamb = 25 °C; CL = 30 pF tPHL, tPLH HIGH-to-LOW and see Figure 7 LOW-to-HIGH VCC = 0.8 V propagation delay A or B to Y VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V 2.8 5.7 9.8 ns VCC = 2.3 V to 2.7 V 2.4 4.7 7.6 ns VCC = 3.0 V to 3.6 V 2.2 4.4 7.1 ns 74AUP1G86_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 8 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate Table 8: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol Parameter Conditions Min Typ VCC = 0.8 V - VCC = 1.1 V to 1.3 V - VCC = 1.4 V to 1.6 V [1] Max Unit 2.7 - pF 2.9 - pF - 3.0 - pF VCC = 1.65 V to 1.95 V - 3.1 - pF VCC = 2.3 V to 2.7 V - 3.6 - pF VCC = 3.0 V to 3.6 V - 4.2 - pF Tamb = 25 °C power dissipation capacitance f = 1 MHz; VI = GND to VCC CPD [1] All typical values are measured at nominal VCC. [2] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [2] Table 9: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol Parameter −40 °C to +85 °C Conditions −40 °C to +125 °C Min Max Min Max Unit CL = 5 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A or B to Y see Figure 7 VCC = 1.1 V to 1.3 V 2.1 14.3 2.1 15.8 ns VCC = 1.4 V to 1.6 V 1.6 8.8 1.6 9.7 ns VCC = 1.65 V to 1.95 V 1.4 6.9 1.4 7.6 ns VCC = 2.3 V to 2.7 V 1.1 5.3 1.1 5.9 ns VCC = 3.0 V to 3.6 V 0.9 4.7 0.9 5.2 ns VCC = 1.1 V to 1.3 V 2.4 16.2 2.4 17.9 ns VCC = 1.4 V to 1.6 V 1.9 10.0 1.9 11.0 ns VCC = 1.65 V to 1.95 V 1.7 8.0 1.7 8.8 ns VCC = 2.3 V to 2.7 V 1.4 6.2 1.4 6.9 ns VCC = 3.0 V to 3.6 V 1.3 5.6 1.3 6.2 ns CL = 10 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A or B to Y see Figure 7 74AUP1G86_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 9 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate Table 9: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol Parameter −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Max Min Max VCC = 1.1 V to 1.3 V 2.7 18.1 2.7 20.0 ns VCC = 1.4 V to 1.6 V 2.2 11.3 2.2 12.5 ns VCC = 1.65 V to 1.95 V 1.9 9.0 1.9 9.9 ns VCC = 2.3 V to 2.7 V 1.6 7.0 1.6 7.7 ns VCC = 3.0 V to 3.6 V 1.5 6.4 1.5 7.1 ns CL = 15 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A or B to Y see Figure 7 CL = 30 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A or B to Y see Figure 7 VCC = 1.1 V to 1.3 V 3.5 24.1 3.5 26.6 ns VCC = 1.4 V to 1.6 V 2.8 14.8 2.8 16.3 ns VCC = 1.65 V to 1.95 V 2.5 11.7 2.5 12.9 ns VCC = 2.3 V to 2.7 V 2.2 9.1 2.2 10.1 ns VCC = 3.0 V to 3.6 V 2.1 8.3 2.1 9.2 ns 12. Waveforms VI VM A, B input GND t PHL t PLH VOH VM Y output mna615 VOL Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The data input (A or B) to output (Y) propagation delays Table 10: Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns 74AUP1G86_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 10 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate VCC VEXT 5 kΩ PULSE GENERATOR VI VO DUT RT CL RL 001aac521 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Load circuitry for switching times Table 11: Test data Supply voltage Load VEXT VCC CL 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ [1] RL [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ open GND 2 × VCC For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 74AUP1G86_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 11 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC JEITA MO-203 SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 9. Package outline SOT353-1 (TSSOP5) 74AUP1G86_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 12 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 4 e1 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 Fig 10. Package outline SOT886 (XSON6) 74AUP1G86_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 13 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 L L1 e 6 5 4 e1 e1 A A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-03-11 05-04-06 SOT891 Fig 11. Package outline SOT891 (XSON6) 74AUP1G86_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 14 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate 14. Abbreviations Table 12: Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor Transistor Logic 15. Revision history Table 13: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes 74AUP1G86_1 <tbd> Product data sheet - - - 74AUP1G86_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 15 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate 16. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19. Trademarks 18. Disclaimers Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 20. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 74AUP1G86_2 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 02.00 — 16 May 2006 16 of 17 74AUP1G86 Philips Semiconductors Low-power 2-input EXCLUSIVE-OR gate 21. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information . . . . . . . . . . . . . . . . . . . . 16 © Koninklijke Philips Electronics N.V. 2006 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 16 May 2006 Document number: 74AUP1G86_2 Published in The Netherlands