Philips Semiconductors Product specification Arithmetic Logic Unit 74F381 FEATURES PIN CONFIGURATION • Low-input loading minimizes drive requirements • Performs six arithmetic and logic functions • Selectable Low (clear) and High (preset) functions • Carry Generate and Propagate outputs for use with Carry A1 1 20 V CC B1 2 19 A2 A0 3 18 B2 B0 4 17 A3 S0 5 16 B3 DESCRIPTION S1 6 15 Cn The 74F381 performs three arithmetic and three logic operations on two 4-bit words, A and B. Three additional Select (S0–S2) input codes force the Function outputs Low or High. Carry Propagate (P) and Generate (G) ouputs are provided for use with the 74F182 Carry Look Ahead Generator for high-speed expansion to longer word lengths. For ripple expansion, refer to the 74F382 ALU data sheet. S2 7 14 P 8 13 G look-ahead generator F0 F1 9 12 F3 GND 10 11 F2 SF00921 Signals applied to the Select inputs (S0–S2) determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output function levels is shown in the Function Table. The circuit performs the arithmetic functions for either active-HIgh or active-Low operands, with output levels in the same convention. In the subtract operating modes, it is necessary to force a Carry (High for active-HIgh operands, Low for active-Low operands) into the Cn input of the least significant package. The Carry Generate (G) and Carry Propagate (P) outputs supply input signals to the 74F182 Carry look-ahead generator for expansion to longer word length, as shown in Figure 1. Note that a 74F382 ALU is used for the most significant package. Typical delays for Figure 1 are given in Table 1. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 6.5ns 59mA 74F381 ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 20-pin plastic DIP N74F381N 20-pin plastic SO N74F381D INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW A0 – A3 A operand inputs 1.0/4.0 20µA/2.4mA B0 – B3 A operand inputs 1.0/4.0 20µA/2.4mA S0 – S2 Function select inputs 1.0/1.0 20µA/0.6mA Carry input 1.0/4.0 20µA/2.4mA P Carry Propagate ouptut (active-Low) 50/33 1.0mA/20mA G Carry Generate ouptut (active-Low) 50/33 1.0mA/20mA 50/33 1.0mA/20mA Cn F0–F3 Outputs NOTE: One (1.0) FAST unit load is defined as 20µA in the High state and 0.6mA in the Low state. 1989 Mar 01 1 853–0418 95907 Philips Semiconductors Product specification Arithmetic Logic Unit 74F381 LOGIC SYMBOL IEC/IEEE SYMBOL 5 3 4 1 2 19 18 17 16 ALU 0 6 7 A0 B0 A1 B1 A2 B2 A3 B3 Cn 5 S0 6 S1 7 S2 G P 13 14 F0 F1 F2 F3 P Q 1 9 11 12 18 SF00922 17 16 1989 Mar 01 2 (1/2/3) CP 14 (1/2/3) CG 13 3 Cl 4 19 8 4 3 2 VCC = Pin 20 GND = Pin 10 0 7 (1/2) Bl 15 15 M P Q P Q P Q 8 [1] [2] 9 [4] 11 [8] 12 SF00923 Philips Semiconductors Product specification Arithmetic Logic Unit 74F381 LOGIC DIAGRAM Cn A0 15 3 8 B0 A1 4 1 9 B1 A2 F0 F1 2 19 11 F2 B2 A3 18 17 12 F3 14 P B3 16 13 S0 S1 5 G 6 7 S2 VCC = Pin 20 GND = Pin 10 1989 Mar 01 SF00924 3 Philips Semiconductors Product specification Arithmetic Logic Unit 74F381 FUNCTION TABLE INPUTS OUTPUTS S0 S1 S2 Cn An Bn F0 F1 F2 F3 G P OPERATING MODE Clear L L L X X X L L L L L L H L L L L L H H H H H L H L L L L H L H H H L L H L L L H L L L L L H H H L L L H H H H H H H L H L L H L L L L L L H L H L L H L H H H H H L L H L L H H L H L L L H H H L L H H H L L L L H L L H L L L L H H H H H L L H L L L H L L L L H H L H L L H L L H H H L L L H L L H H H H H H H L L H L H L L L L L L H L L H L H L H H L L L H H L H L H H L H H H H L L L H L H H H L L L L H L H H L L L L L L L L H H H H L L L H H H H H H L H H L L H L H H H H H L H H L L H H L H H H L L H H L H L L H L L L H H H H L H L H L L L L H L H H L H H L L L L L H L H H L H H H H H H H L L L L H X L L L L L L H H L L H X L H H H H H H H L L H X H L H H H H H L L L H X H H L L L L L L H L H X L L L L L L H H H L H X L H H H H H H H H L H X H L H H H H H H L H L H X H H H H H H H L H H X L L L L L L L L L H H X L H L L L L H H L H H X H L L L L L L L L H H X H H H H H H H L H H H X L L H H H H H H H H H X L H H H H H H H H H H X H L H H H H H H H H H X H H H H H H H L H = High voltage level L = Low voltage level X = Don’t care 1989 Mar 01 4 B minus A A minus B A Plus B AB A+B AB Preset Philips Semiconductors Product specification Arithmetic Logic Unit 74F381 FUNCTION SELECT TABLE Table 1. 16-Bit Delay Tabulation SELECT PATH SEGMENT TOWARD F OUTPUT Cn+4, OVR Clear Ai or Bi to P 7.2ns 7.2ns B minus A Pi to Cn+i (74F182) 6.2ns 6.2ns A minus B Cn to F 8.1ns – – 8.0ns 21.5ns 21.4ns S0 S1 S2 OPERATING MODE L L L H L L L H L H H L A Plus B Cn to Cn+4, OVR L L H AB Total Delay H L H A+B L H H AB H Preset H H H = High voltage level L = Low voltage level APPLICATION A0–A3 B0–B3 4 4 A CIN A4–A7 4 B B F Q P A12–A15 4 A B F Q P B Cn+4 Cn F 3 Q 4 A 74F381 S B12–B15 4 Cn 74F381 S B8–B11 4 Cn 74F381 3 SELECT A8–A11 4 A Cn S B4–B7 F P 3 COUT 74F382 S OVERFLOW OVR 3 3 F0–F3 F4–F7 G0 P0 Cn+x F8–F11 G1 Cn P1 Cn+y G2 F12–F15 P2 Cn+z 74F182 SF00925 Figure 1. 16-bit Look-ahead Carry ALU Expansion ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V VCC Supply voltage –0.5 to +7.0 VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +1 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 40 mA Tamb Operating free-air temperature range 0 to +70 °C TSTG Storage temperature range –65 to +150 °C 1989 Mar 01 5 Philips Semiconductors Product specification Arithmetic Logic Unit 74F381 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARMETER SYMBOL MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range 70 °C V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL TEST PARAMETER LIMITS CONDITIONS1 MIN ±10%VCC 2.5 VIH = MIN, IOH = MAX ±5%VCC 2.7 VCC = MIN, VIL = MAX, ±10%VCC 0.30 0.50 V VIH = MIN, IOL = MAX ±5%VCC 0.30 0.50 V –0.73 –1.2 V 100 µA High-level output voltage VOL Low-level output voltage VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High-level input current VCC = MAX, VI = 2.7V An, Bn, Cn IOS Low-level input current Short-circuit output current3 S0, S1, S2 UNIT MAX VCC = MIN, VIL = MAX, VOH IIL TYP2 VCC = MAX, VI = 0.5V VCC = MAX –60 V 3.4 V 20 µA –2.4 mA –0.6 mA –150 mA ICC Supply current (total) VCC = MAX 59 89 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1989 Mar 01 6 Philips Semiconductors Product specification Arithmetic Logic Unit 74F381 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN TYP MAX MIN MAX UNIT tPLH tPHL Propagation delay Cn to Fn Waveform 1 2.5 2.5 6.0 4.5 11.0 6.5 2.5 2.5 12.5 7.5 ns tPLH tPHL Propagation delay Any An or Bn to any Fn Waveform 1 3.5 3.0 7.0 6.0 13.0 9.0 3.5 3.0 16.0 10.0 ns tPLH tPHL Propagation delay Sn to Fn Waveform 1 5.0 4.0 9.0 7.5 20.0 10.5 5.0 4.0 21.5 11.5 ns tPLH tPHL Propagation delay An to Bn to G Waveform 1 3.5 3.0 6.5 6.0 9.0 8.5 3.5 3.0 10.0 9.0 ns tPLH tPHL Propagation delay An or Bn to P Waveform 1 3.0 3.5 5.5 6.0 8.0 8.5 3.0 3.5 9.0 9.0 ns tPLH tPHL Propagation delay Sn to G or P Waveform 1 5.0 5.5 7.5 8.5 11.0 12.5 5.0 5.0 12.5 14.0 ns AC WAVEFORMS For all waveforms, VM = 1.5V. VIN VM VM tPLH tPHL VOUT VM VM SF00926 Waveform 1. Propagation Delay for Non-Inverting or Inverting paths TEST CIRCUIT AND WAVEFORM VCC VIN tw 90% NEGATIVE PULSE 10% D.U.T. RT CL RL AMP (V) VM VM VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% POSITIVE PULSE VM VM 10% Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 90% 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 1989 Mar 01 7