TDA9910 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) direct/ultra high IF sampling Rev. 02 — 9 December 2004 Objective data sheet 1. General description The TDA9910 is a 12-bit Analog-to-Digital Converter (ADC) optimized for direct IF sampling, and supporting the most demanding use conditions in ultra high IF radio transceivers for cellular infrastructure and other applications such as wireless access system, optical networking and fixed telecommunication. Thanks to its broadband input capabilities, the TDA9910 is ideal for single and multiple carriers data conversion. Operating at a maximum sampling rate of 80 Msample/s, analog input signals are converted into 12-bit binary coded digital words. All static digital inputs are CMOS compatible. All output signals are LVCMOS compatible. The TDA9910 offers the most possible flexible acquisition control system thanks to its programmable Complete Conversion Signal (CCS) that allows to adjust the delay of the acquisition clock. Thanks to its internal front-end buffer, the TDA9910 offers the lowest input capacitance (< 1 pF) and therefore the highest flexibility in front-end aliasing filter strategy. Released in HTQFP48, it keeps the industry's smallest ADC of its category. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 12-bit resolution Direct IF sampling up to 370 MHz 90 dB SFDR; 71 dB SNR (fi = 225 MHz; B = 5 MHz) 72 dB SFDR; 66 dB SNR (fi = 175 MHz; B = Nyquist) High-speed sampling rate up to 80 Msample/s Programmable acquisition output clock (complete conversion signal) Internal front-end buffer (input capacitance below 1 pF) Full-scale controllable from 1.5 V to 2 V (p-p); continuous scale Single 5 V power supply 3.3 V LVCMOS compatible digital outputs Binary or two’s-complement LVCMOS outputs CMOS compatible static digital inputs Only 2 clock cycles latency Industrial temperature range from −40 °C to +85 °C HTQFP48 package. TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) 3. Applications ■ ■ ■ ■ ■ 2.5G and 3G cellular base infrastructure radio transceivers Wireless access systems Fixed telecommunication Optical networking WLAN infrastructure. 4. Ordering information Table 1: Ordering information Type number TDA9910HW/6 Package Name Description Version Sampling frequency (Msample/s) HTQFP48 plastic thermal enhanced thin quad flat package; 48 leads; body 7 × 7 × 1 mm; exposed die pad SOT545-2 60 TDA9910HW/8 80 5. Block diagram CLK CLKN TDA9910 2 CLOCK DRIVER DEL0 to DEL1 CCS 12 LATCH 12 D0 to D11 front-end buffer IN INN OTC TRACK AND HOLD RESISTOR LADDERS ADC CORE VCCO U/I IR LATCH FSIN FSOUT VREF REFERENCE CMADC REFERENCE OUTPUTS ENABLE 001aaa511 CMADC DEC CE_N Fig 1. Block diagram. 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 2 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) 6. Pinning information 37 CCS 38 DGND1 39 CLKN 40 CLK 41 VCCD1(5V0) 42 DGND1 43 AGND2 44 VCCA2(5V0) 45 VCCA1(5V0) 46 AGND1 47 VCCA1(5V0) 48 AGND1 6.1 Pinning n.c. 1 36 D0 AGND1 2 35 D1 IN 3 34 D2 CMADC 4 33 D3 INN 5 32 D4 AGND1 6 DEC 7 n.c. 8 29 D7 FSOUT 9 28 D8 31 D5 TDA9910HW FSIN 10 30 D6 27 D9 DGND n.c. 11 26 D10 n.c. 12 IR 24 VCCO(3V3) 23 OGND 22 VCCO(3V3) 21 OGND 20 OTC 19 CE_N 18 DGND2 17 VCCD2(5V0) 16 DEL0 15 n.c. 13 DEL1 14 25 D11 001aaa512 Fig 2. Pin configuration. 6.2 Pin description Table 2: Symbol Pin description Pin Type [1] Description n.c. 1 - not connected AGND1 2 G analog ground 1 IN 3 I analog input voltage CMADC 4 O regulator common mode ADC output INN 5 I complementary analog input voltage AGND1 6 G analog ground 1 DEC 7 I/O decoupling node n.c. 8 - not connected FSOUT 9 O full-scale reference voltage output FSIN 10 I full-scale reference voltage input n.c. 11 - not connected n.c. 12 - not connected n.c. 13 - not connected DEL1 14 I complete conversion signal delay input 1 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 3 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) Table 2: Pin description …continued Symbol Pin Type [1] Description DEL0 15 I complete conversion signal delay input 0 VCCD2(5V0) 16 P digital supply voltage 2 (5.0 V) DGND2 17 G digital ground 2 CE_N 18 I chip enable input (CMOS level; active LOW) OTC 19 I control input for two’s complement output (active HIGH) OGND 20 G data output ground VCCO(3V3) 21 P data output supply voltage (3.3 V) OGND 22 G data output ground VCCO(3V3) 23 P data output supply voltage (3.3 V) IR 24 O in-range output D11 25 O data output bit 11 (MSB) D10 26 O data output bit 10 D9 27 O data output bit 9 D8 28 O data output bit 8 D7 29 O data output bit 7 D6 30 O data output bit 6 D5 31 O data output bit 5 D4 32 O data output bit 4 D3 33 O data output bit 3 D2 34 O data output bit 2 D1 35 O data output bit 1 D0 36 O data output bit 0 (LSB) CCS 37 O complete conversion signal output DGND1 38 G digital ground 1 CLKN 39 I complementary clock input CLK 40 I clock input VCCD1(5V0) 41 P digital supply voltage 1 (5.0 V) DGND1 42 G digital ground 1 AGND2 43 G analog ground 2 VCCA2(5V0) 44 P analog supply voltage 2 (5.0 V) VCCA1(5V0) 45 P analog supply voltage 1 (5.0 V) AGND1 46 G analog ground 1 VCCA1(5V0) 47 P analog supply voltage 1 (5.0 V) AGND1 48 G analog ground 1 DGND exposed G die pad [1] digital ground P: power supply; G: ground; I: input; O: output. 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 4 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) 7. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Min Max Unit analog supply voltage [1] −0.5 +7.0 V VCCD digital supply voltage [1] −0.5 +7.0 V VCCO output supply voltage [2] −0.5 +5.0 V ∆VCC supply voltage difference VCCA − VCCD −1.0 +1.0 V VCCD − VCCO −1.0 +4.0 V VCCA − VCCO −1.0 +4.0 V VCCA VIN, VINN Parameter Conditions input voltage referenced to AGND 0 VCCA + 1 V VCLK, VCLKN input voltage for differential clock drive referenced to DGND 0 VCCD + 1 V IO output current - <tbd> mA Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C Tj junction temperature - 150 °C [1] The supply voltages VCCA and VCCD may have any value between −0.5 V and +7.0 V provided that the supply voltage differences ∆VCC are respected. [2] The supply voltage VCCO may have any value between −0.5 V and +5.0 V provided that the supply voltage differences ∆VCC are respected. 8. Thermal characteristics Table 4: Symbol Thermal characteristics Parameter Conditions Rth(j-a) thermal resistance from junction to ambient [1] Rth(j-c) thermal resistance from junction to case [1] [1] Typ Unit 36.2 K/W 14.3 K/W In compliance with JEDEC test board, in free air. 9. Characteristics Table 5: Characteristics VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to +85 °C; VIN(p-p) − VINN(p-p) = 2.0 V − 0.5 dB; VFSIN = VCCA1 − 1.77 V; Vi(CM) = VCCA1 − 1.85 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test [1] Min Typ Max Unit Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 2.7 3.3 3.6 V 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 5 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) Table 5: Characteristics …continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to +85 °C; VIN(p-p) − VINN(p-p) = 2.0 V − 0.5 dB; VFSIN = VCCA1 − 1.77 V; Vi(CM) = VCCA1 − 1.85 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test [1] Min Typ Max Unit ICCA analog supply current - 122 - mA ICCD digital supply current - 52 - mA ICCO output supply current fCLK = 80 Msample/s; fi = 175 MHz - 29 - mA Ptot total power dissipation fCLK = 80 Msample/s; DC input - 870 - mW PECL mode 3.19 - 3.52 V TTL mode DGND - 0.8 V PECL mode 3.83 - 4.12 V TTL mode 2.0 - VCCD V 20 - - µA VCLK or VCLKN = 2.00 V 1 - - nA VCLK or VCLKN = 3.83 V - - 30 µA VCLK or VCLKN = 0.80 V - - 2 nA Clock inputs: pins CLK and CLKN [2] VIL VIH IIL IIH LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current referenced to DGND; VCCD = 5 V referenced to DGND; VCCD = 5 V VCLK or VCLKN = 3.52 V D ∆VCLK differential AC input voltage for switching (VCLK − VCLKN) AC mode; DC voltage level is 2.5 V - 1.5 - V Ri input resistance fCLK = 80 Msample/s - 6.3 - kΩ Ci input capacitance fCLK = 80 Msample/s - 1.1 - pF Analog inputs: pins IN and INN IIL LOW-level input current VFSIN = VCCA − 1.75 V - 5 - µA IIH HIGH-level input current VFSIN = VCCA − 1.75 V - 5 - µA Ri input resistance fi = 21.4 MHz D 6.3 - - MΩ fi = 93 MHz D 6.3 - - MΩ fi = 175 MHz D 6.3 - - MΩ fi = 21.4 MHz D - - 700 fF fi = 93 MHz D - - 700 fF fi = 175 MHz D 700 Ci Vi(CM) input capacitance common mode input voltage VIN = VINN; output code = 2047 - - VCCA − 2 VCCA − 1.85 VCCA − 1.6 V fF - 0.3 × VCCD V VCCD V Digital inputs: pins OTC and CE_N VIL LOW-level input voltage DGND VIH HIGH-level input voltage 0.7 × VCCD - 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 6 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) Table 5: Characteristics …continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to +85 °C; VIN(p-p) − VINN(p-p) = 2.0 V − 0.5 dB; VFSIN = VCCA1 − 1.77 V; Vi(CM) = VCCA1 − 1.85 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions IIL LOW-level input current VIL = 0.8 V IIH HIGH-level input current VIH = 2.0 V Test [1] Min Typ Max Unit - 5 - µA - 5 - µA DGND - 0.3 × VCCD V Digital inputs: pins DEL0 and DEL1 VIL LOW-level input voltage VIH HIGH-level input voltage 0.7 × VCCD - VCCD V IIL LOW-level input current VIL = 0.8 V - 80 - µA IIH HIGH-level input current VIH = 2.0 V - 80 - µA IL = 0 mA - VCCA − 1.88 - V IL = 2 mA - VCCA − 1.91 - V - VCCA − 1.84 - V Voltage controlled regulator output: pin CMADC Vo(CM) common mode output voltage Reference voltage input: pin FSIN [3] VFSIN full-scale fixed voltage IFSIN input current Vi(p-p) input voltage (peak-to-peak value) - 1 - µA 1.5 1.9 2.0 V IL = IFSIN - VCCA − 1.84 - V IL = 2 mA - VCCA − 1.87 - V DGND - DGND + 0.5 V see Figure 5; Vi = VIN − VINN; Vi(CM) = VCCA − 1.91 V Full-scale voltage controlled regulator output: pin FSOUT Vo(ref) 1.9 V full-scale output voltage Digital outputs: pins D11 to D0, IR and CCS Output levels VOL LOW-level output voltage IOL = 2 mA VOH HIGH-level output voltage IOH = −0.4 mA VCCO − 0.5 - VCCO V IOZ output current in 3-state output level between 0.5 V and VCCO −20 1 +20 µA td(s) sampling delay time CL = 10 pF - 0.2 - ns th(o) output hold time CL = 10 pF - 4 - ns td(o) output delay time CL = 10 pF - 5 - ns Timing [4] 3-state output delay tdZH enable HIGH - 3 - ns tdZL enable LOW - 5 - ns tdHZ disable HIGH - 8 - ns tdLZ disable LOW - 5 - ns - - 8 Msample/s 80 - - Msample/s Clock timing inputs: pins CLK and CLKN fCLK(min) minimum clock frequency fCLK(max) maximum clock frequency duty cycle 45 % to 65 % tCLKH clock pulse width HIGH fi = 175 MHz 5.6 - - ns tCLKL clock pulse width LOW fi = 175 MHz 5.6 - - ns 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 7 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) Table 5: Characteristics …continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to +85 °C; VIN(p-p) − VINN(p-p) = 2.0 V − 0.5 dB; VFSIN = VCCA1 − 1.77 V; Vi(CM) = VCCA1 − 1.85 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test [1] Min Typ Max Unit Timing complete conversion signal: pin CCS; see Figure 6 tcd(o) complete conversion signal delay time CL = 10 pF; DEL0 = LOW; DEL1 = HIGH - 0.2 - ns CL = 10 pF; DEL0 = HIGH; DEL1 = LOW - 1.3 - ns CL = 10 pF; DEL0 = HIGH; DEL1 = HIGH - 2.4 - ns Analog signal processing (clock duty cycle 50 %; VIN − VINN = 1.9 V; Vref = VCCA3 − 1.75 V) INL integral non-linearity fCLK = 20 Msample/s; fi = 21.4 MHz - ±1.6 - LSB DNL differential non-linearity fCLK = 20 Msample/s; fi = 21.4 MHz; no missing code guaranteed - ±0.4 - LSB Eoffset offset error VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 °C; output code = 2047 - 5 - mV EG gain error amplitude (spread from device to device) VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 °C - 0.8 - %FS B analog bandwidth [5] fCLK = 80 Msample/s; −3 dB; full-scale input - 370 - MHz THD total harmonic distortion TDA9910/6 [6] fi = 21.4 MHz - −74 - dBFS fi = 93 MHz - −72 - dBFS fi = 175 MHz - −72 - dBFS total harmonic distortion TDA9910/8 [6] fi = 21.4 MHz - −76 - dBFS fi = 93 MHz - −74 - dBFS fi = 175 MHz - −70 - dBFS fi = 21.4 MHz - 67.5 - dBc fi = 93 MHz - 67.2 - dBc fi = 175 MHz - 66.5 - dBc fi = 21.4 MHz - 67 - dBc fi = 93 MHz - 66.7 - dBc fi = 175 MHz - 66 - dBc SNR signal-to-noise ratio TDA9910/6 [7] signal-to-noise ratio TDA9910/8 [7] 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 8 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) Table 5: Characteristics …continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to +85 °C; VIN(p-p) − VINN(p-p) = 2.0 V − 0.5 dB; VFSIN = VCCA1 − 1.77 V; Vi(CM) = VCCA1 − 1.85 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions SFDR fi = 21.4 MHz fi = 93 MHz spurious free dynamic range TDA9910/6 spurious free dynamic range TDA9910/8 ACPR d2(IM2) d3(IM3) adjacent channel power rejection second order intermodulation distortion [8] third order intermodulation distortion [8] Test [1] Min Typ Max Unit - 76 - dBc - 73 - dBc fi = 175 MHz - 73 - dBc fi = 21.4 MHz - 79 - dBc fi = 93 MHz - 75 - dBc fi = 175 MHz - 72 - dBc fi = 93 MHz; 5 MHz channel spacing; B = 4.096 MHz - 86 - dB fi = 175 MHz; 5 MHz channel spacing; B = 4.096 MHz - 74 - dB fi1 = 21 MHz; fi2 = 22 MHz - −81 - dBFS fi1 = 93 MHz; fi2 = 96 MHz - −83 - dBFS fi1 = 174 MHz; fi2 = 176 MHz - −80 - dBFS fi1 = 21 MHz; fi2 = 22 MHz - −87 - dBFS fi1 = 93 MHz; fi2 = 96 MHz - −88 - dBFS fi1 = 174 MHz; fi2 = 176 MHz - −83 - dBFS [1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. [2] The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation: a) PECL mode 1: (DC levels vary 1:1 with VCCD) CLK and CLKN inputs are at differential PECL levels. b) PECL mode 2: (DC levels vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC levels vary 1:1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF capacitor. e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has to be connected to the ground. [3] The ADC input range can be adjusted with an external reference connected to FSIN pin. This voltage has to be referenced to VCCA. [4] Output data acquisition: the output data is available after the maximum delay of td(o). [5] The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. [6] The total harmonic distortion is obtained with the addition of the first five harmonics. [7] The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency. 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 9 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) [8] Intermodulation measured relative to either tone with analog input frequencies fi1 and fi2. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (−6 dB below full-scale for each input signal). d3(IM3) is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product; d2(IM2) is the ratio of the RMS value of either input tone to the RMS value of the worst case second order intermodulation product. Table 6: Output coding with differential inputs VIN(p-p) − VINN(p-p) = 1.9 V; VFSIN = VCCA1 − 1.77 V; typical values to AGND. Code VIN(p-p) (V) VINN(p-p) (V) IR Binary outputs (D11 to D0) Two’s complement outputs (D11 to D0) Underflow < 2.675 > 3.625 0 0000 0000 0000 1000 0000 0000 0 2.675 3.625 1 0000 0000 0000 1000 0000 0000 1 - - 1 0000 0000 0001 1000 0000 0001 ... ... ... ... ... ... 2047 3.15 3.15 1 0111 1111 1111 1111 1111 111 ... ... ... ... ... ... 4094 - - 1 1111 1111 110 0111 1111 110 4095 3.625 2.675 1 1111 1111 111 0111 1111 111 Overflow > 3.625 < 2.675 0 1111 1111 111 0111 1111 111 Table 7: Mode selection Two’s complement output (OTC) Chip enable input (CE_N) Data output (D0 to D11; IR) 0 0 binary; active 1 0 two’s complement; active X [1] 1 high-impedance [1] X = don’t care. CLK n 50 % td(o) data n−1 D0 to D11 data n VCCO − 0.5 V data n+1 0.5 V th(o) td(s) IN sample n sample n+1 sample n+2 sample n+3 sample n+4 001aaa513 Fig 3. Output timing diagram. 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 10 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) 001aaa514 0 (1) power spectrum (dBc) −40 (2) −80 (3) (4) (5) (6) −120 −160 0 10 20 30 40 fi (MHz) (1) fi = 15 MHz; 0 dBc (2) fi = 5.1 MHz; −73.64 dBc (3) fi = 9.88 MHz; −82.6 dBc (4) fi = 20.1 MHz; −77.26 dBc (5) fi = 30 MHz; −71.73 dBc (6) fi = 35.1 MHz; −71.68 dBc THD (5H): 66.93 dBc SFDR: −71.68 dBc Fig 4. Single tone; fi = 175 MHz; fCLK = 80 Msample/s. 001aaa515 2.2 Vi(CM) (V) (3) 2.0 (2) 1.8 1.6 (1) 1.4 1.5 1.6 1.7 1.8 1.9 2.0 VCCA − VFSIN (V) (1) Vi(CM) = 1.54 V; VCCA − VFSIN = 1.5 V (2) Vi(CM) = 1.9 V; VCCA − VFSIN = 1.84 V (3) Vi(CM) = 2.07 V; VCCA − VFSIN = 2.0 V Fig 5. ADC full-scale; Vi(CM) as a function of VCCA − VFSIN. 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 11 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) The TDA9910 allows to modify the ADC full-scale. This could be done with FSIN (full-scale input) according to Figure 5. The TDA9910 generates an adjustable clock output called Complete Conversion Signal (CCS), which can be used to control the acquisition of converted output data by the digital circuit connected to the TDA9910 output data bus. Two logic inputs, DEL0 and DEL1 pins, allow to adjust the delay of the edge of the CCS signal to achieve an optimal position in the stable, usable zone of the data. Table 8: Complete conversion signal selection DEL1 DEL0 CCS output 0 0 high-impedance 0 1 active, typical delay 0.2 ns 1 0 active, typical delay 1.3 ns 1 1 active, typical delay 2.4 ns (1) D0 to D11 tcd(o) CCS 001aaa516 (1) tcd(o) is referenced to the middle of the active data. Fig 6. Complete conversion signal timing diagram. 10. Definitions 10.1 Static parameters 10.1.1 INL (integral non-linearity) It is defined as the deviation of the transfer function from a best fit straight line (linear regression computation). The INL of the code i is obtained from the equation: V I ( i ) – V I ( ideal ) INL ( i ) = -----------------------------------------S where: S is corresponding to the slope of the ideal straight line (code width); i is corresponding to the code value. 10.1.2 DNL (differential non-linearity) It is the deviation in code width from the value of 1 LSB. V I (i + 1) – V I (i) DNL ( i ) = ---------------------------------------S 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 12 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) where: n i = 0x ( 2 – 2 ) 10.2 Dynamic parameters Figure 7 shows the spectrum of a single tone full-scale input sine wave with frequency ft, conforming to coherent sampling (ft/fs = M/N, with M number of cycles and N number of samples, M and N being relatively prime), and digitized by the ADC under test. 001aaa518 magnitude a1 SFDR a3 ak a2 measured output range (MHz) fs/2 Fig 7. Single tone spectrum of full-scale input sine wave with frequency ft. Remark: In the following equations, Pnoise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and “quantization noise”. 10.2.1 SINAD (signal-to-noise and distortion) The ratio of the output signal power to the noise plus distortion power for a given sample rate and input frequency, excluding the DC component: P signal SINAD [ dB ] = 10log 10 ---------------------------------------- P noise + distortion 10.2.2 ENOB (effective number of bits) It is derived from SINAD and gives the theoretical resolution an ideal ADC would require to obtain the same SINAD measured on the real ADC. A good approximation gives: SINAD – 1.76 ENOB = ---------------------------------6.02 10.2.3 THD (total harmonic distortion) The ratio of the power of the harmonics to the power of the fundamental. For k − 1 harmonics the THD is: 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 13 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) P harmonics THD [ dB ] = 10log 10 ------------------------- P signal where: 2 2 2 P harmonics = a 2 + a 3 + … + a k 2 P signal = a 1 The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics). 10.2.4 SNR (signal-to-noise ratio) The ratio of the output signal power to the noise power, excluding the harmonics and the DC component is: P signal SNR [ dB ] = 10log 10 ---------------- P noise 10.2.5 SFDR (spurious free dynamic range) The number SFDR specifies available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious harmonic and non-harmonic, excluding DC component: a1 SFDR [ dB ] = 20log 10 ------------------ max ( S ) 10.2.6 IMD2 (IMD3) 001aaa527 magnitude IMD3 measured output range (MHz) fs/2 Fig 8. Spectral of dual tone input sine wave with frequency. 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 14 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) From a dual tone input sinusoid (ft1 and ft2, these frequencies being chosen according to the coherence criterion), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd order components) are defined, as follows. The ratio of the RMS value of either tone to the RMS value of the worst second (third) order intermodulation product. The total intermodulation distortion IMD is given by: P intermod IMD [ dB ] = 10log 10 ---------------------- P signal where: 2 P intermod = a im ( f t1 – f t2 ) 2 – a im ( f + f t2 ) + a im ( f t1 – f t2 ) + a im ( 2 f 2 … + a im ( 2 f 2 with a im ( f t1 ) 2 t1 t1 – 2 f t2 ) 2 t1 t1 + 2 f t2 ) +… + f t2 ) corresponding to the power in the intermodulation component at frequency ft. 2 2 P signal = a f + a f t1 t2 9397 750 14418 Objective data sheet 2 + a im ( f © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 15 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) 11. Application information 11.1 TDA9910 in 3G radio receivers The TDA9910 has been proven in many 3G radio receivers with various operating conditions regarding Input Frequency (IF), signal IF bandwidth and sampling frequency. The TDA9910 provides with a maximum analog input signal frequency of 400 MHz. It allows a significant cost-down of the RF front-end, from two mixers to only one, even in multi-carriers architecture. Table 9 describes some possible applications with the TDA9910 in high IF sampling mode. Table 9: Examples of possible fi, fCLK, IF BW combinations supported fi (MHz) fCLK (Msample/s) IF BW (MHz) [1] SNR (dB) SFDR (dBc) 350 80 5.00 65 71 243.95 9.60 0.25 71 80 96 76.80 1.60 72 76 96 76.80 4.80 71 77 96 76.80 20.00 68 76 80 61.44 10.00 70 85 78.4 44.80 3.50 71 76 70 40.00 1.25 72 79 [1] IF bandwidth corresponds to the observed area on the ADC output spectrum. For a dual carrier W-CDMA receiver, the most important parameters are sensitivity and Adjacent Channel Selectivity (ACS). The sensitivity is defined as the lowest detectable signal level. In W-CDMA, it can be far below the noise floor. This difference, between the sensitivity and the noise floor, is defined by the Sensitivity-to-Noise Ratio (SENR). Its value is negative due to the gain processing. The Adjacent Channel Power Ratio (ACPR) is the difference between the full-scale −3 dB peak and the noise floor. It represents the ratio of the adjacent-channel power and the average power level of the channel. The ACS is defined by the sum of SENR and ACPR. interfering channel wanted channel ACS ACPR noise floor NF SENR sensibility thermal noise 001aaa517 Fig 9. Adjacent channel sensitivity and ADC sensibility. 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 16 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) 11.2 Application diagram ADT1_1WT 100 nF 6 3 2 5 4 1 CLK n.c. VCCD VCCA 47 46 45 44 43 42 41 40 39 VCCD1 TL431CPK 100 nF CCS DGND1 CLKN CLK VCCD1(5V0) DGND1 AGND2 VCCA2(5V0) VCCA1(5V0) AGND1 AGND1 VCCA1(5V0) 2.2 kΩ 48 50 Ω 37 38 330 nF AGND1 100 Ω DEC 10 nF n.c. 100 nF FSOUT FSIN n.c. n.c. 34 4 33 5 32 6 D1 D2 D3 D4 D5 31 TDA9910HW 7 D0 D6 30 D7 29 8 9 10 27 11 26 12 25 14 DEL1 n.c. 13 15 10 nF 16 17 D8 28 DGND 18 19 20 21 22 23 VCCD D9 D10 D11 24 G1 IR INN 3 OGND 4 35 VCCO(3V3) 1 CMADC 2 VCCO(3V3) 2 IN OTC IN 5 100 Ω OGND 100 nF 6 36 CE_N n.c. 3 1 DGND2 AGND1 DEL0 ADT1_1WT VCCD2(5V0) n.c. VCCO VCCD 4700_000_S (16) (41) analog ground 10 nF 100 nF 330 nF digital ground 10 nF VCCA 4700_000_S (44) 100 nF 330 nF (45) (47) 10 nF 10 nF 10 nF HF70ACB 5V xx 10 V GND IN xx 4.7 µF 470 nF LM317MDT 3 2 1 ADJ VCCO (21) OUT 240 Ω 100 nF (23) 10 nF 10 nF 300 Ω coa002 Fig 10. Application diagram. 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 17 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) 12. Package outline HTQFP48: plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1 mm; exposed die pad SOT545-2 c y exposed die pad side X Dh 36 25 A 24 37 ZE e E HE Eh (A 3) A A2 A1 w M θ bp Lp L pin 1 index 13 48 detail X 1 12 ZD w M bp v M A e D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 A2 A3 bp c D(1) Dh E(1) Eh e HD HE L Lp v w y 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 7.1 6.9 4.6 4.4 7.1 6.9 4.6 4.4 0.5 9.1 8.9 9.1 8.9 1 0.75 0.45 0.2 0.08 0.08 ZD(1) ZE(1) 0.9 0.6 0.9 0.6 θ 7° 0° Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT545-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 03-04-07 04-01-29 MS-026 Fig 11. Package outline SOT545-2 (HTQFP48). 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 18 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) 13. Revision history Table 10: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes TDA9910_2 20041209 Objective data sheet - 9397 750 14418 TDA9910_1 Modifications: • Four values changed in Table 5 (Clock timing inputs) 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 19 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) 14. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 15. Definitions 16. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 17. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 14418 Objective data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 02 — 9 December 2004 20 of 21 TDA9910 Philips Semiconductors 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.1.1 10.1.2 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 11 11.1 11.2 12 13 14 15 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Static parameters . . . . . . . . . . . . . . . . . . . . . . 12 INL (integral non-linearity) . . . . . . . . . . . . . . . 12 DNL (differential non-linearity) . . . . . . . . . . . . 12 Dynamic parameters. . . . . . . . . . . . . . . . . . . . 13 SINAD (signal-to-noise and distortion) . . . . . . 13 ENOB (effective number of bits) . . . . . . . . . . . 13 THD (total harmonic distortion). . . . . . . . . . . . 13 SNR (signal-to-noise ratio) . . . . . . . . . . . . . . . 14 SFDR (spurious free dynamic range) . . . . . . . 14 IMD2 (IMD3) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information. . . . . . . . . . . . . . . . . . 16 TDA9910 in 3G radio receivers. . . . . . . . . . . . 16 Application diagram . . . . . . . . . . . . . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information . . . . . . . . . . . . . . . . . . . . 20 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 9 December 2004 Document number: 9397 750 14418 Published in The Netherlands