INTEGRATED CIRCUITS DATA SHEET TDA8705A 6-bit high-speed dual Analog-to-Digital Converter (ADC) Product specification Supersedes data of November 1994 File under Integrated Circuits, IC02 1996 Jan 12 Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) TDA8705A FEATURES APPLICATIONS • 2 times 6-bit resolution High-speed analog-to-digital conversion for: • Sampling rate up to 80 MHz • DBS (Digital Broadcast Satellite) • High signal-to-noise ratio over a large analog input frequency range (5.5 effective bits at 20 MHz full-scale input at fclk = 80 MHz) • QPSK (Quadrature Phase Shift Keying) demodulation • Video. • TTL output GENERAL DESCRIPTION • Two separated inputs (AC-coupling) The TDA8705A is a 6-bit high-speed dual analog-to-digital converter (ADC) for satellite video and other applications. It converts the two analog input signals into two 6-bit binary-coded digital words at a maximum sampling rate of 80 MHz. All digital inputs and outputs are TTL compatible, although a low-level sine wave clock input signal is allowed. • TTL compatible digital inputs • Low-level AC clock input signal allowed • Internal reference voltage regulator (external reference regulation possible) • Power dissipation only 250 mW (typical) • Low analog input capacitance, no buffer amplifier required • No sample-and-hold circuit required. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 4.75 5.0 5.25 V ICCA analog supply current 20 27 32 mA ICCD digital supply current 10 14 18 mA ICCO output stages supply current 10 14 18 mA ILE DC integral linear error − ±0.25 ±0.5 LSB DLE DC differential linearity error − ±0.25 ±0.5 LSB AILE AC integral linearity error − ±0.5 ±1.0 LSB fclk(max) maximum clock frequency 80 − − MHz Ptot total power dissipation − 250 − mW note 1 Note 1. Full-scale sine wave (fi = 20 MHz; fclk = 80 MHz). ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8705AT SO28 1996 Jan 12 DESCRIPTION plastic small outline package; 28 leads; body width 7.5 mm 2 VERSION SOT136-1 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2 21 REGULATOR reference V voltage TOP RTA A analog voltage input A V IA 5 28 D5A MSB 27 D4A 6 ANALOG -TO-DIGITAL CONVERTER A 26 D3A 6 TTL OUTPUTS LATCHES 25 D2A data outputs 24 D1A R INTA reference V voltage BOTTOM RBA A 9 12 14 LSB TDA8705A R INTB 20 D5B MSB 19 D4B analog voltage input B V IB 11 ANALOG -TO-DIGITAL CONVERTER B 18 D3B 6 LATCHES TTL OUTPUTS 17 D2B data outputs 16 D1B reference V RBB voltage BOTTOM B 15 D0B 13 LSB CLOCK DRIVER AGND output ground analog ground 3 1 DGND digital ground Fig.1 Block diagram. MLC374 CLK Product specification 7 TDA8705A 22 OGND handbook, full pagewidth 3 reference voltage MIDDLE A reference V RMA voltage TOP V RTB B V RMB reference voltage MIDDLE B 23 D0A 4 Philips Semiconductors 8 V CCO 6-bit high-speed dual Analog-to-Digital Converter (ADC) 10 V CCD BLOCK DIAGRAM 1996 Jan 12 V CCA DEC Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) TDA8705A PINNING SYMBOL PIN DESCRIPTION CLK 1 clock input VCCD 2 digital supply voltage (+5 V) DGND 3 digital ground VRBA 4 reference voltage BOTTOM for ADC A (decoupling) VRTA 5 reference voltage TOP for ADC A (decoupling) VIA 6 analog input voltage for ADC A AGND 7 analog ground VCCA 8 VRMA handbook, halfpage CLK 1 28 D5A analog supply voltage (+5 V) V CCD 2 27 D4A 9 reference voltage MIDDLE for ADC A (decoupling) DGND 3 26 D3A V RBA 4 25 D2A DEC 10 decoupling input 24 D1A 11 analog input voltage for ADC B V RTA 5 VIB VRTB 12 reference voltage TOP for ADC B (decoupling) V IA 6 23 D0A AGND 7 22 OGND VCCA 8 21 V CCO V RMA 9 20 D5B DEC 10 19 D4B V IB 11 18 D3B TDA8705A VRBB 13 reference voltage BOTTOM for ADC B (decoupling) VRMB 14 reference voltage MIDDLE for ADC B (decoupling) D0B 15 data output; bit 0 (LSB), ADC B D1B 16 data output; bit 1, ADC B V RTB 12 17 D2B D2B 17 data output; bit 2, ADC B V RBB 13 16 D1B D3B 18 data output; bit 3, ADC B V RMB 14 15 D0B D4B 19 data output; bit 4, ADC B D5B 20 data output; bit 5 (MSB), ADC B VCCO 21 supply voltage for output stages (+5 V) OGND 22 output ground D0A 23 data output; bit 0 (LSB), ADC A D1A 24 data output; bit 1, ADC A D2A 25 data output; bit 2, ADC A D3A 26 data output; bit 3, ADC A D4A 27 data output; bit 4, ADC A D5A 28 data output; bit 5 (MSB), ADC A 1996 Jan 12 MLC375 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) TDA8705A LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage note 1 −0.3 +7.0 V VCCD digital supply voltage note 1 −0.3 +7.0 V VCCO output stages supply voltage note 1 −0.3 +7.0 V ∆VCC supply voltage differences between VCCA and VCCD −1.0 +1.0 V ∆VCC supply voltage differences between VCCO and VCCD −1.0 +1.0 V ∆VCC supply voltage differences between VCCA and VCCO −1.0 +1.0 V VI input voltage referenced to AGND −0.3 +7.0 V Vclk(p-p) AC input voltage for switching (peak-to-peak value) referenced to DGND − VCCD V IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature 0 +70 °C Tj junction temperature − +150 °C Note 1. The supply voltages VCCA, VCCO and VCCD may have any value between −0.3 V and +7 V provided the difference between VCCA, VCCO and VCCD is between −1 V and +1 V. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1996 Jan 12 PARAMETER thermal resistance from junction to ambient in free air 5 VALUE UNIT 70 K/W Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) TDA8705A CHARACTERISTICS VCCA = V8 to V7 = 4.75 to 5.25 V; VCCD = V2 to V3 = 4.75 to 5.25 V; VCCO = V21 to V22 = 4.75 to 5.25 V; AGND, OGND and DGND shorted together; VCCA to VCCD = −0.25 to +0.25 V; VCCO to VCCD = −0.25 to +0.25 V; VCCA to VCCO = −0.25 to +0.25 V; Tamb = 0 to +70 °C; typical values measured at VCCA = VCCD = VCCO = 5 V and Tamb = 25 °C; CL = 15 pF; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 4.75 5.0 5.25 V ICCA analog supply current 20 27 32 mA ICCD digital supply current 10 14 18 mA ICCO output stages supply current 10 14 18 mA Inputs CLOCK INPUT CLK; REFERENCED TO DGND; note 1 VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VCCD V IIL LOW level input current −1 − +1 µA IIH HIGH level input current Vclk = 2.7 V − − 20 µA ZI input impedance fclk = 80 MHz − 2 − kΩ CI input capacitance fclk = 80 MHz − 2 − pF 20 − − kΩ Vclk = 0.4 V VI ANALOG INPUT VOLTAGE FOR A AND B; REFERENCED TO AGND RI DC parallel input resistance CI parallel input capacitance fi = 20 MHz − 1.5 − pF αCT crosstalk between VIA and VIB fi = 20 MHz 40 − − dB Reference voltages for the resistor ladder (A and B); see Table 1 VRB reference voltage BOTTOM 1.9 2.0 2.1 V VRT reference voltage TOP 2.8 2.9 3.0 V Vdiff differential reference voltage VRT − VRB 0.85 0.90 0.95 V Iref reference current − 2 − mA RLAD resistor ladder − 450 − Ω TCRLAD temperature coefficient of the resistor ladder − 3280 − ppm VosB offset voltage BOTTOM note 2 − 200 − mV VosT offset voltage TOP note 2 − 200 − mV Vi(p-p) input voltage amplitude (peak-to-peak value) 0.45 0.50 0.55 V Outputs (A and B) DIGITAL OUTPUTS D5 TO D0 (REFERENCED TO DGND) VOL LOW level output voltage IO = 1 mA 0 − 0.4 V VOH HIGH level output voltage IO = −1 mA 2.4 − VCCD V 1996 Jan 12 6 Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) SYMBOL PARAMETER TDA8705A CONDITIONS MIN. TYP. MAX. UNIT Switching characteristics CLOCK INPUT CLK; note 1; see Fig.3 fclk(max) maximum clock frequency 80 − − MHz tCPH clock pulse width HIGH 5.5 − − ns tCPL clock pulse width LOW 5.5 − − ns Analog signal processing LINEARITY ILE DC integral linearity error − ±0.25 ±0.5 LSB DLE DC differential linearity error − ±0.25 ±0.5 LSB AILE AC integral linearity error note 3 − ±0.5 ±1.0 LSB OFE offset error between A and B fi = 10 MHz; ±1 fclk = 40 MHz; note 4 − ±2 LSB GE gain error between A and B ±1 fi = 10 MHz; fclk = 40 MHz; note 4 − ±2 LSB MID middle scale output code (A and B) 31 − 32 BANDWIDTH; fclk = 80 MHz B −0.5 dB analog bandwidth full-scale sine wave; note 5 − 50 − MHz tSTLH analog input settling time LOW-to-HIGH full-scale square wave; Fig.4; note 6 − 8 − ns tSTHL analog input settling time HIGH-to-LOW full-scale square wave; Fig.4; note 6 − 5 − ns − − 0 dB second harmonics − −45 − dB third harmonics − −41 − dB fi = 20 MHz − −39 −34 dB without harmonics; fclk = 80 MHz; fi = 20 MHz 33 36 − dB fi = 10 MHz − 5.7 − bits fi = 20 MHz − 5.5 − bits fi = 30 MHz − 5.1 − bits HARMONICS; fclk = 40 MHZ; see Fig.5 h1 fundamental harmonics (full scale) fi = 20 MHz hall harmonics (full scale); all components fi = 20 MHz THD total harmonic distortion SIGNAL-TO-NOISE RATIO; note 7; see Fig.5 S/N signal-to-noise ratio (full scale) EFFECTIVE BITS; note 7; see Fig.5 EB effective bits 1996 Jan 12 fclk = 80 MHz 7 Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) SYMBOL PARAMETER TDA8705A CONDITIONS MIN. TYP. MAX. UNIT TWO-TONE; note 8 TTIR two-tone intermodulation rejection fclk = 80 MHz − 48 − dB fclk = 80 MHz; fi = 20 MHz; VI = ±16 LSB at code 32 − 10−12 − times/ samples − − 2 ns BIT ERROR RATE BER bit error rate Timing (fclk = 80 MHz; CL = 15 pF); note 9; see Fig.3 tds sampling delay time th output hold time 5 − − ns td output delay time − − 11 ns Notes 1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. 2. Analog input voltages producing code 00 up to and including 3F: a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and the reference voltage BOTTOM (VRB) at Tamb = 25 °C. b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which produces data outputs equal to 3F at Tamb = 25 °C. 3. Full-scale sine wave (fi = 20 MHz; fclk = 80 MHz). 4. The Offset Error (OFE) and Gain Error (GE) are determined by taking results from a simultaneous acquisition on both ADCs of a sine wave greater than full-scale. The occurrences of code 0 and 63 are used to calculate the OFE (mid-scale-to-mid-scale) and the GE (amplitude difference) between the two converters A and B. 5. The −0.5 dB analog bandwidth is determined by the 0.5 dB reduction in the reconstructed output, the input being a full-scale sine wave. It is determined with a beat frequency method; no glitches occurrence. 6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data. 7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB. 8. Intermodulation measured relative to either tone with analog input frequencies of 20.0 MHz and 20.1 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter. 9. Output data acquisition: the output data is available after the maximum delay time of td. 1996 Jan 12 8 Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) Table 1 TDA8705A Output coding and input voltage (typical values; referenced to AGND) BINARY OUTPUT BITS STEP VI(p-p) A or B (V) D5 D4 D3 D2 D1 D0 <2.2 0 0 0 0 0 0 0 2.2 0 0 0 0 0 0 1 2.208 0 0 0 0 0 1 . . . . . . . . Underflow . . . . . . . . 62 2.692 1 1 1 1 1 0 63 2.7 1 1 1 1 1 1 Overflow >2.7 1 1 1 1 1 1 t CPL handbook, full pagewidth t CPH 1.4 V CLK sample N sample N + 1 sample N + 2 Vl(n) t ds th 2.4 V DATA D0 to D5 DATA N-2 DATA N-1 DATA N DATA N+1 1.4 V 0.4 V td MLC115 Fig.3 Timing diagram for data output. t STHL t STLH handbook, full pagewidth code 63 V I(n) 50 % 50 % code 0 2 ns 2 ns CLK MLC116 50 % 50 % 0.5 ns Fig.4 Analog input settling-time diagram. 1996 Jan 12 9 0.5 ns Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) TDA8705A MLC376 0 handbook, full pagewidth amplitude (dB) 20 40 60 80 100 120 40.2 45.2 50.2 55.2 60.3 65.3 70.3 Effective bits: 5.54; THD = −39.89 dB; Harmonic levels (dB): 2nd = −46.51; 3rd = −41.21; 4th = −80.65; 5th = −60.16; 6th = −54.51. Fig.5 Typical Fast Fourier Transform (fclk = 80 MHz; fi = 20 MHz). 1996 Jan 12 10 75.3 f (MHz) 80.4 Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) TDA8705A APPLICATION INFORMATION 100 nF CLK handbook, full pagewidth V CCD 5V DGND input A 100 nF V RBA 100 nF V RTA C LA (1) V IA AGND 5V input B VCCA 100 nF 100 nF V RMA 1 nF (2) DEC C LB (1) V IB 100 nF V RTB 100 nF V RBB 100 nF V RMB 1 28 2 27 3 26 4 25 5 24 6 23 7 22 D5A D4A D3A D2A TDA8705A 8 21 9 20 10 19 11 18 12 17 13 16 14 15 D1A D0A OGND V CCO 5V D5B D4B 100 nF D3B D2B D1B D0B MLC377 The analog and digital supplies should be separated and decoupled. VRT(n), VRM(n) and VRB(n) and DEC inputs are decoupled to AGND. (1) In the event of AC-coupling, CLA and CLB values are chosen in accordance with the classical low frequencies cut-off formulae 1 f CL = -------------------------------------- where input resistance RI is the value measured under DC conditions. 2 × π × RI × CL In the event of DC-coupling, CLA and CLB capacitors are omitted. The DC biassing and AC modulation signal directly applied to inputs (pin 6 and 11), must be in the range of VRT(n) − VRB(n). (2) When pin 10 (DEC) is short-circuited to AGND, an external regulator can be connected to VRT(n) and VRB(n). Fig.6 Application diagram. 1996 Jan 12 11 Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) TDA8705A PACKAGE OUTLINE SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 D E A X c y HE v M A Z 15 28 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 e bp 0 detail X w M 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.71 0.69 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT136-1 075E06 MS-013AE 1996 Jan 12 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 12 Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) TDA8705A SOLDERING Wave soldering Introduction Wave soldering techniques can be used for all SO packages if the following conditions are observed: There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all SO packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 1996 Jan 12 13 Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) TDA8705A DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Jan 12 14 Philips Semiconductors Product specification 6-bit high-speed dual Analog-to-Digital Converter (ADC) NOTES 1996 Jan 12 15 TDA8705A Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. (31)40-2788399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. 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(02)92 0601 Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 © Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1100/02/pp16 Document order number: Date of release: 1996 Jan 12 9397 750 00569