TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Rev. 01 — 15 December 2005 Product data sheet 1. General description The TZA3012HW is a fully integrated optical network receiver containing a dual limiter, data and clock recovery and demultiplexer with demultiplexing ratios of 1 : 16, 1 : 10, 1 : 8, or 1 : 4. The A-rate feature allows the IC to operate at any bit rate between 30 Mbit/s and 3.2 Gbit/s using a single reference frequency. The receiver supports loop modes with serial clock and data inputs and outputs. All clock signals are generated using a fractional N synthesizer with 10 Hz resolution giving a true, continuous rate operation. For full configuration flexibility, the receiver can be configured by pin or via the I2C-bus. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. 2. Features 2.1 General ■ Single 3.3 V supply voltage ■ I2C-bus and pin configured fiber-optic receiver 2.2 Dual limiter ■ ■ ■ ■ Dual limiting input with 12 mV sensitivity Received Signal Strength Indicator (RSSI) Loss-Of-Signal (LOS) indicator with threshold adjust Differential overvoltage protection 2.3 Data and clock recovery ■ Supports SHD/SONET bit rates at 155.52 Mbit/s, 622.08 Mbit/s, 2488.32 Mbit/s and 2666.06 Mbit/s (STM16/OC48 + FEC) ■ Supports Gigabit Ethernet at 1250 Mbit/s and 3125 Mbit/s ■ Supports Fiber Channel at 1062.5 Mbit/s and 2125 Mbit/s ■ ITU-T compliant jitter tolerance ■ Frequency lock indicator ■ Stable clock signal when input data absent ■ Outputs for recovered data and clock loop mode TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 2.4 Demultiplexer ■ Demultiplexing ratios of 1 : 16, 1 : 10, 1 : 8 or 1 : 4 ■ Low Voltage Positive Emitter Coupled Logic (LVPECL) or Common Mode Logic (CML) demultiplexer outputs ■ Parity bit generation ■ Loop mode inputs to demultiplexer 2.5 Additional features with I2C-bus ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ A-rate supports any bit rate from 30 Mbit/s to 3.2 Gbit/s with one reference frequency Programmable frequency resolution of 10 Hz Four reference frequency ranges Adjustable swing of data, clock and parallel outputs Programmable polarity of all RF I/Os Exchangeable pin designations of RF clock with data for all I/Os for optimum connectivity Reversible pin designations of parallel data bus bits for optimum connectivity Slice level adjustment to improve Bit Error Rate (BER) Mute function for a forced logic 0 output state Programmable parity 3. Applications ■ ■ ■ ■ Any optical transmission system with bit rates between 30 Mbit/s and 3.2 Gbit/s Physical interface IC in receive channels Transponder applications Dense Wavelength Division Multiplexing (DWDM) systems 4. Ordering information Table 1: Ordering information Type number TZA3012HW Package Name Description Version HTQFP100 plastic thermal enhanced thin quad flat package; 100 leads; body 14 × 14 × 1 mm; exposed die pad SOT638-1 TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 2 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 5. Block diagram CLOOP DMXR0 DLOOPQ CLOOPQ LOS1 RSSI1 LOSTH1 5 6 7 DLOOP 87 DMXR1 ENLINQ 88 84 85 91 30 31 38 39 PARITY PARITYQ LOS RSSI INSEL IN1 IN1Q 12 TZA3012HW 9 c LIM 10 DMX 1 : 4 16 1:8 1 : 10 1 : 16 d SWITCH PHASE 2 DETECTOR 16 d PARITY GENERATOR AND BUS SWAP c IN2 LIM 17 16 16 44, 46, 48, 53 55, 57, 59, 61, 64, 66, 68, 70 72, 77, 79, 81 45, 47, 49, 54 56, 58, 60, 62, 65, 67, 69, 71 73, 78, 80, 82 2 IN2Q 41 42 2 LPF 2 94 95 RSSI LOS LOSTH2 SCL(DR2) SDA(DR1) CS(DR0) UI i.c. FREQUENCY WINDOW DETECTOR 19 2 RREF 97 98 24 23 I2C-BUS 22 INTERRUPT CONTROLLER 4 92 36, 37 28, 29 14 8, 11, 15, 18 4 20 21 RSSI2 LOS2 VCCA 13 33 34 27 2 CREFQ CREF WINSIZE 3 90 PRSCLOQ 25 26, 50, 52, 63, 74, 100 D00Q to D15Q POCLK POCLKQ COUT COUTQ DOUT DOUTQ INT n.c. 001aad377 13 VDD VCCD PRSCLO INWINDOW 1, 35, 40, 43, 51 75, 76, 83, 86, 89, 93, 96, 99 32 D00 to D15 VCCO VEE ENLOUTQ LIM = Limiting amplifier RSSI = Received signal strength indicator LOS = Loss-of-signal detector LPF = Low-pass filter DMX = Demultiplexer Fig 1. Block diagram TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 3 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 6. Pinning information 77 D13 76 VCCD 78 D13Q 79 D14 80 D14Q 81 D15 82 D15Q 83 VCCD 84 CLOOP 85 CLOOPQ 86 VCCD 87 DLOOP 88 DLOOPQ 89 VCCD 90 ENLOUTQ 91 ENLINQ 92 INT 93 VCCD 94 COUT 95 COUTQ 96 VCCD 97 DOUT 98 DOUTQ 99 VCCD 100 VEE 6.1 Pinning VCCD 1 PRSCLO 2 75 VCCD 74 VEE PRSCLOQ 3 73 D12Q UI 4 72 D12 LOS1 5 71 D11Q RSSI1 6 70 D11 LOSTH1 7 69 D10Q VCCA 8 68 D10 IN1 9 67 D09Q INQ1 10 66 D09 VCCA 11 65 D08Q INSEL 12 64 D08 TZA3012HW WINSIZE 13 RREF 14 63 VEE 62 D07Q VCCA 15 61 D07 IN2 16 60 D06Q IN2Q 17 59 D06 VCCA 18 58 D05Q LOSTH2 19 57 D05 RSSI2 20 56 D04Q LOS2 21 55 D04 CS/DR0 22 54 D03Q SDA/DR1 23 53 D03 SCL/DR2 24 52 VEE 51 VCCD VEE 50 D02Q 49 D02 48 D01Q 47 D01 46 D00Q 45 D00 44 VCCD 43 POCLKQ 42 POCLK 41 VCCD 40 PARITYQ 39 PARITY 38 n.c. 37 n.c. 36 VCCD 35 CREFQ 34 CREF 33 VCCO 32 DMXR1 31 DMXR0 30 i.c. 29 i.c. 28 VEE 26 INWINDOW 27 VDD 25 001aad378 Fig 2. Pin configuration TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 4 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 6.2 Pin description Table 2: Pin description Symbol Pin Description VCCD 1 supply voltage (digital signal part) PRSCLO 2 prescaler output PRSCLOQ 3 prescaler inverted output UI 4 user interface select input LOS1 5 first input channel loss-of-signal output RSSI1 6 first input channel received signal strength indicator output LOSTH1 7 first input channel loss-of-signal threshold input VCCA 8 supply voltage (analog part) IN1 9 first channel input IN1Q 10 first channel inverted input VCCA 11 supply voltage (analog part) INSEL 12 input selector WINSIZE 13 wide and narrow frequency detect window select input RREF 14 reference resistor input VCCA 15 supply voltage (analog part) IN2 16 second channel input IN2Q 17 second channel inverted input VCCA 18 supply voltage (analog part) LOSTH2 19 second input channel loss-of-signal threshold input RSSI2 20 second input channel received signal strength indicator output LOS2 21 second input channel loss-of-signal output CS/DR0 22 chip select input or data rate select input 2 SDA/DR1 23 I2C-bus serial data input and output or data rate select input 1 SCL/DR2 24 I2C-bus serial clock input or data rate select input 2 VDD 25 supply voltage (digital controller part) VEE 26 ground INWINDOW 27 frequency window detector output i.c. 28 internally connected; leave open i.c. 29 internally connected; leave open DMXR0 30 demultiplexing ratio select 0 DMXR1 31 demultiplexing ratio select 1 VCCO 32 supply voltage (clock generator part) CREF 33 reference clock input CREFQ 34 reference clock inverted input VCCD 35 supply voltage (digital signal part) n.c. 36 not connected n.c. 37 not connected PARITY 38 parity output PARITYQ 39 parity inverted output TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 5 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Table 2: Pin description …continued Symbol Pin Description VCCD 40 supply voltage (digital signal part) POCLK 41 parallel clock output POCLKQ 42 parallel clock inverted output VCCD 43 supply voltage (digital signal part) D00 44 parallel data 00 output D00Q 45 parallel data 00 inverted output D01 46 parallel data 01 output D01Q 47 parallel data 01 inverted output D02 48 parallel data 02 output D02Q 49 parallel data 02 inverted output VEE 50 ground VCCD 51 supply voltage (digital signal part) VEE 52 ground D03 53 parallel data 03 output D03Q 54 parallel data 03 inverted output D04 55 parallel data 04 output D04Q 56 parallel data 04 inverted output D05 57 parallel data 05 output D05Q 58 parallel data 05 inverted output D06 59 parallel data 06 output D06Q 60 parallel data 06 inverted output D07 61 parallel data 07 output D07Q 62 parallel data 07 inverted output VEE 63 ground D08 64 parallel data 08 output D08Q 65 parallel data 08 inverted output D09 66 parallel data 09 output D09Q 67 parallel data 09 inverted output D10 68 parallel data 10 output D10Q 69 parallel data 10 inverted output D11 70 parallel data 11 output D11Q 71 parallel data 11 inverted output D12 72 parallel data 12 output D12Q 73 parallel data 12 inverted output VEE 74 ground VCCD 75 supply voltage (digital signal part) VCCD 76 supply voltage (digital signal part) D13 77 parallel data 13 output D13Q 78 parallel data 13 inverted output D14 79 parallel data 14 output D14Q 80 parallel data 14 inverted output TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 6 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Table 2: Pin description …continued Symbol Pin Description D15 81 parallel data 15 output D15Q 82 parallel data 15 inverted output VCCD 83 supply voltage (digital signal part) CLOOP 84 loop mode clock input CLOOPQ 85 loop mode clock inverted input VCCD 86 supply voltage (digital signal part) DLOOP 87 loop mode data input DLOOPQ 88 loop mode data inverted input VCCD 89 supply voltage (digital signal part) ENLOUTQ 90 line loop back enable input (active LOW) ENLINQ 91 diagnostic loop back enable input (active LOW) INT 92 interrupt output VCCD 93 supply voltage (digital signal part) COUT 94 recovered clock output COUTQ 95 recovered clock inverted output VCCD 96 supply voltage (digital signal part) DOUT 97 recovered data output DOUTQ 98 recovered data inverted output VCCD 99 supply voltage (digital signal part) VEE 100 ground VEE die pad common ground plane TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 7 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 7. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCCA Conditions Min Max Unit analog supply voltage −0.5 +3.6 V VCCD digital supply voltage −0.5 +3.6 V VCCO oscillator supply voltage −0.5 +3.6 V VDD supply voltage −0.5 +3.6 V Vn voltage on pin n D00 to D15, D00Q to D15Q, POCLK, POCLKQ, PARITY, PARITYQ, PRSCLO and PRSCLOQ VCC − 2.5 VCC + 0.5 V LOSTH1, LOSTH2 and RREF −0.5 VCC + 0.5 V RSSI1 and RSSI2 −0.5 VCC + 0.5 V UI, INSEL, WINSIZE, CS, SDA, SCL, DMXR0, DMXR1, ENLOUTQ and ENLINQ −0.5 VCC + 0.5 V LOS1, LOS2 and INWINDOW −0.5 VCC + 0.5 V INT −0.5 VCC + 0.5 V IN1, IN1Q, IN2 and IN2Q −30 +30 mA CREF, CREFQ, CLOOP, CLOOPQ, DLOOP and DLOOPQ −20 +20 mA INT −2 +2 mA input current on pin n II(n) Tamb ambient temperature −40 +85 °C Tj junction temperature - +125 °C Tstg storage temperature −65 +150 °C Typ Unit 16 K/W 8. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter Rth(j-a) Conditions thermal resistance from junction to ambient [1] In compliance with JEDEC standards JESD 51-5 and JESD 51-7. [2] Four-layer Printed-Circuit Board (PCB) in still air with 36 plated vias connected with the heatsink and the second and fourth layer in the PCB. TZA3012HW_1 Product data sheet [1] [2] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 8 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 9. Characteristics Table 5: Default measurement settings All measurements are done with the default settings. Parameter Pin Pin configured mode UI = LOW STM16/OC48 DR0 = LOW, DR1 = HIGH, DR2 = LOW Limiter 1 active INSEL = HIGH Detect window 1000 ppm WINSIZE = HIGH Disabled DOUT and COUT ENLOUTQ = HIGH Disabled DLOOP and CLOOP ENLINQ = HIGH DMX ratio = 1 : 16 DMXR0 = HIGH, DMXR1 = HIGH Reference frequency CREF and CREFQ = 19.44 MHz LOS2 switched off LOSTH2 = not connected D00 to D15 and D00Q to D15Q not connected PARITY, PARITYQ not connected POCLK, POCLKQ not connected PRSCLO and PRSCLOQ not connected Table 6: Supply characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies: pins VCCA, VCCD, VCCO VCC supply voltage 3.14 3.30 3.47 V ICCA analog supply current 15 20 27 mA ICCD digital supply current 270 350 450 mA ICCO oscillator supply current ICC(tot) total supply current [1] 20 25 33 mA 305 395 511 mA Digital controller: pins VDD VDD supply voltage 3.14 3.30 3.47 V IDD supply current 0 0 1 mA 0.96 1.3 1.77 W 1.17 1.21 1.26 V General [1] total power dissipation Ptot Reference: pin RREF reference voltage Vref [1] 10 kΩ to 20 kΩ to VEE The total supply current and power dissipation are dependent on the IC setups such as swing and loop modes and termination conditions. TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 9 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Table 7: Logic control input and output characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit CMOS input: pins UI, DR0, DR1, DR2, INSEL, WINSIZE, DMXR0, DMXR1, ENLOUTQ and ENLINQ VIL LOW-state input voltage - - 0.2VCC V VIH HIGH-state input voltage 0.8VCC - - V IIL LOW-state input current VIL = 0 V −200 - - µA IIH HIGH-state input current VIH = VCC - - 10 µA CMOS output: INWINDOW and INT VOL LOW-state output voltage IOL = 1 mA 0 - 0.2 V VOH HIGH-state output voltage IOH = −0.5 mA VCC − 0.2 - VCC V Open-drain output: pin INT VOL LOW-state output voltage IOL = 1 mA 0 - 0.2 V IOH HIGH-state output current VOH = VCC - - 10 µA Table 8: RF input, RSSI and LOS characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit [1] 12 - 500 mV lower slice level voltage [2] - −50 - mV Vsl(upper) upper slice level voltage [2] Zi input impedance RF input: pins IN1, INQ1, IN2 and INQ2 Vi(p-p) Vsl(lower) peak-to-peak input voltage single-ended - +50 - mV 80 100 120 Ω - 60 - dB Vi = 5 mV to 500 mV (p-p) 15 17 20 mV/dB differential αisol(ch-ch) isolation between channels RSSI circuit Vi(sens) input sensitivity voltage Output: pins RSSI1 and RSSI2 VO output voltage Vi = 32 mV (p-p); PRBS = (231 − 1) 580 680 780 mV ∆VO output voltage variation input 30 Mbit/s to 3200 Mbit/s; PRBS = (231 − 1); VCC = 3.14 V to 3.47 V; ∆Tamb = 120 °C −50 - +50 mV IO(source) output source current - - 1 mA IO(sink) output sink current - - 0.4 mA Zo output impedance - 1 10 Ω LOS detector LOS circuit [3] Vhys(i) input hysteresis voltage - 3 - dB tas assert time ∆Vi(p-p) = 3 dB - - 5 µs tdas de-assert time ∆Vi(p-p) = 3 dB - - 5 µs TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 10 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Table 8: RF input, RSSI and LOS characteristics …continued VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit CMOS output: pins LOS1 and LOS2 VOL LOW-state output voltage IOL = 1 mA 0 - 0.2 V VOH HIGH-state output voltage IOH = −0.5 mA VCC − 0.2 - VCC V [1] The RF input is protected against a differential overvoltage; the maximum input current is 30 mA. It is assumed that both inputs carry a complementary signal of the specified peak-to-peak value. [2] The slice level is adjustable in 256 steps controlled by I2C-bus registers LIMSLICE1 (address C0h) and LIMSLICE2 (address C1h). [3] The hysteresis is adjustable in 8 steps controlled by bits HYS1 and HYS2 in I2C-bus registers LIMLOS1CNF (address BDh) and LIMLOS2CNF (address BFh). Table 9: Clock and PLL characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 50 - 1000 mV VCC − 1 - VCC + 0.25 V Reference input frequency: pins CREF and CREFQ Vi(p-p) peak-to-peak input voltage single-ended VI input voltage Zi input impedance single-ended to VCC 40 50 60 Ω fi(ref) reference input frequency R = 1, 2, 4 or 8 18R 19.4R 21R MHz ∆fi(ref) reference input frequency accuracy SDH/SONET requirement −20 - +20 ppm PLL characteristics tacq acquisition time 30 Mbit/s - - 200 µs tacq(pc) power cycle acquisition time 30 Mbit/s - - 10 ms tacq(oc) octave change acquisition time 30 Mbit/s - - 10 µs TDRmax maximum transitionless data run 30 Mbit/s - 1000 - bit Table 10: Serial input and output characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 50 - 100 mV Serial input: pins CLOOP, CLOOPQ, DLOOP and DLOOPQ Vi(p-p) peak-to-peak input voltage VI input voltage Zi input impedance td delay time tsu single-ended VCC − 1 - VCC + 0.25 V single-ended to VCC 40 50 60 Ω data DLOOP and DLOOPQ to clock CLOOP and CLOOPQ; between differential crossovers referenced to negative clock edge 260 340 400 ps setup time see Figure 3 15 30 60 ps th hold time see Figure 3 15 30 60 ps δclk clock duty cycle clock CLOOP and CLOOPQ; between differential crossovers 40 50 60 % TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 11 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Table 10: Serial input and output characteristics …continued VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 50 80 110 mV Serial output: pins COUT, COUTQ, DOUT and DOUTQ Vo(p-p) peak-to-peak output voltage single-ended with 50 Ω external load; ENLOUTQ = LOW Zo output impedance single-ended to VCC 80 100 120 Ω tr rise time 20 % to 80 % - 100 - ps tf fall time 80 % to 20 % - 100 - ps td delay time data DOUT and DOUTQ to clock COUT and COUTQ; between differential crossovers referenced to negative clock edge 80 140 200 ps δclk clock duty cycle COUT and COUTQ; between differential crossovers 40 50 60 % [1] [1] The output swing is adjustable in 16 steps controlled by bits RFS in I2C-bus register CBh. CLOOP td tsu th DLOOP mbl554 The timing is measured from the crossover point of the clock input signal to the crossover point of the data input. Fig 3. Loop mode input timing Table 11: Parallel outputs characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Parallel output: pins D00 to D15, D00Q to D15Q, PARITY, PARITYQ, POCLK, POCLKQ, PRSCLO and PRSCLOQ CML mode Vo(p-p) peak-to-peak output voltage single-ended with 50 Ω external load to VCC; AC-coupled or DC-coupled Zo output impedance [1] 650 800 1000 mV single-ended to VCC 70 95 110 Ω tr rise time 20 % to 80 % 200 250 350 ps tf fall time 80 % to 20 % 200 250 350 ps fbit(par) parallel bit rate - - 400 Mbit/s LVPECL mode VOH HIGH-state output voltage 50 Ω termination to VCC − 2 V VCC − 1.2 VCC − 1.0 VCC − 0.9 V VOL LOW-state output voltage 50 Ω termination to VCC − 2 V VCC − 2.0 VCC − 1.9 VCC − 1.7 V TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 12 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Table 11: Parallel outputs characteristics …continued VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter Conditions [1] Min Typ Max Unit 700 900 1150 mV Vo(p-p) peak-to-peak output voltage LVPECL floating; single-ended with 50 Ω external load to VCC; AC-coupled or DC-coupled tr rise time 20 % to 80 % 300 350 400 ps tf fall time 80 % to 20 % 300 350 400 ps fbit(par) parallel bit rate - - 400 Mbit/s Timing delay time td referenced to negative clock edge [2] data D00 to D15 to clock POCLK DMX = 1 : 16, 1 : 10, 1 : 8 −100 +100 +250 ps data D06 to D09 to clock POCLK DMX = 1 : 4 150 180 250 ps 40 50 60 % δclk clock duty cycle POCLK and POCLKQ; between differential crossovers tsk(o) output skew time between channels [2] data D00 to data Dn DMX = 1 : 16, 1 : 10, 1 : 8 - - 200 ps data D06 to D09 to clock POCLK DMX = 1 : 4 - - 50 ps [1] The output swing is adjustable in 16 steps controlled by bits MFS in I2C-bus register IOCNF3 (address C8h). In standard LVPECL mode only swing = 12 (default) should be used. [2] With 50 % duty cycle. Table 12: Jitter tolerance characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter Conditions tjit(tol)(p-p) peak-to-peak jitter tolerance ITU-T G.958; PRBS = (231 − 1) [1] Min Typ Max STM1/OC3 mode [2] f = 6.5 kHz 3 10 - f = 65 kHz 0.3 1.0 - f = 1 MHz 0.3 0.5 - f = 25 kHz 3 10 - f = 250 kHz 0.3 1.0 - f = 5 MHz 0.3 0.5 - f = 100 kHz 3 10 - f = 1 MHz 0.3 1.0 - f = 20 MHz 0.3 0.5 - STM4/OC12 mode STM16/OC48 mode [1] Unit [3] [4] The peak-to-peak jitter tolerance is expressed as a ratio of the Unit Interval (UI): UI ( max ) – UI ( min ) t jit ( tol ) ( p – p ) = -------------------------------------------------UI ( nom ) [2] The minimum value of the peak-to-peak jitter tolerance is 0.25 for Tamb = −40 °C to 0 °C at f = 65 kHz and 1 MHz. TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 13 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver [3] The minimum value of the peak-to-peak jitter tolerance is 0.25 for Tamb = −40 °C to 0 °C at f = 250 kHz and 5 MHz. [4] The minimum value of the peak-to-peak jitter tolerance is 0.25 for Tamb = −40 °C to 0 °C at f = 1 MHz and 20 MHz. Table 13: I2C-bus characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit DC characteristics: pins SCL and SDA VIL LOW level input voltage - - 0.2VCC V VIH HIGH level input voltage 0.8VCC - - Vhys hysteresis of Schmitt trigger inputs VOL1 LOW level output voltage Ii V 0.05VCC - - V 0 - 0.4 V input current each I/O pin −10 - +10 µA Ci capacitance for each I/O pin - - 10 pF Cb capacitive load for each bus line - - 400 pF VnL noise margin at the LOW-level 0.1VCC - - V VnH noise margin at the HIGH-level 0.2VCC - - V SDA open-drain; IOL = 3 mA Timing (standard mode): pins SCL and SDA fSCL SCL clock frequency - - 100 kHz tLOW LOW period of the SCL clock 1.3 - - µs tHD;STA hold time (repeated) START condition 0.6 - - µs tHIGH HIGH period of the SCL clock 0.6 - - µs tSU;STA set-up time for a repeated START condition 0.6 - - µs tHD;DAT data hold time 0 - 0.9 µs tSU;DAT data set-up time 100 - - ns tSU;STO setup time for STOP condition 0.6 - - µs tr rise time of both SDA and SCL signals 20 - 300 ns tf fall time of both SDA and SCL signals 20 - 300 ns tBUF bus free time between a STOP and START condition 1.3 - - µs tSP pulse width of spikes that must be suppressed by the input filter 0 - 50 ns tSP tr SDA tLOW tf tSU;DAT tr tf tHD;STA tBUF SCL tHD;STA S tHD;DAT tHIGH tSU;STA tSU;STO Sr P S msc610 Fig 4. I2C-bus timing TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 14 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 10. Package outline HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad SOT638-1 c y exposed die pad side X Dh A 75 51 76 50 ZE e E HE Eh A A2 (A3) A1 w M θ bp Lp pin 1 index L detail X 26 100 1 25 bp e w M ZD v M A D B HD v M B 0 10 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 A2 A3 bp c D(1) Dh E(1) Eh e 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 7.1 6.1 14.1 13.9 7.1 6.1 0.5 HD HE 16.15 16.15 15.85 15.85 L Lp v w y 1 0.75 0.45 0.2 0.08 0.08 ZD(1) ZE(1) θ 1.15 0.85 7° 0° 1.15 0.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT638-1 REFERENCES IEC JEDEC JEITA MS-026 EUROPEAN PROJECTION ISSUE DATE 03-04-07 05-02-02 Fig 5. Package outline SOT638-1 (HTQFP100) TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 15 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 11. Revision history Table 14: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes TZA3012HW_1 20051215 Product data sheet - - - TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 16 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 12. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 13. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 14. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 15. Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of Koninklijke Philips Electronics N.V. A-Rate — is a trademark of Koninklijke Philips Electronics N.V. 16. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] TZA3012HW_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 15 December 2005 17 of 18 TZA3012HW Philips Semiconductors 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 17. Contents 1 2 2.1 2.2 2.3 2.4 2.5 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Dual limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Data and clock recovery . . . . . . . . . . . . . . . . . . 1 Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Additional features with I2C-bus . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal characteristics. . . . . . . . . . . . . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information . . . . . . . . . . . . . . . . . . . . 17 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 15 December 2005 Document number: TZA3012HW_1 Published in The Netherlands