As the roll out of digital TV accelerates, DTV receiver manufacturers are looking for improved performance, flexibility and cost reductions to meet the demands of the consumer market. Philips’ latest reference design meets these stringent requirements, using two new ICs, the second generation TDA8961 VSB demodulator and the TDA8980 integrated ATSC/NTSC TV input processor ATSC/NTSC digital TV front-end chipset Second generation chipset Complete ATSC (VSB)/NTSC channel decoding solution with just two ICs This chipset combines Philips’ long experience in analog TV with our innovative approach to DTV, creating an outstanding system solution showcasing Philips’ mixed signal technology expertise and offering very high levels of integration, performance and flexibility. Designed for analog and digital TV systems in North America and other ATSC countries, the chipset enables manufacturers to design systems offering end-users significantly improved reception at an attractive price. The two key chips featured are the TDA8980 TV input processor and the TDA8961 8-VSB demodulator/decoder for the ATSC DTV standard. Designed specifically to reduce the chip count of first generation front-ends, the TDA8980 eliminates many components by integrating NTSC decoding, an IF circuit, picture and sound Applications • • demodulation and VSB downconversion, all into a single device. Digital ATSC/NTSC-compliant TV receivers and Set Top Converters This chipset gives true design flexibility, with the TDA8980 offering DTV-equipped PC/multimedia applications both analog and digital capability, with comprehensive analog source selection and also providing format conversion. This ensures glueless support for the many legacy inputs a digital hybrid receiver is likely to Tightly integrated, flexible DTV front-end • • • require. Second generation ATSC/NTSC channel decoding chipset Benefiting from real-world experience of VSB reception, Philips’ second Greatly reduced chip count due to single-chip generation VSB demodulator handles the many problems caused by ATSC/NTSC TV input processor providing man-made and naturally occurring echoes. Intelligent techniques in the NTSC TV decoding and VSB IF downconversion decoder allow it to cope with the delays and reflections caused by indoor Analog source selection and format conversion environments full of objects and moving people. Its maximum equalizer length of 80 µs in conjunction with external software allows the receiver to cope with very long static echoes. Patented NTSC co-channel High performance reception interference technology prevents strong NTSC signals from interfering • Urban reception improvement with their less powerful DTV counterparts on the same channel, without • Unique co-channel filter to reduce interference the noise penalty associated with regular comb filter schemes. from strong NTSC signals • Ability to handle very long static echoes (up to 80 µs) in conjunction with external software COMPLETE REFERENCE DESIGN FOR HYBRID ATSC/NTSC RECEIVER FRONT-ENDS This reference design demonstrates a complete solution for building hybrid ATSC/NTSC receiver front-ends for HDTV sets, STBs and PC/multimedia applications, using just two highly integrated, second generation ICs. TDA8980HL ATSC/NTSC TV INPUT PROCESSOR Key features When decoding NTSC, the chip digitizes the audio signals into an • NTSC-M colour decoder tuned with a An incoming 6 MHz wide 8-VSB IF signal is downconverted to a low 12 MHz reference crystal IF, centred at 4 MHz, which is digitized using an on-chip 10-bit ADC (or external clock signal) and gluelessly interfaced to the VSB demodulator for further VSB IF circuit for pre-processing processing. In a typical application, the TDA8980 handles AGC, DTV signals eliminating the need for external components such as an op-amp loop Alignment-free PLL demodulator Vision integrator. • • I2S stream using on-chip audio stereo 16-bit ADCs, and the video information into an ITU656 stream via the on-chip video ADCs. IF circuit without external components • • Sound IF amplifier with separate input It has an internal 2-D adaptive comb filter for NTSC, and a YUV for single reference QSS mode and interface allows simple connection of additional picture enhancement separate AGC circuit ICs such as a 3-D comb filter. For sound decoding, external Alignment-free FM sound demodulator devices - a BTSC sounder decoder, for example - can be connected. generates the input signal for a BTSC Video source selection with 2 external TDA8961 DTV DEMODULATOR/DECODER General features CVBS or Y/C inputs and an • stereo decoder • • • One-chip ATSC-compliant demodulator and concatenated independently switchable output Trellis (Viterbi)/Reed-Solomon decoder with de-interleaver Two 10-bit video ADCs for converting and de-randomizer selected YUV signals (video mode) • Parallel (8-bit) or serial MPEG2 transport stream output or downconverted I&Q signals • On-board I2C-bus interface (VSB mode) • MPEG2 serial transport stream input Two 16-bit audio A/D converters and I2S formatter Up to four stereo analog inputs and one I2S input • • CD out CD in ITU656 or VSB formatter 4 TDA1315 AUDIO MIX stereo audio in 3 AUDIO MUX 3 L3 bus I2S out S/PDIF in Direct input to video ADCs TS in MPOC output VCC TDA9851 BTSC DECODER 5V I2C VCC 5 12 Integrating many components into a single 12 MHz TDA8980 (w/socket) (w/socket) status tuner AGC I2C PCF9851 I2C ADC and ADCs for audio and video, it can also generate a ‘mixed down’ I signal for demodulation of a digital broadcast VSB input. An I2C-bus controlled internal switch enables the device to switch between analog NTSC and digital 8-VSB IF signals. 4.5 MHz TRAP I2C reset IF AGC comp. RGBS/YUVS video in in S-video in 3V I2C 9 8 Errror InRange_1 Tuner_Lock FE_Lock EQ_Lock FSHNDSHK FPGA_1 FPGA_2 FPGA_3 I2C EEPROM & CONTROL diag an NTSC-M colour decoder, an IF circuit TS 6 TDA8961 12 MHz 2 TV and multimedia applications. Containing parallel output 9 TUNER chip, the TDA8980HL is designed for both I2S out JTAG 9 I2S in TS connector • reset I2S out diag 11 30 FIFO 6 SAA7146 FPGA 8 11 TS + diag + control + status reset FIFO power +5 V +12 V PCI connector serial TS input serial TS output MSD051 8-VSB demodulator • On-chip digital tuner AGC control feedback equalizer (DFE) structure. • Integrated digital Square-Root Raised-Cosine (half Nyquist) Once trellis decoding is complete, the stream filter with 11.5 % roll-off is de-interleaved with a convolutional Fully internal carrier recovery loop with programmable de-interleaver with on-chip memory. loop filter The Reed-Solomon decoder is ATSC- No need for external VCXO and DAC due to internal sample compliant, with a length of 207, and it can rate converter correct up to 10 bytes. After the decoded Fully internal symbol timing recovery with programmable stream is de-randomized using a pseudo- loop filters random bit sequence (PRBS), it outputs an • • • 8-bit parallel or a serial MPEG2 transport Adaptive equalizer stream for subsequent de-multiplexing. • Feed forward including a decision feedback equalizer (DFE) • Standard range: -2.3 µs to +22.5 µs (up to 80 µs in conjunction TD1536 tuner with external software) Able to handle ATSC terrestrial signals as well Adaptation based on ATSC field sync (trained) and/or as NTSC and QAM, the TD1536 offers flat 8-VSB data (blind) frequency response, low oscillator phase noise Additional complex equaliser to cope with highly dense and excellent large signal handling urban multipath characteristics. Optimized for handling high Patented adaptive NTSC co-channel filter technology, adjacent channel levels, through on-board with low/zero insertion loss selectivity adjustment (SAW filter), the • • • TD1536 also provides internal automatic gain On-chip FEC control (AGC), minimizing design-in effort. • Trellis (Viterbi) decoder The TD1536’s low output impedance makes • Rate 2/3 (Rate 1/2 Ungerboeck-code-based) it capable of driving several SAW filters • (207, 187, T=10) Reed-Solomon decoder (for example, second VSB and NTSC SAWs). • Internal convolutional de-interleaving It is powered from a single 5V supply. • ATSC standard-based de-randomizer SAA7146A PCI bridge The TDA8961 is an ATSC-compliant device with forward error For PC/multimedia applications, the reference correction, accepting 8-VSB modulated signals with the additional design includes the option to include the ability to apply the VSB IC AGC control output directly to the SAA7146A PCI bridge. This device features tuner. The combination of the TDA8980 and TDA8961 requires high performance 2D scaling, resulting in very only one 12 MHz crystal and when the TDA8980 is performing few artefacts even when pictures are reduced to NTSC decoding, the TDA8961 can be set in a feed-through mode, icon size, making it ideal for windowing and enabling ITU656 data to appear at the MPEG2 transport stream high-end applications. It also has a hardware output for feeding to the graphics display IC. The demodulator can vanity picture function and by performing also act as an MPEG2 Transport Stream switcher for an additional most of the video processing on-board, the serial stream. SAA7146A helps reduce load on the CPU, maintaining high overall system performance. After the TDA8961 has performed internal carrier recovery, Nyquist In addition to the PCI-bus, it supports a filtering and symbol timing recovery, it carries out adaptive variety of interfaces including two ITU-R 656 equalization using the ATSC field sync (trained equalization) ports, an Intel/Motorola 8/16-bit DEBI and/or the 8-VSB data itself (blind equalization). This uses a decision (Digital Expansion Bus Interface), I2C and I2S bus connectors, and a 4-bit general purpose interface. ATSC/NTSC digital TV front-end chipset Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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