Philips Semiconductors FAST Products Product specification Octal shift/count registered transceiver with adder and parity (3–State) FEATURES this device only on the output states. Both OE pins are enabled low. • High speed parallel registers with positive edge–triggered D–type flip–flops • High speed full adder All operating modes, other than clear, 3–State, and the two hold modes require the rising edge of the clock. All setup and hold times must be observed for proper functioning. • 8–bit parity generator • High impedance PNP inputs for light bus loading • Center VCC and GND pins and controlled output buffers minimize ground–bounce problems • 3–State glitch–free power–up and power–down • Broadside pinout Data on the internal register can be switched on either the A or B ports for output. Depeding on the state of the select inputs (S0, S1, S2), and carry in/ serial in/ clock enable (CI/SI/CE), the 74F807 has nine distinct operating modes: DESCRIPTION The 74F807 is a registered transceiver that also has the capability to perform count, shift, and add functions. It is also has the capability to generate a parity bit output. All of this is done within a 28–pin package. The MR input is an overriding asynchronous reset which forces the STATOUT output low as well as the A and B busses. The A and B busses have separate OE inputs (OEA, OEB]. These inputs have no bearing on the internal functioning of TYPE 74F807 FAST 74F807 1. Add mode w/carry in – the CI/SI/CE input is used as a carry in signal and the STATOUT output is the carry out signal. (In add mode the COUT is NOT registered. This means the carry output signal appears at the STATOUT output one clock prior to the related data.). In this mode, the CI/SI/CE input is added to the register contents and to the inputs. (The adder uses only the An inputs, not the Bn inputs.) input and the STATOUT output is terminal count. In this mode the CI/SI/CE input must be high to enable the count function. The register contents are incremented by one. 4. Count w/count enable (hold) –– same as above except no incrementing occurs. 5. Count wo/count enable –– same as number 3 except the CI/SI/CE input has no control over counting or holding. 6. Shift –– The CI/SI/CE input now becomes the serial input and the STATOUT output becomes the serial output. In this mode the CI/SI/CE input is shifted into the Q0 register, Q0 into the Q1 register etc. The Q7 register is shifted into the STATOUT. 7. Load A inputs –– The CI/SI/CE input has no bearing in either of the load modes. The STATOUT output becomes the parity out. The parity out is high for an odd number of registered bits high, and low for even number of registered bits high (even parity). In this mode the An inputs are loaded into the internal register and output to the B bus. If OEA = low the internal register would wrap around and be loaded again. 8. Load B inputs –– same as number 7 except the A and B busses are switched. 9. Hold –– Again the CI/SI/CE input is not used; the STATOUT output is still the parity out. In this mode either the A bus, B bus or both can be held with the registered data. No other operation is performed. 2. Add mode wo/carry in –– same as above except the CI/SI/CE input is not included in the addition. 3. Count w/count enable (count) –– the CI/SI/ CE input is now used as the count enable TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL) 115MHz 155mA ORDERING INFORMATION DESCRIPTION ORDER CODE COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 28–pin plastic DIP (300 mils) N74F807N 28–pin SOL1 N74F807D 28–pin PLCC N74F807A Note to ordering information 1.Thermal mounting techiques are recommended. See SMD Process Applications (page 17) for a discussion of thermal consideration for surface mounted devices. June 18, 1991 1 853–1421 02931 Philips Semiconductors FAST Products Product specification Octal shift/count registered transceiver with adder and parity (3–State) FAST 74F807 INPUT AND OUTPUT LOADING AND FAN OUT TABLE 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Data I/O inputs 3.5/0.166 70µA/70µA A output enable inputs 1.0/0.033 20µA/20µA Carry in/serial in/clock enable input 1.0/0.033 20µA/20µA CP Clock input 1.0/0.033 20µA/20µA MR Master reset input (active low) 1.0/0.033 20µA/20µA Sn Select inputs 1.0/0.033 20µA/20µA 150/40 3mA/24mA PINS DESCRIPTION An, Bn OEA, OEB CI/SI/CE STATOUT Status out output An, Bn Data I/O outputs 150/40 3mA/24mA Note to input and output loading and fan out table 1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. PIN CONFIGURATION PIN CONFIGURATION PLCC OEA 1 28 MR OEB 2 27 STATOUT A0 3 STAT A1 A0 OEB OEA MR OUT B0 4 26 B0 A1 4 25 B1 A3 23 B3 GND 7 GND 7 22 V CC GND 8 GND 8 21 B4 A4 9 A4 9 20 B5 A5 10 A5 10 19 B6 A6 11 A6 11 18 B7 16 S1 CP 14 15 S2 26 23 B3 22 VCC 21 B4 20 B5 19 B6 13 14 15 16 17 18 A7 CI/ CP SI/ CE S2 S1 S0 B7 IEC/IEEE SYMBOL 13 3 4 5 6 9 10 11 12 15 28 OEA 2 OEB 1 STATOUT 13 CI/SI/CE 28 MR 2 27 3 B0 B1 B2 B3 B4 B5 B6 B7 26 25 24 23 22 20 19 0 M1 15 3 14 A0 A1 A2 A3 A4 A5 A6 A7 1 EN3 17 16 18 VCC = Pin 22 GND = Pin 7, 8 June 18, 1991 27 PLCC 12 LOGIC SYMBOL 28 24 B2 24 B2 A3 6 17 S0 1 25 B1 A2 5 A7 12 2 5 6 CI/SI/CE 13 3 A2 2 STATUS OUT 27 R EN1 EN2 26 1 2 4 25 5 24 8 23 9 21 10 20 11 19 13 18 Philips Semiconductors FAST Products Product specification Octal shift/count registered transceiver with adder and parity (3–State) FAST 74F807 LOGIC DIAGRAM OEA OEB CP MR CI/SI/CE S0 1 2 14 28 13 LE 17 An 16 QIN S1 S2 SUMn 15 ADDER CIN COUT 8 8 8 8 8 QIN RCOUT LE An 2 – 7, 9 – 12 A0 – A7 SUMn SHIFTOUT CI/SI/CE LOAD A 8 DATA REGISTERS Bn HOLD 8 Qn Dn CP R E G I S T E R R TCIN 8 26 –23, 21 – 18 B0 – B7 TC 27 LOAD B CNTE C O N T R O L TC REGISTER CP CNTNE CNT PARITY SHIFT QIN ADD VCC = Pin 22, GND = Pin 7, 8 June 18, 1991 3 P0 STATOUT Philips Semiconductors FAST Products Product specification Octal shift/count registered transceiver with adder and parity (3–State) FAST 74F807 FUNCTION TABLE INPUTS INTERNAL REGISTER OUTPUT OPERATING MODE MR CP SO S1 S2 CI/SI/CE Qn STATOUT L X X X X X L L Clear H ↑ L L L CI/SI/CE COUT Add mode w/carry in H ↑ L L H X an0 + qn0 COUT Add mode wo/carry in H ↑ L H L H qn0 + 1 TC (1) Count w/count enable (count) H X L H H L qn0 TC (1) Count w/count enable (hold) H ↑ L H H X qn0 + 1 TC (1) Count wo/count enable H ↑ H L L CI/SI/CE (3) Q7 Shift H ↑ H L H X An0 parity (2) Load A ports H ↑ H H L X Bn0 parity (2) Load B ports H X H H H X Qn0 parity (2) Hold CI/SI/CE + an0 + qn0 Notes to function table 1. H = High–voltage level 2. L = Low–voltage level 3. a, b, q = Lower case indicate the state of the referenced output prior to the low–to–high clock transition 4. X = Don’t care 5. Z = High impedance ”off)” state 6. ↑ = Low–to–high clock transition. 7. (1) = Terminal count is high when the output is a terminal count (HHHHHHHH). 8. (2) = Parity is high for odd number of internal register bits high, low for even number of internal register bits high. 9. (3) = CI/SI/CE → Q0 → Q1, etc. OE FUNCTION TABLE INPUTS OEa OUTPUTS MODE OEb An Bn L L active output active output L H active output input Enable A outputs, B inputs H L input active output A inputs, enable B outputs H H input input Enable A and B outputs A and B are inputs NOTE: The outputs, whether An or Bn, are equal to the INTERNAL REGISTER Qn. ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free–air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in high output state –0.5 to VCC V IOUT Current applied to output in low output state 48 mA Tamb Operating free air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C NOTE: When outputs are disabled the internal registers (Qn) operate as usual. June 18, 1991 4 Philips Semiconductors FAST Products Product specification Octal shift/count registered transceiver with adder and parity (3–State) FAST 74F807 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER MIN NOM MAX UNIT 5.0 5.5 V VCC Supply voltage 4.5 VIH High–level input voltage 2.0 VIL Low–level input voltage 0.8 V IIk Input clamp current –18 mA IOH High–level output current –3 mA IOL Low–level output current 24 mA Tamb Operating free air temperature range +70 °C V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST LIMITS CONDITIONS1 VOH VOL High-level output voltage Low-level output voltage MIN TYP2 UNIT MAX VCC = MIN, VIL = MAX, ±10%VCC 2.4 VIH = MIN, IOH = MAX ±5%VCC 2.7 VCC = MIN, VIL = MAX, ±10%VCC 0.35 0.50 V VIH = MIN, IOL = MAX ±5%VCC 0.35 0.50 V –0.73 -1.2 V 100 µA V 3.4 V VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High–level input current VCC = MAX, VI = 2.7V 20 µA IIL Low–level input current VCC = MAX, VI = 0.5V –20 µA IOZH + IIH Off–state output current, high–level voltage applied VCC = MAX, VO = 2.7V 50 µA IOZL + IIL Off–state output current, low–level voltage applied VCC = MAX, VO = 0.5V –50 µA IOS Short–circuit output current3 VCC = MAX -150 mA An, Bn -60 ICC Supply current (total) VCC = MAX 155 210 mA Notes to DC electrical characteristics 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. June 18, 1991 5 Philips Semiconductors FAST Products Product specification Octal shift/count registered transceiver with adder and parity (3–State) FAST 74F807 AC ELECTRICAL CHARACTERISTICS LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V CL = 50pF, RL = 500Ω UNIT CL = 50p, RL = 500Ω MIN TYP fmax Maximum clock frequency Waveform 1 100 115 tPLH tPHL Propagation delay CP to An or Bn (load) Waveform 1 9.0 5.0 10.5 6.5 11.5 9.5 8.0 4.5 13.5 10.0 ns tPLH tPHL Propagation delay CP to An or Bn (shift) Waveform 1 9.0 4.5 10.5 6.5 12.5 9.5 8.0 4.5 15.0 10.0 ns tPLH tPHL Propagation delay CP to An or Bn (count) Waveform 1 9.0 5.0 11.5 6.5 14.0 9.5 8.0 4.5 15.5 10.0 ns tPLH tPHL Propagation delay CP to Bn (add) Waveform 1 9.0 5.0 10.5 6.5 11.5 9.5 8.0 4.5 13.5 10.0 ns tPLH tPHL Propagation delay CP to STATOUT (load A) Waveform 1 17.5 12.5 19.5 14.5 22.5 17.0 15.5 11.5 26.5 19.0 ns tPLH tPHL Propagation delay CP to STATOUT (shift) Waveform 1 11.0 7.0 13.0 8.5 15.5 11.5 9.5 6.5 18.0 12.0 ns tPLH tPHL Propagation delay CP to STATOUT (count) Waveform 1 10.5 6.5 12.0 8.0 15.0 11.0 9.0 6.0 17.0 11.5 ns tPLH tPHL Propagation delay CP to STATOUT (add) Waveform 1 13.0 8.5 15.0 10.5 18.0 13.0 11.5 8.0 20.5 14.0 ns tPHL Propagation delay MR to An or Bn (load A) Waveform 3 6.5 8.0 11.0 6.0 12.0 ns tPHL Propagation delay MR to STATOUT (load A) Waveform 3 14.0 16.0 18.5 13.0 20.5 ns tPHL Propagation delay MR to STATOUT (shift) Waveform 3 8.5 10.0 12.5 8.0 14.0 ns tPHL Propagation delay MR to STATOUT (count) Waveform 3 8.5 10.0 12.5 8.0 14.0 ns tPHL Propagation delay MR to STATOUT (add) Waveform 3 10.5 12.0 14.5 9.5 16.0 ns tPLH tPHL Propagation delay An to STATOUT (add) Waveform 4 6.5 8.0 14.0 14.0 23.5 22.5 5.5 7.5 26.5 27.0 ns tPLH tPHL Propagation delay CI/SI/CE to STATOUT Waveform 4 19.5 21.0 21.5 22.5 24.0 25.5 17.0 20.0 28.0 29.5 ns tPLH tPHL Propagation delay Sn to STATOUT (load A) Waveform 4 8.0 7.5 10.0 11.5 12.5 15.5 7.0 7.0 14.5 17.0 ns tPLH tPHL Propagation delay Sn to STATOUT (load B) Waveform 4 6.5 8.0 10.0 12.0 13.0 15.0 5.5 7.0 15.0 16.5 ns tPLH tPHL Propagation delay Sn to STATOUT (add) Waveform 4 19.0 18.5 21.0 20.0 23.5 23.0 17.0 17.5 27.5 26.0 ns tPLH tPHL Propagation delay Sn to STATOUT (shift) Waveform 4 6.0 8.0 8.0 9.5 10.5 12.0 5.0 7.0 12.0 13.5 ns tPZH tPZL Output enable time, OEA to An or OEB to Bn Waveform 6 Waveform 7 2.5 4.0 4.5 5.5 7.0 8.5 2.0 3.5 8.0 9.0 ns tPHZ tPLZ Output disable time, OEA to An or OEB to Bn Waveform 6 Waveform 7 2.0 3.5 4.5 5.5 7.5 8.5 2.0 3.0 9.0 9.5 ns June 18, 1991 6 MAX VCC = +5.0V ± 10% MIN MAX 70 MHz Philips Semiconductors FAST Products Product specification Octal shift/count registered transceiver with adder and parity (3–State) FAST 74F807 AC SETUP REQUIREMENTS LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500Ω MIN tsu(H) tsu(L) Setup time, high or low An, Bn to CP (load) th(H) th(L) TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% UNIT CL = 50pF, RL = 500Ω MIN MAX Waveform 5 6.0 9.5 6.5 12.0 ns Hold time, high or low An, Bn to CP (load) Waveform 5 0.0 0.0 0.0 0.0 ns tsu(H) tsu(L) Setup time, high or low An, Bn to CP (add) Waveform 5 10.5 16.5 12.0 21.5 ns th(H) th(L) Hold time, high or low An, Bn to CP (add) Waveform 5 0.0 0.0 0.0 0.0 ns tsu(H) tsu(L) Setup time, high or low Sn to CP (add) Waveform 5 16.0 16.0 20.0 28.5 ns tsu(H) tsu(L) Setup time, high or low Sn to CP (count) Waveform 5 16.5 19.5 19.0 22.5 ns tsu(H) tsu(L) Setup time, high or low Sn to CP (shift) Waveform 5 11.0 7.0 13.0 8.0 ns tsu(H) tsu(L) Setup time, high or low Sn to CP (load) Waveform 5 17.5 6.5 20.5 7.0 ns th(H) th(L) Hold time, high or low Sn to CP (all modes) Waveform 5 0.0 0.0 0.0 0.0 ns tsu(H) tsu(L) Setup time, high or low CI/SI/CE to CP (add) Waveform 5 10.0 18.0 11.5 22.0 ns tsu(H) tsu(L) Setup time, high or low CI/SI/CE to CP (count) Waveform 5 8.5 16.0 10.0 18.5 ns tsu(H) tsu(L) Setup time, high or low CI/SI/CE to CP (shift) Waveform 5 5.0 9.0 5.5 10.5 ns th(H) th(L) Hold time, high or low CI/SI/CE to CP (all modes) Waveform 5 0.0 0.0 0.0 0.0 ns tw(H) tw(L) CP pulse width, High or low Waveform 1 5.5 4.5 6.0 4.5 ns tw(L) MR pulse width, low Waveform 3 4.5 5.0 ns trec Recovery time, MR to CP Waveform 2 2.0 2.0 ns June 18, 1991 7 Philips Semiconductors FAST Products Product specification Octal shift/count registered transceiver with adder and parity (3–State) FAST 74F807 AC WAVEFORMS 1/fmax CPBA or CPAB VM VM VM tw(H) tPHL VM tPLH tw(L) trec CP VM VM An or Bn STATOUT VM MR Waveform 1. Propagation delay for clock input to output, clock pulse width, and maximum clock frequency VM Waveform 2. Master reset to clock recovery time tw(L) MR VM An, Sn, CI/SI/CE VM tPHL Bn or An STATOUT VM tPLH VM tPLH VM VM VM VM th(L) th(H) tw(L) tsu(H) VM CP VM Waveform 4. Propagation delay for select to STATOUT, CI/SI/CE to STATOUT or data to STATOUT VM tsuL) tPHL VM STATOUT Waveform 3. Propagation delay for master reset to data or master reset to STATOUT An, Bn, Sn, CI/SI/CE VM VM VM Waveform 5. Data setup and hold times VM OEB or OEA VM tPZH VOH -0.3V tPHZ Bn or An VM OEB or OEA VM tPZL tPLZ Bn or An VM VM 0V Waveform 6. 3–State output enable time to high level and output disable time from high level Waveform 7. 3-state output enable time to low level and output disable time from low level VOL +0.3V Notes to AC waveforms 1. For all waveforms, VM = 1.5V. 2. The shaded areas indicate when the input is permitted to change for predictable output performance. TEST CIRCUIT AND WAVEFORMS . SWITCH POSITION TEST SWITCH tPLZ, tPZL closed All other open 7.0V VCC NEGATIVE PULSE 90% RL VOUT PULSE GENERATOR AMP (V) VM VM 10% VIN 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V D.U.T. RT CL RL Test circuit for 3–State outputs DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value RT = Termination resistance should be equal to ZOUT of pulse generators. June 18, 1991 tw 90% AMP (V) 90% POSITIVE PULSE 90% VM VM 10% 10% tw 0V Input pulse definition INPUT PULSE REQUIREMENTS family 74F 8 amplitude VM rep. rate 3.0V 1.5V 1MHz tw tTLH 500ns 2.5ns tTHL 2.5ns