IRF IRFU540Z

APPROVED
PD - TBD
AUTOMOTIVE MOSFET
IRFR540Z
IRFU540Z
Features
HEXFET® Power MOSFET
Advanced Process Technology
Ultra Low On-Resistance
l175°C Operating Temperature
lFast Switching
lRepetitive Avalanche Allowed up to Tjmax
l
l
D
VDSS = 100V
RDS(on) = 28.5mΩ
G
Description
Specifically designed for Automotive applications,
this HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating . These features combine to make this design an extremely efficient and
reliable device for use in Automotive applications
and a wide variety of other applications.
ID = 35A
S
D-Pak
IRFR540Z
Absolute Maximum Ratings
Parameter
Max.
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
35
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
Pulsed Drain Current
140
PD @TC = 25°C Power Dissipation
VGS
Linear Derating Factor
Gate-to-Source Voltage
d
EAS (Thermally limited) Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
EAS (Tested )
c
IAR
Avalanche Current
EAR
TJ
Repetitive Avalanche Energy
TSTG
Storage Temperature Range
h
Parameter
RθJA
Junction-to-Ambient
j
mJ
A
°C
Mounting Torque, 6-32 or M3 screw
Junction-to-Ambient (PCB mount)
39
-55 to + 175
y
ij
300
y
10 lbf in (1.1N m)
Thermal Resistance
RθJA
W
W/°C
V
mJ
Reflow Soldering Temperature, for 10 seconds
j
91
0.61
± 20
75
Operating Junction and
Junction-to-Case
A
See Fig.12a, 12b, 15, 16
g
RθJC
Units
25
c
IDM
I-Pak
IRFU540Z
Typ.
Max.
–––
1.64
–––
40
–––
110
Units
°C/W
HEXFET® is a registered trademark of International Rectifier.
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1
2/3/05
IRFR/U540Z
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
–––
V
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
100
–––
VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.092
–––
V/°C Reference to 25°C, ID = 1mA
RDS(on)
Static Drain-to-Source On-Resistance
–––
22.5
28.5
mΩ
VGS = 10V, ID = 21A
VGS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
VDS = VGS, ID = 50µA
gfs
Forward Transconductance
28
–––
–––
S
VDS = 25V, ID = 21A
IDSS
Drain-to-Source Leakage Current
µA
VDS = 100V, VGS = 0V
–––
–––
20
–––
–––
250
Gate-to-Source Forward Leakage
–––
–––
200
Gate-to-Source Reverse Leakage
–––
–––
-200
Qg
Total Gate Charge
–––
39
59
Qgs
Gate-to-Source Charge
–––
11
–––
Qgd
Gate-to-Drain ("Miller") Charge
–––
12
–––
VGS = 10V
td(on)
Turn-On Delay Time
–––
14
–––
VDD = 50V
tr
Rise Time
–––
42
–––
ID = 21A
td(off)
Turn-Off Delay Time
–––
43
–––
tf
Fall Time
–––
34
–––
VGS = 10V
LD
Internal Drain Inductance
–––
4.5
–––
Between lead,
IGSS
VDS = 100V, VGS = 0V, TJ = 125°C
nA
Internal Source Inductance
–––
7.5
VGS = 20V
VGS = -20V
ID = 21A
nC
ns
nH
LS
e
–––
VDS = 50V
RG = 13 Ω
e
e
D
6mm (0.25in.)
G
from package
and center of die contact
S
Ciss
Input Capacitance
–––
1690
–––
VGS = 0V
Coss
Output Capacitance
–––
180
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
–––
100
–––
Coss
Output Capacitance
–––
720
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
110
–––
VGS = 0V, VDS = 80V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
190
–––
VGS = 0V, VDS = 0V to 80V
pF
ƒ = 1.0MHz
f
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
–––
–––
35
ISM
(Body Diode)
Pulsed Source Current
–––
–––
140
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.3
V
p-n junction diode.
TJ = 25°C, IS = 21A, VGS = 0V
trr
Reverse Recovery Time
–––
32
48
ns
TJ = 25°C, IF = 21A, VDD = 50V
Qrr
Reverse Recovery Charge
–––
40
60
nC
di/dt = 100A/µs
ton
Forward Turn-On Time
2
c
MOSFET symbol
A
showing the
integral reverse
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRFR/U540Z
1000
100
BOTTOM
1000
≤60µs PULSE WIDTH
TOP
Tj = 25°C
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
10
100
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
4.5V
10
≤60µs PULSE WIDTH
Tj = 175°C
4.5V
1
1
0.1
1
10
100
0.1
10
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
70
Gfs , Forward Transconductance (S)
ID, Drain-to-Source Current(Α)
1
100
TJ = 175°C
10
TJ = 25°C
1
VDS = 25V
2
3
4
5
6
7
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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50
40
TJ = 175°C
30
20
VDS = 10V
10
380µs PULSE WIDTH
≤60µs PULSE WIDTH
0.1
TJ = 25°C
60
0
8
0
10
20
30
40
50
ID,Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
vs. Drain Current
3
IRFR/U540Z
3000
20
2500
VGS, Gate-to-Source Voltage (V)
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
C, Capacitance(pF)
Coss = Cds + Cgd
2000
Ciss
1500
1000
500
Coss
Crss
0
ID= 21A
VDS = 80V
16
VDS= 50V
VDS= 20V
12
8
4
0
1
10
0
100
1000.0
ID, Drain-to-Source Current (A)
1000
100.0
TJ = 175°C
10.0
TJ = 25°C
1.0
VGS = 0V
0.1
0.2
0.4
0.6
0.8
1.0
30
40
50
60
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
ISD , Reverse Drain Current (A)
20
QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
1.2
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10
1.4
OPERATION IN THIS AREA
LIMITED BY R DS (on)
100
100µsec
1msec
10
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
DC
0.1
0
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFR/U540Z
2.5
ID = 21A
RDS(on) , Drain-to-Source On Resistance
30
VGS = 10V
2.0
(Normalized)
ID , Drain Current (A)
40
20
10
1.5
1.0
0.5
0
25
50
75
100
125
150
-60 -40 -20
175
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
TC , CaseTemperature (°C)
Fig 10. Normalized On-Resistance
vs. Temperature
Fig 9. Maximum Drain Current vs.
Case Temperature
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
0.05
τJ
0.02
0.01
R1
R1
τJ
τ1
R2
R2
τ2
τ1
τ2
Ci= τi/Ri
Ci τi/Ri
0.01
SINGLE PULSE
( THERMAL RESPONSE )
R3
R3
τ3
τC
τ
τ3
Ri (°C/W) τi (sec)
2.626
0.000052
0.6611
0.001297
0.7154
0.01832
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFR/U540Z
D.U.T
RG
VGS
20V
DRIVER
L
VDS
+
V
- DD
IAS
tp
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS, Single Pulse Avalanche Energy (mJ)
160
15V
ID
6.5A
9.4A
BOTTOM 21A
TOP
120
80
40
0
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
QGS
QGD
4.5
ID = 1.0mA
VG
Charge
Fig 13a. Basic Gate Charge Waveform
L
DUT
0
1K
VGS(th) Gate threshold Voltage (V)
10 V
ID = 250µA
ID = 50µA
4.0
3.5
3.0
2.5
2.0
1.5
VCC
1.0
-75
-50
-25
0
25
50
75
100 125 150 175
TJ , Temperature ( °C )
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage vs. Temperature
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IRFR/U540Z
100
Avalanche Current (A)
Duty Cycle = Single Pulse
10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses
0.01
0.05
0.10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
40
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 21A
30
20
10
0
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRFR/U540Z
D.U.T
Driver Gate Drive
ƒ
+
‚
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
D=
Period
P.W.
+
VDD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
VDS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRFR/U540Z
D-Pak (TO-252AA) Package Outline
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 1234
AS S EMBLED ON WW 16, 1999
IN THE AS S EMBLY LINE "A"
N ote: "P" in as s embly line
pos ition indicates "Lead-Free"
OR
INT ERNATIONAL
RECT IFIER
LOGO
PART NUMBER
IRFR120
916A
12
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRFR120
P916A
12
AS S EMBLY
LOT CODE
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34
AS S EMBLY
LOT CODE
DAT E CODE
YEAR 9 = 1999
WEEK 16
LINE A
34
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 9 = 1999
WEEK 16
A = AS S EMBLY S IT E CODE
9
IRFR/U540Z
I-Pak (TO-251AA) Package Outline
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFU120
WIT H AS SEMBLY
LOT CODE 5678
ASS EMBLED ON WW 19, 1999
IN T HE AS SEMBLY LINE "A"
Note: "P" in as sembly line
pos ition indicates "Lead-Free"
OR
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRFU120
919A
56
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRFU120
56
AS SEMBLY
LOT CODE
10
78
ASSEMBLY
LOT CODE
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
78
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 9 = 1999
WEEK 19
A = AS SEMBLY SIT E CODE
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IRFR/U540Z
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
„ Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
max. junction temperature. (See fig. 11).
‚ Limited by TJmax, starting TJ = 25°C, L = 0.17mH … Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
RG = 25Ω, IAS = 21A, VGS =10V. Part not
avalanche performance.
recommended for use above this value.
† This value determined from sample failure population. 100%
ƒ Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
tested to this value in production.
‡ When mounted on 1" square PCB (FR-4 or G-10 Material) .
ˆ Rθ is measured at TJ approximately 90°C
 Repetitive rating; pulse width limited by
Data and specifications subject to change without notice.
This product has been designed for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.2/05
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11