KERSEMI IRFU4104

IRFR4104PbF
IRFU4104PbF
AUTOMOTIVE MOSFET
Features
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
l
l
l
l
l
l
D
VDSS = 40V
RDS(on) = 5.5mΩ
G
ID = 42A
S
Description
Specifically designed for Automotive applications, this HEXFET®
Power MOSFET utilizes the latest processing techniques to
achieve extremely low on-resistance per silicon area. Additional
features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche
rating . These features combine to make this design an extremely
efficient and reliable device for use in Automotive applications and
a wide variety of other applications.
D-Pak
IRFR4104
I-Pak
IRFU4104
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
119
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current
IDM
42
480
PD @TC = 25°C Power Dissipation
140
W
Linear Derating Factor
VGS
Gate-to-Source Voltage
EAS (Thermally limited) Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
EAS (Tested )
0.95
± 20
W/°C
V
145
mJ
84
c
d
c
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
TJ
Operating Junction and
TSTG
Storage Temperature Range
h
310
See Fig.12a, 12b, 15, 16
g
-55 to + 175
°C
Mounting Torque, 6-32 or M3 screw
300 (1.6mm from case )
y
Parameter
RθJA
RθJA
Junction-to-Ambient
i
y
10 lbf in (1.1N m)
Thermal Resistance
Junction-to-Case
Junction-to-Ambient (PCB mount)
A
mJ
Soldering Temperature, for 10 seconds
RθJC
A
Typ.
Max.
–––
1.05
–––
40
–––
110
Units
°C/W
1
12/06/04
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IRFR/U4104PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
V(BR)DSS
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
40
–––
–––
∆V(BR)DSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.032
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
4.3
5.5
VGS(th)
Gate Threshold Voltage
2.0
–––
4.0
gfs
IDSS
Forward Transconductance
IGSS
V
Conditions
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 42A
e
V
VDS = VGS, ID = 250µA
58
–––
–––
S
VDS = 10V, ID = 42A
–––
–––
20
µA
VDS = 40V, VGS = 0V
–––
–––
250
Gate-to-Source Forward Leakage
–––
–––
200
nA
VGS = 20V
–––
-200
Drain-to-Source Leakage Current
VDS = 40V, VGS = 0V, TJ = 125°C
Gate-to-Source Reverse Leakage
–––
Qg
VGS = -20V
Total Gate Charge
–––
59
89
Qgs
Gate-to-Source Charge
–––
19
–––
Qgd
Gate-to-Drain ("Miller") Charge
–––
24
–––
VGS = 10V
td(on)
Turn-On Delay Time
–––
17
–––
VDD = 20V
tr
Rise Time
–––
69
–––
td(off)
Turn-Off Delay Time
–––
37
–––
tf
Fall Time
–––
36
–––
VGS = 10V
LD
Internal Drain Inductance
–––
4.5
–––
Between lead,
LS
Internal Source Inductance
–––
7.5
–––
6mm (0.25in.)
from package
Ciss
Input Capacitance
–––
2950
–––
and center of die contact
VGS = 0V
Coss
Output Capacitance
–––
660
–––
Crss
Reverse Transfer Capacitance
–––
370
–––
Coss
Output Capacitance
–––
2130
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
590
–––
VGS = 0V, VDS = 32V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
850
–––
VGS = 0V, VDS = 0V to 32V
ID = 42A
nC
VDS = 32V
e
ID = 42A
ns
nH
RG = 6.8 Ω
e
VDS = 25V
pF
ƒ = 1.0MHz
f
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
42
ISM
(Body Diode)
Pulsed Source Current
–––
–––
480
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.3
V
trr
Reverse Recovery Time
–––
28
42
ns
Qrr
Reverse Recovery Charge
–––
24
36
nC
ton
Forward Turn-On Time
2
c
Conditions
MOSFET symbol
A
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 42A, VGS = 0V
e
TJ = 25°C, IF = 42A, VDD = 20V
di/dt = 100A/µs
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRFR/U4104PbF
ID, Drain-to-Source Current (A)
TOP
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
100
10
4.5V
60µs PULSE WIDTH
Tj = 25°C
VGS
TOP
ID, Drain-to-Source Current (A)
1000
1
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
100
4.5V
10
60µs PULSE WIDTH
Tj = 175°C
1
0.1
0
1
10
100
100
0.1
0
VDS, Drain-to-Source Voltage (V)
10
100
100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
120
Gfs, Forward Transconductance (S)
T J = 25°C
ID, Drain-to-Source Current (Α)
1
T J = 175°C
100
10
VDS = 20V
60µs PULSE WIDTH
T J = 175°C
100
80
60
TJ = 25°C
40
20
VDS = 10V
380µs PULSE WIDTH
1
4
6
8
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
10
0
0
20
40
60
80
100
ID, Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
Vs. Drain Current
3
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IRFR/U4104PbF
5000
ID= 42A
VGS, Gate-to-Source Voltage (V)
4000
C, Capacitance (pF)
20
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
C oss = C ds + C gd
Ciss
3000
2000
Coss
1000
VDS= 32V
VDS= 20V
16
12
8
4
Crss
0
0
1
10
0
100
20
40
60
80
100
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
10000
1000.0
100.0
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
T J = 175°C
10.0
T J = 25°C
1.0
1000
100
100µsec
10
1msec
1
VGS = 0V
0.1
0.1
0.0
0.5
1.0
1.5
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
2.0
0
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFR/U4104PbF
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
120
LIMITED BY PACKAGE
ID , Drain Current (A)
100
80
60
40
20
0
ID = 42A
VGS = 10V
1.5
1.0
0.5
25
50
75
100
125
150
175
-60 -40 -20
T C , Case Temperature (°C)
0
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 10. Normalized On-Resistance
Vs. Temperature
Fig 9. Maximum Drain Current Vs.
Case Temperature
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
τJ
0.05
0.02
0.01
0.01
R1
R1
τJ
τ1
R2
R2
τC
τ2
τ1
τ2
τ
Ri (°C/W)
0.5067
τi (sec)
0.000414
0.5428
0.004081
Ci= τi/Ri
Ci= i/Ri
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
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IRFR/U4104PbF
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
VGS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS, Single Pulse Avalanche Energy (mJ)
600
15V
ID
9.2A
13A
BOTTOM 42A
TOP
500
400
300
200
100
0
25
50
75
100
125
150
175
Starting T J, Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGD
4.0
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
VGS(th) Gate threshold Voltage (V)
QGS
ID = 250µA
3.0
2.0
+
V
- DS
1.0
-75 -50 -25
VGS
0
25
50
75
100 125 150 175
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage Vs. Temperature
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IRFR/U4104PbF
1000
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
Avalanche Current (A)
100
0.01
0.05
10
0.10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
EAR , Avalanche Energy (mJ)
160
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 42A
120
80
40
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P D (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I av = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
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IRFR/U4104PbF
D.U.T
Driver Gate Drive
ƒ
+
-
„
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
*

RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
-
Period
P.W.
+
VDD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V DS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRFR/U4104PbF
D-Pak (TO-252AA) Package Outline
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
WITH ASS EMBLY
LOT CODE 1234
AS SEMBLED ON WW 16, 1999
IN T HE ASS EMBLY LINE "A"
PART NUMBER
INTERNATIONAL
RECT IFIER
LOGO
Note: "P" in as sembly line pos ition
indicates "Lead-F ree"
IRFU120
12
916A
34
ASS EMBLY
LOT CODE
DAT E CODE
YEAR 9 = 1999
WEEK 16
LINE A
OR
PART NUMBER
INT ERNAT IONAL
RECT IF IER
LOGO
IRFU120
12
AS SEMBLY
LOT CODE
34
DATE CODE
P = DESIGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 9 = 1999
WEEK 16
A = AS SEMBLY S ITE CODE
9
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IRFR/U4104PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFU120
WIT H ASS EMBLY
LOT CODE 5678
ASS EMBLED ON WW 19, 1999
IN T HE AS SEMB LY LINE "A"
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRFU120
919A
56
78
AS SEMBLY
LOT CODE
Note: "P" in ass embly line
pos ition indicates "Lead-Free"
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
OR
INTERNATIONAL
RECTIFIER
LOGO
PART NUMBER
IRFU120
56
AS S EMBLY
LOT CODE
10
78
DAT E CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 9 = 1999
WEEK 19
A = ASS EMBLY SITE CODE
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IRFR/U4104PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
„ Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
max. junction temperature. (See fig. 11).
‚ Limited by TJmax, starting TJ = 25°C, L = 0.16mH … Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
RG = 25Ω, IAS = 42A, VGS =10V. Part not
avalanche performance.
recommended for use above this value.
† This value determined from sample failure population. 100%
ƒ Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
tested to this value in production.
‡ When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
 Repetitive rating; pulse width limited by
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11