INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4066B gates Quadruple bilateral switches Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4066B gates Quadruple bilateral switches disabled and a high impedance between Y and Z is established (OFF condition). DESCRIPTION The HEF4066B has four independent bilateral analogue switches (transmission gates). Each switch has two input/output terminals (Y/Z) and an active HIGH enable input (E). When E is connected to VDD a low impedance bidirectional path between Y and Z is established (ON condition). When E is connected to VSS the switch is The HEF4066B is pin compatible with the HEF4016B but exhibits a much lower ON resistance. In addition the ON resistance is relatively constant over the full input signal range. Fig.1 Functional diagram. Fig.2 Pinning diagram. PINNING HEF4066BP(N): 14-lead DIL; plastic (SOT27-1) E0 to E3 enable inputs HEF4066BD(F): 14-lead DIL; ceramic (cerdip) (SOT73)) Y0 to Y3 input/output terminals Z0 to Z3 input/output terminals HEF4066BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America APPLICATION INFORMATION An example of application for the HEF4066B is: • Analogue and digital switching Fig.3 Schematic diagram (one switch). January 1995 2 Philips Semiconductors Product specification HEF4066B gates Quadruple bilateral switches RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Power dissipation per switch P max. 100 mW For other RATINGS see Family Specifications DC CHARACTERISTICS Tamb = 25 °C VDD V SYMBOL 5 ON resistance ON resistance MIN. TYP. MAX. CONDITIONS − 350 2500 Ω En at VDD − 80 245 Ω Vis = VSS to VDD 15 − 60 175 Ω see Fig.4 5 − 115 340 Ω En at VDD 10 RON − 50 160 Ω Vis = VSS 15 − 40 115 Ω see Fig.4 5 − 120 365 Ω En at VDD 10 RON − 65 200 Ω Vis = VDD 15 − 50 155 Ω see Fig.4 ‘∆’ ON resistance 5 − 25 − En at VDD between any two 10 − 10 − Ω Vis = VSS to VDD channels 15 − 5 − Ω see Fig.4 5 − − − nA − − − nA ON resistance OFF state leakage 10 RON ∆RON IOZ Ω current, any 10 channel OFF 15 − − 200 nA 5 − 2,25 1 V − 4,50 2 V − 6,75 2 V En input voltage LOW VIL 10 15 VDD V SYMBOL +25 MAX. MAX. Quiescent device current 5 10 IDD 15 Input leakage current at En January 1995 15 ± IIN Iis = 10 µA see Fig.9 Tamb (°c) −40 En at VSS CONDITIONS +85 MAX. 1,0 1,0 7,5 µA 2,0 2,0 15,0 µA input combinations; 4,0 4,0 30,0 µA VI = VSS or VDD − 300 1000 nA En at VSS or VDD 3 VSS = 0; all valid Philips Semiconductors Product specification HEF4066B gates Quadruple bilateral switches Fig.4 Test set-up for measuring RON. En at VDD Iis = 200 µA VSS = 0 V Fig.5 Typical RON as a function of input voltage. NOTE To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VSS. January 1995 4 Philips Semiconductors Product specification HEF4066B gates Quadruple bilateral switches AC CHARACTERISTICS (1), (2) VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD V SYMBOL TYP. MAX. Propagation delays Vis → Vos HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 10 20 ns 5 10 ns 5 10 ns 10 20 ns 5 10 ns 5 10 ns note 3 note 3 Output disable times En → Vos 5 HIGH 10 80 160 ns 65 130 ns 60 120 ns 80 160 ns 70 140 ns 15 70 140 ns En → Vos 5 40 80 ns HIGH 10 20 40 ns 15 15 30 ns 5 45 90 ns 20 40 ns 15 15 30 ns 5 0,25 % 10 0,04 % 15 0,04 % tPHZ 15 5 LOW 10 tPLZ note 4 note 4 Output enable times LOW Distortion, sine-wave response Crosstalk between any two channels Crosstalk; enable input to output OFF-state feed-through ON-state frequency response January 1995 10 tPZH tPZL 5 − MHz 10 1 MHz 15 − MHz 5 − mV 10 50 mV 15 − mV 5 − MHz 10 1 MHz 15 − MHz 5 − MHz 10 90 MHz 15 − MHz 5 note 4 note 4 note 5 note 6 note 7 note 8 note 9 Philips Semiconductors Product specification HEF4066B gates Quadruple bilateral switches VDD V Dynamic power 5 dissipation per package (P) TYPICAL FORMULA FOR P (µW) 800 fi + ∑ (foCL) × VDD 2 10 3 500 fi + ∑ (foCL) × VDD 2 15 10 100 fi + ∑ (foCL) × VDD 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) Notes 1. Vis is the input voltage at a Y or Z terminal, whichever is assigned as input. 2. Vos is the output voltage at a Y or Z terminal, whichever is assigned as output. 3. RL = 10 kΩ to VSS; CL = 50 pF to VSS; En = VDD; Vis = VDD (square-wave); see Figs 6 and 10. 4. RL = 10 kΩ; CL = 50 pF to VSS; En = VDD (square-wave); Vis = VDD and RL to VSS for tPHZ and tPZH; Vis = VSS and RL to VDD for tPLZ and tPZL; see Figs 6 and 11. 5. RL = 10 kΩ; CL = 15 pF; En = VDD; Vis = 1⁄2 VDD(p-p) (sine-wave, symmetrical about 1⁄2 VDD); fis = 1 kHz; see Fig.7. 6. RL = 1 kΩ; Vis = 1⁄2 VDD(p-p) (sine-wave, symmetrical about 1⁄2 VDD); V os (B) 20 log ------------------- = -50 dB; E n (A) = V SS ; E n ( B ) = V DD ; see Fig. 8. V is ( A ) 7. RL = 10 kΩ to VSS; CL = 15 pF to VSS; En = VDD (square-wave); crosstalk is Vos (peak value); see Fig.6. 8. RL = 1 kΩ; CL = 5 pF; En = VSS; Vis = 1⁄2 VDD(p-p) (sine-wave, symmetrical about 1⁄2 VDD); V os 20 log --------- = -50 dB; see Fig. 7. V is 9. RL = 1 kΩ; CL = 5 pF; En = VDD; Vis = 1⁄2 VDD(p-p) (sine-wave, symmetrical about 1⁄2 VDD); V os 20 log --------- = -3 dB; see Fig. 7. V is Fig.6 January 1995 Fig.7 6 Philips Semiconductors Product specification HEF4066B gates Quadruple bilateral switches Fig.8 Fig.9 January 1995 7 Philips Semiconductors Product specification HEF4066B gates Quadruple bilateral switches Fig.10 Waveforms showing propagation delays from Vis to Vos. (1) Vis at VDD (2) Vis at VSS. Fig.11 Waveforms showing output disable and enable times. January 1995 8