IRF HIP6019

Data Sheet No. PD94142
IRU3007
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK, NON-SYNCHRONOUS, ADJUSTABLE LDO AND 200mA ON-BOARD LDO
FEATURES
DESCRIPTION
Provides Single Chip Solution for Vcore, GTL+,
Clock Supply & 3.3V Switcher On-Board
Second switcher provides simple control for the
on-board 3.3V supply
200mA On-Board LDO Regulator
Designed to meet Intel VRM 8.2 and 8.3 specification for Pentium II
On-Board DAC programs the output voltage from
1.3V to 3.5V
Linear Regulator Controller On-Board for 1.5V
GTL+ supply
Loss-less Short Circuit Protection
Synchronous Operation allows maximum efficiency
Patented architecture allows fixed frequency
operation as well as 100% duty cycle during
dynamic load
Minimum Part Count
Soft-Start
High current totem pole drivers for directly driving
the external Power MOSFETs
Power Good function monitors all outputs
Over-Voltage Protection circuitry protects the
switcher outputs and generates a fault output
Thermal Shutdown
APPLICATIONS
Total Power Solution for Pentium II processor
application
TYPICAL APPLICATION
The IRU3007 controller IC is specifically designed to meet
Intel specification for Pentium II microprocessor applications as well as the next generation of P6 family
processors. The IRU3007 provides a single chip controller IC for the Vcore, LDO controller for GTL+ and an
internal 200mA regulator for clock supply which are required for the Pentium II applications. It also contains a
switching controller to convert 5V to 3.3V regulator for
on-board applications that uses either AT type power
supply or is desired not to rely on the ATX power supply’s
3.3V output. These devices feature a patented topology
that in combination with a few external components, as
shown in the typical application circuit, will provide in
excess of 14A of output current for an on-board DC/DC
converter while automatically providing the right output
voltage via the 5-bit internal DAC. The IRU3007 also features, loss-less current sensing for both switchers by
using the RDS(on) of the high-side power MOSFET as the
sensing resistor, internal current limiting for the clock
supply, a Power Good window comparator that switches
its open collector output low when any one of the outputs is outside of a pre-programmed window. Other features of the device are: Under-Voltage Lockout for both
5V and 12V supplies, an external programmable softstart function, programming the oscillator frequency via
an external resistor, Over-Voltage Protection (OVP) circuitry for both switcher outputs and an internal thermal
shutdown.
Note: Pentium II and Pentium Pro are trademarks of Intel Corp.
5V
SWITCHER2
CONTROL
VO U T 2
SWITCHER1
CONTROL
VO U T1
LINEAR
REGULATOR
VO U T4
IRU3007
LINEAR
CONTROL
VO U T 3
Figure 1 - Typical application of IRU3007.
PACKAGE ORDER INFORMATION
TA (°C)
0 To 70
Rev. 2.1
08/20/02
DEVICE
IRU3007CW
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PACKAGE
28-pin Plastic SOIC WB (W)
1
IRU3007
ABSOLUTE MAXIMUM RATINGS
V5 Supply Voltage ....................................................
V12 Supply Voltage ..................................................
Storage Temperature Range ......................................
Operating Junction Temperature Range .....................
7V
20V
-65°C To 150°C
0°C To 125°C
PACKAGE INFORMATION
28-PIN WIDE BODY PLASTIC SOIC (W)
TOP VIEW
UGate2 1
28 V12
Phase2 2
27 UGate1
VID4 3
26 Phase1
VID3 4
25 LGate1
VID2 5
24 PGnd
VID1 6
23 OCSet1
VID0 7
22 VSEN1
PGood 8
21 Fb1
OCSet2 9
20 NC
Fb2 10
19 Fb3
V5 11
18 Gate3
SS 12
17 Gnd
Fault / Rt 13
16 VOUT4
Fb4 14
15 VSEN2
uJA =808C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over V12=12V, V5=5V and TA=0 to 70°C. Typical values refer
to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER
Supply UVLO Section
UVLO Threshold-12V
UVLO Hysteresis-12V
UVLO Threshold-5V
UVLO Hysteresis-5V
Supply Current
Operating Supply Current
SYM
TEST CONDITION
Supply Ramping Up
Supply Ramping Up
V12
V5
Switching Controllers; Vcore (V OUT1) and I/O (V OUT2)
VID Section (Vcore only)
DAC Output Voltage (Note 1)
DAC Output Line Regulation
DAC Output Temp Variation
VID Input LO
VID Input HI
VID Input Internal Pull-Up
Resistor to V5
VFB2 Voltage
Oscillator Section (Internal)
Osc Frequency
Rt=Open
2
MIN
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0.99Vs
TYP
MAX
UNITS
10
0.4
4.3
0.3
V
V
V
V
6
30
mA
Vs
0.1
0.5
1.01Vs
0.8
2
27
2
V
%
%
V
V
KV
V
KHz
200
Rev. 2.1
08/20/02
IRU3007
PARAMETER
Error Comparator Section
Input Bias Current
Input Offset Voltage
Delay to Output
Current Limit Section
CS Threshold Set Current
CS Comp Offset Voltage
Hiccup Duty Cycle
Output Drivers Section
Rise Time
Fall Time
Dead Band Time Between
High Side and Synch Drive
(Vcore Switcher Only)
2.5V Regulator (V OUT4)
Reference Voltage
Reference Voltage
Dropout Voltage
Load Regulation
Line Regulation
Input Bias Current
Output Current
Current Limit
Thermal Shutdown
1.5V Regulator (V OUT3)
Reference Voltage
Reference Voltage
Input Bias Current
Output Drive Current
Power Good Section
Core UV Lower Trip Point
Core UV Upper Trip Point
Core UV Hysteresis
Core OV Upper Trip Point
Core OV Lower Trip Point
Core OV Hysteresis
I/O UV lower trip point
I/O UV Upper Trip Point
Fb4 Lower Trip Point
Fb4 Upper Trip Point
Fb3 Lower Trip Point
Fb3 Upper Trip Point
Power Good Output LO
Power Good Output HI
Fault (Over-Voltage) Section
Core OV Upper Trip Point
Core OV Lower Trip Point
Soft-Start Section
Pull-Up Resistor to 5V
I/O OV Upper Trip Point
I/O OV Lower Trip Point
Fault Output HI
Rev. 2.1
08/20/02
SYM
TEST CONDITION
MIN
TYP
-2
VDIFF=10mV
MAX UNITS
2
+2
100
mA
mV
ns
+5
CSS=0.1mF
10
mA
mV
%
CL=3000pF
CL=3000pF
CL=3000pF
70
70
200
ns
ns
ns
1.260
1.260
0.6
0.5
0.2
V
V
V
%
%
mA
mA
mA
8C
200
-5
VO4
TA=258C, V OUT4=Fb4
IO=200mA
1mA<IO<200mA
3.1V<VI/O<4V, VO=2.5V
2
200
300
145
VO3
TA=258C, Gate3=Fb3
1.260
1.260
2
50
VSEN 1 Ramping Down
VSEN 1 Ramping Up
V
V
mA
mA
VSEN 2 Ramping Down
VSEN 2 Ramping Up
Fb4 Ramping Down
Fb4 Ramping Up
Fb3 Ramping Down
Fb3 Ramping Up
RL=3mA
RL=5K Pull Up to 5V
0.90Vs
0.92Vs
0.02Vs
1.10Vs
1.08Vs
0.02Vs
2.4
2.6
0.95
1.05
0.95
1.05
0.4
4.8
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VSEN 1 Ramping Up
VSEN 1 Ramping Down
1.17Vs
1.15Vs
V
V
OCSet=0V, Phase=5V
VSEN 2 Ramping Up
VSEN 2 Ramping Down
IO=3mA
23
4.3
4.2
10
KV
V
V
V
VSEN 1 Ramping Up
VSEN 1 Ramping Down
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3
IRU3007
Note 1: Vs refers to the set point voltage given in Table 1
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
Table 1 - Set point voltage vs. VID codes
PIN DESCRIPTIONS
PIN#
1
2
4
PIN SYMBOL
UGate2
Phase2
3
VID4
4
VID3
5
VID2
6
VID1
7
VID0
8
PGood
9
OCSet2
PIN DESCRIPTION
Output driver for the high-side power MOSFET for the I/O supply.
This pin is connected to the Source of the power MOSFET for the I/O supply and it
provides the negative sensing for the internal current sensing circuitry.
This pin selects a range of output voltages for the DAC. When in the LO state the range
is 1.3V to 2.05V and when it switches to HI state the range is 2.0V to 3.5V. This pin is
TTL compatible that realizes a logic “1” as either HI or Open. When left open, this pin is
pulled up internally by a 27KV resistor to 5V supply.
MSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic “1” as either HI or Open. When left open, this pin is pulled up internally by
a 27KV resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes a logic “1” as either HI or Open. When left open, this pin is pulled up internally by a
27KV resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes a logic “1” as either HI or Open. When left open, this pin is pulled up internally by a
27KV resistor to 5V supply.
LSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic “1” as either HI or Open. When left open, this pin is pulled up internally by
a 27KV resistor to 5V supply.
This pin is an open collector output that switches LO when any of the outputs are outside
of the specified under voltage trip point. It also switches low when V SEN 1 pin is more than
10% above the DAC voltage setting.
This pin is connected to the Drain of the power MOSFET of the I/O supply and it provides
the positive sensing for the internal current sensing circuitry. An external resistor programs the CS threshold depending on the RDS of the power MOSFET. An external capacitor is placed in parallel with the programming resistor to provide high frequency noise
filtering.
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Rev. 2.1
08/20/02
IRU3007
PIN#
10
PIN SYMBOL
Fb2
11
V5
12
SS
13
Fault / Rt
14
15
Fb4
VSEN 2
16
17
18
19
20
21
VOUT4
Gnd
Gate3
Fb3
NC
Fb1
22
VSEN 1
23
OCSet1
24
PGnd
25
26
LGate1
Phase1
27
28
UGate1
V12
Rev. 2.1
08/20/02
PIN DESCRIPTION
This pin provides the feedback for the non-synchronous switching regulator. A resistor
divider is connected from this pin to VOUT2 and ground that sets the output voltage. The
value of the resistor connected from VOUT2 to Fb2 must be less than 100V.
5V supply voltage. A high frequency capacitor (0.1 to 1mF) must be placed close to this
pin and connected from this pin to the ground plane for noise free operation.
This pin provides the soft-start for the 2 switching regulators. An internal resistor charges
an external capacitor that is connected from 5V supply to this pin which ramps up the
outputs of the switching regulators, preventing the outputs from overshooting as well as
limiting the input current. The second function of the Soft-Start cap is to provide long off
time (HICCUP) for the synchronous MOSFET during current limiting.
This pin has dual function. It acts as an output of the OVP circuitry or it can be used to
program the frequency using an external resistor. When used as a fault detector, if any of
the switcher outputs exceed the OVP trip point, the Fault pin switches to 12V and the
soft-start cap is discharged. If the Fault pin is to be connected to any external circuitry,
it needs to be buffered as shown in the application circuit.
This pin provides the feedback for the internal LDO regulator that its output is VOUT4.
This pin is connected to the output of the I/O switching regulator. It is an input that
provides sensing for the Under/Over-voltage circuitry for the I/O supply as well as the
power for the internal LDO regulator.
This pin is the output of the internal LDO regulator.
This pin serves as the ground pin and must be connected directly to the ground plane.
This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.
This pin provides the feedback for the linear regulator that its output drive is Gate3.
No connection.
This pin provides the feedback for the synchronous switching regulator. Typically this pin
can be connected directly to the output of the switching regulator. However, a resistor
divider is recommended to be connected from this pin to VOUT1 and ground to adjust the
output voltage for any drop in the output voltage that is caused by the trace resistance.
The value of the resistor connected from VOUT1 to Fb1 must be less than 100V.
This pin is internally connected to the undervoltage and overvoltage comparators sensing
the Vcore status. It must be connected directly to the Vcore supply.
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resistor programs the CS threshold depending on the RDS of the power MOSFET. An external
capacitor is placed in parallel with the programming resistor to provide high frequency
noise filtering.
This pin serves as the Power ground pin and must be connected directly to the ground
plane close to the source of the synchronous MOSFET. A high frequency capacitor
(typically 1mF) must be connected from V12 pin to this pin for noise free operation.
Output driver for the synchronous power MOSFET for the Core supply.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
Output driver for the high-side power MOSFET for the Core supply.
This pin is connected to the 12V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (typically 1mF) must be placed close to this pin and
PGnd pin and be connected directly from this pin to the ground plane for noise free
operation.
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5
IRU3007
BLOCK DIAGRAM
4.3V
Enable
V12
Over
Voltage
28
UVLO
V5
Vset
Enable
1.17Vset
11
Vset
7
VID1
6
VID2
5
VID3
4
VID4
3
VSEN1
22
Fb3
19
18
VSEN2
15
Slope
Comp
2.5V
5Bit
DAC
1.1Vset
16
Fb4
14
PGood
UGate1
25
LGate1
26
Phase1
23
OCSet1
Enable
2
Phase2
9
OCSet2
13
Fault / Rt
1
UGate2
24
PGnd
17
Gnd
10
Fb2
12
SS
Osc
Soft
Start &
Fault
Logic
Over
Current
200uA
0.9Vset
V12
Slope
Comp
1.26V
0.9V
PWM
Control
+
V5
2.0V
VOUT4
27
V12
V12
Gate3
Fb1
PWM
Control
+
VID0
21
V12
Enable
8
Figure 2 - Simplified block diagram of the IRU3007.
6
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Rev. 2.1
08/20/02
IRU3007
TYPICAL APPLICATION
R22
12V
L1
R9
C5
5V
C2
R12
C8
C10
C14
C3
R10
Q1
L2
V OUT2
3.0V - 3.5V
OCSet2
V12
OCSet1
UGate2
UGate1
Phase2
Phase1
R13
Q3
V OUT1
1.8V - 3.5V
C1
C16
R14
C4
Q4
LGate1
D1
L3
C13
R15
R1
R21
PGnd
V SEN2
R2
V SEN1
Fb2
R3
5V
R16
R17
Fb1
U1
IRU3007
V5
C19
R19
C15
PGood
PGood
Fault/Rt
Q2
Gate3
R5
V OUT3
1.5V
Fb3
C17
VID0
VID1
R6
VID2
V OUT4
2.5V
V OUT4
C18
VID3
R7
VID4
Fb4
5V
SS
R8
Gnd
C9
Figure 3 - Typical application of IRU3007 for an on-board DC-DC converter providing power
for the Vcore, GTL+, Clock supply as well as an on-board 3.3V I/O supply
for the Deschutes and the next generation processor applications.
Rev. 2.1
08/20/02
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7
IRU3007
IRU3007 APPLICATION PARTS LIST
Ref Desig Description
Q1
MOSFET
Qty
1
Part #
IRL3103S, TO-263 package
Manuf
IR
Q2
MOSFET
1
IRLR024, TO-252 package
IR
Q3
MOSFET
1
IRL3103S, TO-263 package
IR
Q4
MOSFET with Schottky
1
IRL3103D1S, TO-263 package
IR
D1
Diode
1
MBRB1035, TO-263 package
IR
L1
Inductor
1
L=1mH, 5052 core with 4 turns of
L2
Inductor
1
Micro Metal
1.0mm wire
L=4.7mH, 5052 core with 11 turns of
Micro Metal
1.0mm wire
L3
Inductor
1
L=2.7mH, 5052B core with 7 turns of
Micro Metal
C1
Capacitor, Electrolytic
2
6MV1500GX, 1500mF, 6.3V
Sanyo
C2
Capacitor, Electrolytic
1
10MV470GX, 470mF, 10V
Sanyo
C3
Capacitor, Electrolytic
1
10MV1200GX, 1200mF, 10V
Sanyo
C4, 13
Capacitor, Ceramic
2
1000pF, 0603
C5, 10
Capacitor, Ceramic
2
220pF, 0603
C8
Capacitor, Ceramic
1
1mF, 0805
C9, 15, 19 Capacitor, Ceramic
3
1mF, 0603
C14
Capacitor, Electrolytic
2
10MV1200GX, 1200mF, 10V
Sanyo
C16
Capacitor, Electrolytic
6
6MV1500GX, 1500mF, 6.3V
Sanyo
C17
Capacitor, Electrolytic
1
6MV1000GX, 1000mF, 6.3V
Sanyo
C18
Capacitor, Electrolytic
1
6MV150GX, 150mF, 6.3V
Sanyo
4
4.7V, 5%, 1206
Resistor
1
75V, 1%, 0603
R3, 6, 7, 8 Resistor
4
100V, 1%, 0603
R5
Resistor
1
19.1V, 1%, 0603
R9
Resistor
1
1.5KV, 5%, 0603
R10
Resistor
1
10V, 5%, 1206
R12
Resistor
1
3.3KV, 5%, 0603
R16, 17, 21 Resistor
3
2.2KV, 1%, 0603
R19
Resistor
1
220KV, 1%, 0603
R22
Resistor
1
10V, 5%, 0603
1.2mm wire
R1, 5, 13, Resistor
14
R2
8
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Rev. 2.1
08/20/02
IRU3007
TYPICAL APPLICATION
(Dual Layout with HIP6019)
R22
12V
L1
5V
C5
C2
R9
C8
R12
C10
C14
C3
OCSet2
R10
Q1
V12
OCSet1
UGate2
UGate1
Phase2
Phase1
R13
Q3
L3
L2
VOUT2
3.0V - 3.5V
C1
V OUT1
1.8V - 3.5V
R14
C4
C16
Q4
LGate1
D1
R1
C13
R15
R21
PGnd
VSEN2
V SEN1
U1
IRU3007
Fb2
R2
R11
V5/Comp2
Fb1
C11
C19
R4
Q2
C7
C15
R18
R19
PGood
Gate3
R5
VOUT3
1.5V
R17
C12
NC/Comp1
C6
R3
R16
PGood
Fault/Rt
Fb3
VID0
C17
R6
VID1
VID2
VOUT4
2.5V
V OUT4
VID3
R7
C18
VID4
Fb4
Gnd
SS
R8
5V
C20
C9
Figure 4 - Typical application of IRU3007 in a dual layout with HIP6019 for an on-board DC-DC converter
providing power for the Vcore, GTL+, Clock supply as well as an on-board 3.3V I/O supply for the
Deschutes and the next generation processor application.
Components that need to be modified to make the dual layout work for HIP6019 and IRU3007:
Part #
HIP6019
IRU3007
R4
V
O
R11
O
S
S - Short
Rev. 2.1
08/20/02
R18
V
O
C6
V
O
C7
V
O
C9
O
V
C11
V
O
C12
V
O
C19
O
V
C20
V
O
O - Open
V - See IR or Harris parts list for the value
Table 2 - Dual layout component table.
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9
IRU3007
IRU3007 APPLICATION PARTS LIST
Dual Layout with HIP6019
Ref Desig Description
Q1
MOSFET
Qty
1
Part #
IRL3103S, TO-263 package
Manuf
IR
Q2
MOSFET
1
IRLR024, TO-252 package
IR
Q3
MOSFET
1
IRL3103S, TO-263 package
IR
Q4
MOSFET with Schottky
1
IRL3103D1S, TO-263 package
IR
D1
Diode
1
MBRB1035, TO-263 package
IR
L1
Inductor
1
L=1mH, 5052 core with 4 turns of
Micro Metal
1.0 mm wire
L2
Inductor
1
L=4.7mH, 5052 core with 11 turns of
Micro Metal
1.0mm wire
L3
Inductor
1
L=2.7mH, 5052B core with 7 turns of
Micro Metal
1.2mm wire
C1
Capacitor, Electrolytic
2
6MV1500GX, 1500mF, 6.3V
Sanyo
C2
Capacitor, Electrolytic
1
10MV470GX, 470mF, 10V
Sanyo
C3
Capacitor, Electrolytic
1
10MV1200GX, 1200mF, 10V
Sanyo
C4, 13
Capacitor, Ceramic
2
1000pF, 0603
C5, 10
Capacitor, Ceramic
2
220pF, 0603
C6,7,11,12 Capacitor, Ceramic
5
See Table 2, dual layout component
0603 3 5
20
C8
Capacitor, Ceramic
1
1mF, 0805
C9,15,19
Capacitor, Ceramic
3
1mF, 0603
C14
Capacitor, Electrolytic
2
10MV1200GX, 1200mF, 10V
Sanyo
C16
Capacitor, Electrolytic
6
6MV1500GX, 1500mF, 6.3V
Sanyo
C17
Capacitor, Electrolytic
1
6MV1000GX, 1000mF, 6.3V
Sanyo
C18
Capacitor, Electrolytic
1
6MV150GX, 150mF, 6.3V
Sanyo
R1,13,14
Resistor
4
4.7V, 5%, 1206
R2
Resistor
1
75V, 1%, 0603
R3,6,7,8
Resistor
4
100V, 1%, 0603
R4, 18
Resistor
2
See Table 2, dual layout component
R5
Resistor
1
19.1V, 1%, 0603
R9
Resistor
1
1.5KV, 5%, 0603
R10
Resistor
1
10V, 5%, 1206
R11
Resistor
1
0V, 0603
R12
Resistor
1
3.3KV, 5%, 0603
R16,17,21 Resistor
3
2.2KV, 1%, 0603
R19
Resistor
1
220KV, 1%, 0603
R22
Resistor
1
10V, 5%, 0603
15
0603 3 2
10
www.irf.com
Rev. 2.1
08/20/02
IRU3007
APPLICATION INFORMATION
An example of how to calculate the components for the
application circuit is given below.
Assuming, two set of output conditions that this regulator must meet for Vcore:
a) Vo=2.8V , Io=14.2A, DVo=185mV, DIo=14.2A
b) Vo=2V , Io=14.2A, DVo=140mV, DIo=14.2A
Also, the on-board 3.3V supply must be able to provide
10A load current and maintain less than ±5% total output voltage variation.
The regulator design will be done such that it meets the
worst case requirement of each condition.
Output Capacitor Selection
Vcore
The first step is to select the output capacitor. This is
done primarily by selecting the maximum ESR value
that meets the transient voltage budget of the total DVo
specification. Assuming that the regulators DC initial
accuracy plus the output ripple is 2% of the output voltage, then the maximum ESR of the output capacitor is
calculated as:
ESR [
100
= 7mV
14.2
The Sanyo MVGX series is a good choice to achieve
both the price and performance goals. The 6MV1500GX,
1500mF, 6.3V has an ESR of less than 36mV typical.
Selecting 6 of these capacitors in parallel has an ESR
of ≈ 6mV which achieves our low ESR goal.
Other type of Electrolytic capacitors from other manufacturers to consider are the Panasonic FA series or the
Nichicon PL series.
3.3V supply
For the 3.3V supply, since there is not a fast transient
requirement, 2 of the 1500mF capacitors is sufficient.
Reducing the Output Capacitors Using Voltage Level
Shifting Technique
The trace resistance or an external resistor from the output
of the switching regulator to the Slot 1 can be used to
the circuit advantage and possibly reduce the number of
output capacitors, by level shifting the DC regulation point
when transitioning from light load to full load and vice
versa. To accomplish this, the output of the regulator is
typically set about half the DC drop that results from
Rev. 2.1
08/20/02
light load to full load. For example, if the total resistance
from the output capacitors to the Slot 1 and back to the
Gnd pin of the IRU3007 is 5mV and if the total DI, the
change from light load to full load is 14A, then the output
voltage measured at the top of the resistor divider which
is also connected to the output capacitors in this case,
must be set at half of the 70mV or 35mV higher than the
DAC voltage setting. This intentional voltage level shifting during the load transient eases the requirement for
the output capacitor ESR at the cost of load regulation.
One can show that the new ESR requirement eases up
by half the total trace resistance. For example, if the
ESR requirement of the output capacitors without voltage level shifting must be 7mV then after level shifting
the new ESR will only need to be 8.5mV if the trace
resistance is 5mV (7+5/2=9.5). However, one must be
careful that the combined “voltage level shifting” and the
transient response is still within the maximum tolerance
of the Intel specification. To insure this, the maximum
trace resistance must be less than:
Rs [ 2 3
(Vspec - 0.02 3 Vo - DVo)
DI
Where :
Rs = Total maximum trace resistance allowed
Vspec = Intel total voltage spec
Vo = Output voltage
DVo = Output ripple voltage
DI = load current step
For example, assuming:
Vspec = ±140mV = ±0.1V for 2V output
Vo = 2V
DVo = assume 10mV = 0.01V
DI = 14.2A
Then the Rs is calculated to be:
Rs ≤ 2 3
(0.140 - 0.02 3 2 - 0.01)
= 12.6mV
14.2
However, if a resistor of this value is used, the maximum
power dissipated in the trace (or if an external resistor is
being used) must also be considered. For example if
Rs=12.6mV, the power dissipated is:
Io23Rs = 14.22312.6 = 2.54W
This is a lot of power to be dissipated in a system. So, if
the Rs=5mV, then the power dissipated is about 1W,
which is much more acceptable. If level shifting is not
implemented, then the maximum output capacitor ESR
was shown previously to be 7mV which translated to ≈ 6
www.irf.com
11
IRU3007
of the 1500mF, 6MV1500GX type Sanyo capacitors. With
Rs=5mV, the maximum ESR becomes 9.5mV which is
equivalent to ≈ 4 caps. Another important consideration
is that if a trace is being used to implement the resistor,
the power dissipated by the trace increases the case
temperature of the output capacitors which could seriously affect the life span of the output capacitors.
Output Inductor Selection
The output inductance must be selected such that under low line and the maximum output voltage condition,
the inductor current slope times the output capacitor
ESR is ramping up faster than the capacitor voltage is
drooping during a load current step. However, if the inductor is made too small, the output ripple current and
ripple voltage will become too large. One solution to bring
the ripple current down is to increase the switching frequency, however that will be at the cost of reduced efficiency and higher system cost. The following set of formulas are derived to achieve optimum performance without many design iterations.
The maximum output inductance is calculated using the
following equation:
(V IN(MIN) - Vo(MAX) )
L = ESR 3 C 3
(2 3 DI)
Where:
VIN(MIN) = Minimum input voltage
For Vo = 2.8V and DI = 14.2A, we get:
L = 0.006 3 9000 3
(4.75 - 2.8)
= 3.7mH
(2 3 14.2)
T = 1 / Fsw
Vsw = Vsync = Io3RDS
D ≈ (Vo + Vsync) / (V IN - Vsw + Vsync)
TON = D3T
TOFF = T - TON
DIr = (Vo + Vsync)3TOFF / L
DVo = DIr3ESR
In our example for Vo = 2.8V and 14.2 A load, assuming
IRL3103 MOSFET for both switches with maximum on
resistance of 19m V, we have:
T = 1 / 200000 = 5ms
Vsw = Vsync = 14.230.019 = 0.27V
D ≈ (2.8 + 0.27) / (5 - 0.27 + 0.27) = 0.61
TON = 0.6135 = 3.1ms
TOFF = 5 - 3.1 = 1.9ms
DIr = (2.8 + 0.27)31.9 / 3 = 1.94A
DVo = 1.9430.006 = 0.011V = 11mV
Power Component Selection
Vcore
Assuming IRL3103 MOSFETs as power components,
we will calculate the maximum power dissipation as follows:
For high side switch the maximum power dissipation
happens at maximum Vo and maximum duty cycle.
DMAX ≈ (2.8 + 0.27) / (4.75 - 0.27 + 0.27) = 0.65
Assuming that the programmed switching frequency is
set at 200KHz, an inductor is designed using the
Micrometals’ powder iron core material. The summary
of the design is outlined below:
The selected core material is Powder Iron, the selected
core is T50-52D from Micro Metal wound with 8 turns of
#16 AWG wire, resulting in 3mH inductance with ≈ 3 mV
of DC resistance.
PDH = DMAX3Io23RDS(MAX)
PDH = 0.65314.2230.029 = 3.8W
RDS(MAX) =Maximum RDS(ON) of the MOSFET at 1258C
For synch MOSFET, maximum power dissipation happens at minimum Vo and minimum duty cycle.
DMIN ≈ (2 + 0.27) / (5.25 - 0.27 + 0.27) = 0.43
PDS = (1 - DMIN)3Io23RDS(MAX)
PDS = (1 - 0.43)314.22 30.029 = 3.33W
Assuming L=3mH and Fsw=200KHz (switching frequency), the inductor ripple current and the output ripple
voltage is calculated using the following set of equations:
T ≡ Switching Period
D ≡ Duty Cycle
Vsw ≡ High-side MOSFET ON Voltage
RDS ≡ MOSFET On-Resistance
Vsync ≡ Synchronous MOSFET ON Voltage
DIr ≡ Inductor Ripple Current
DVo ≡Output Ripple Voltage
12
3.3V Supply
Again, for high side switch the maximum power dissipation happens at maximum Vo and maximum duty cycle.
The duty cycle equation for non synchronous replaces
the forward voltage of the diode with the Synch MOSFET
on voltage. In equations below:
Vf = 0.5V
DMAX ≈ (3.3 + 0.5) / (4.75 - 0.27 + 0.5) = 0.76
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Rev. 2.1
08/20/02
IRU3007
PDH = DMAX3Io23RDS(MAX)
PDH = 0.76310 30.029 = 2.21W
2
RDS(MAX) = Maximum RDS(ON) of the MOSFET at 1258C
For diode, the maximum power dissipation happens at
minimum Vo and minimum duty cycle.
DMIN ≈ (3.3 + 0.5) / (5.25 - 0.27 + 0.5) = 0.69
To select the heat sink for the LDO MOSFET the first
step is to calculate the maximum power dissipation of
the device and then follow the same procedure as for the
switcher.
Where:
PD = Power Dissipation of the Linear Regulator
IL = Linear Regulator Load Current
PDD = (1 - DMIN)3Io3Vf
For the 1.5V and 2A load:
PDD = (1 - 0.69)31030.5 = 1.55W
Switcher Current Limit Protection
The IRU3007 uses the MOSFET RDS(ON) as the sensing
resistor to sense the MOSFET current and compares to
a programmed voltage which is set externally via a resistor (Rcs) placed between the drain of the MOSFET
and the “CS+” terminal of the IC as shown in the application circuit.
For example, if the desired current limit point is set to
be 22A for the synchronous and 16A for the non synchronous, and from our previous selection, the maximum MOSFET RDS(ON)=19mW, then the current sense
resistor Rcs is calculated as:
PD = (V IN - Vo)3IL
PD = (3.3 - 1.5)32 = 3.6W
Assuming TJ(MAX) = 1258C:
Ts = TJ - PD3(uJC + ucs)
Ts = 125 - 3.63(1.8 + 0.05) = 1188C
With the maximum heat sink temperature calculated in
the previous step, the heat-sink-to-air thermal resistance
(uSA) is calculated as follows:
Assuming TA = 358C:
DT = Ts - TA = 118 - 35 = 838C
Temperature Rise Above Ambient
uSA = DT / PD = 83 / 3.6 = 238C/W
Vcore
The same heat sink as the one selected for the switcher
MOSFETs is also suitable for the 1.5V regulator.
Vcs = ICL3RDS = 2230.019 = 0.418V
Rcs = Vcs / IB = (0.418V) / (200mA) = 2.1KV
Where:
IB=200mA is the internal current setting of the
IRU3007
3.3V supply
Vcs = ICL3RDS = 1630.019 = 0.3V
Rcs = Vcs / IB = (0.3V) / (200mA) = 1.50KV
1.5V, GTL+ Supply LDO Power MOSFET Selection
The first step in selecting the power MOSFET for the
1.5V linear regulator is to select its maximum RDS(ON) of
the pass transistor based on the input to output Dropout
voltage and the maximum load current.
For Vo = 1.5V, VIN = 3.3V and IL = 2A:
RDS(MAX) = (V IN - Vo) / IL = (3.3 - 1.5) / 2 = 0.9V
Note: Since the MOSFETs RDS(ON) increases with temperature, this number must be divided by ≈ 1.5, in order
to find the RDS(ON) max at room temperature. The Motorola
MTP3055VL has a maximum of 0.18V RDS(ON) at room
temperature, which meets our requirement.
2.5V Clock Supply
The IRU3007 provides a complete 2.5V regulator with a
minimum of 200mA current capability. The internal regulator has short circuit protection with internal thermal
shutdown.
1.5V and 2.5V Supply Resistor Divider Selection
Since the internal voltage reference for the linear regulators is set at 1.26V for IRU3007, there is a need to use
external resistor dividers to step up the voltage. The resistor dividers are selected using the following equations:
Vo = (1 + Rt / RB)3VREF
Where:
Rt = Top resistor divider
RB = Bottom resistor divider
VREF = 1.26V typical
For 1.5V supply
Assuming RB = 1KV:
Rt = RB3[(Vo / VREF) - 1]
Rt = 13[(1.5 / 1.26) - 1] = 191V
Rev. 2.1
08/20/02
www.irf.com
13
IRU3007
For 2.5V supply
Assuming RB = 1.02KV:
The bottom resistor, R3 is calculated as follows:
R3 = R23[2 / (Vo - 2)]
Rt = RB3[(Vo / VREF) - 1]
R3 = 753[2 / (3.5 - 2)] = 100V, 1%
Rt = 1.023[(2.5 / 1.26) - 1] = 1KV
Switcher Output Voltage Adjust
Vcore
As it was discussed earlier, the trace resistance from
the output of the switching regulator to the Slot 1 can be
used to the circuit advantage and possibly reduce the
number of output capacitors, by level shifting the DC
regulation point when transitioning from light load to full
load and vice versa. To account for the DC drop, the
output of the regulator is typically set about half the DC
drop that results from light load to full load. For example,
if the total resistance from the output capacitors to the
Slot 1 and back to the Gnd pin of the IRU3007 is 5mV
and if the total DI, the change from light load to full load
is 14A, then the output voltage measured at the top of
the resistor divider which is also connected to the output capacitors in this case, must be set at half of the
70mV or 35mV higher than the DAC voltage setting. To
do this, the top resistor of the resistor divider (R12 in the
application circuit) is set at 100V, and the R19 is calculated. For example, if DAC voltage setting is for 2.8V
and the desired output under light load is 2.835V, then
R19 is calculated using the following formula:
R19 = 1003[VDAC / (Vo - 1.0043VDAC )]
(V)
R19 = 1003[2.8 / (2.835 - 1.00432.800)] = 11.76KV
Select 11.8KV, 1%
Note: The value of the top resistor must not exceed 100V.
The bottom resistor can then be adjusted to raise the
output voltage.
3.3V supply
The loop gain for the non-synchronous switching regulator is intentionally set low to take advantage of the level
shifting technique to reduce the number of output capacitors. Typically there is a 1% drop in the output voltage from light load (discontinuous conduction mode) to
full load (continuous conduction mode) in the 3.3V supply. To account for this, the output voltage is set at 3.5V
typically. The same procedure as for the synchronous is
applied to the non-synch with the exception that the internal voltage reference of this regulator is internally set
at 2V. The following is the set of equations to use for the
output voltage setting for the non-synchronous assuming the Vo=3.5V and R2=75V (R2 is the top resistor in
the application circuit).
14
(V)
Note: The value of the top resistor, R2 must not exceed
100V.
Soft-Start Capacitor Selection
The soft-start capacitor must be selected such that during the start up when the output capacitors are charging
up, the peak inductor current does not reach the current
limit threshold. A minimum of 1mF capacitor insures this
for most applications. An internal 10mA current source
charges the soft-start capacitor which slowly ramps up
the inverting input of the PWM comparator Vfb3. This
insures the output voltage to ramp at the same rate as
the soft-start cap thereby limiting the input current. For
example, with 1mF and the 10mA internal current source
the ramp up rate is (DV/Dt)=I/C=1V/100ms. Assuming
that the output capacitance is 9000mF, the maximum
start up current will be:
I = 9000mF 3 (1V / 100ms) = 0.09A
Input Filter
It is highly recommended to place an inductor between
the system 5V supply and the input capacitors of the
switching regulator to isolate the 5V supply from the
switching noise that occurs during the turn on and off of
the switching components. Typically an inductor in the
range of 1 to 3mH will be sufficient in this type of application.
External Shutdown
The best way to shutdown the IRU3007 is to pull down
on the soft-start pin using an external small signal transistor such as 2N3904 or 2N7002 small signal MOSFET.
This allows slow ramp up of the output, the same as the
power up.
Layout Considerations
Switching regulators require careful attention to the layout of the components, specifically power components
since they switch large currents. These switching components can create large amount of voltage spikes and
high frequency harmonics if some of the critical components are far away from each other and are connected
with inductive traces. The following is a guideline of how
to place the critical components and the connections
between them in order to minimize the above issues.
www.irf.com
Rev. 2.1
08/20/02
IRU3007
Start the layout by first placing the power components:
1) Place the input capacitors C3 and C14 and the high
side MOSFETs, Q1 and Q3 as close to their respective input caps as possible.
9) Place R12 and C10 close to pin 23 and R9 and C5
close to pin 9.
10) Place C9 close to pin 12
Component connections:
2) Place the synchronous MOSFET, Q2 and the Q3 as
close to each other as possible with the intention
that the source of Q3 and drain of the Q4 has the
shortest length. Repeat this for the Q1 and D1 for the
non-synchronous.
Note: It is extremely important that no data bus should
be passing through the switching regulator section specifically close to the fast transition nodes such as PWM
drives or the inductor voltage.
3) Place the snubber R15 and C13 between Q4 and Q3.
Repeat this for R1 and C4 with respect to the Q1 and
D1 for the non-synchronous.
Using the 4 layer board, dedicate one layer to ground,
another layer as the power layer for the 5V, 3.3V, Vcore,
1.5V and if it is possible, for the 2.5V.
4) Place the output inductor , L3 and the output capacitors, C16 between the MOSFET and the load with
output capacitors distributed along the slot 1 and
close to it. Repeat this for L2 with respect to the C1
for the non-synchronous.
Connect all grounds to the ground plane using direct
vias to the ground plane.
5) Place the bypass capacitors, C8 and C19 right next
to 12V and 5V pins. C8 next to the 12V, pin 28 and
C19 next to the 5V, pin 11.
6) Place the IRU3007 such that the pwm output drives,
pins 27 and 25 are relatively short distance from gates
of Q3 and Q4. The non-synch MOSFET must also
be situated such that the distance from its gate to
the pin 1 of the IRU3007 is also relatively short.
7) Place all resistor dividers close to their respective
feedback pins.
8) Place the 2.5V output capacitor, C18 close to the pin
16 of the IC and the 1.5V output capacitor, C17 close
to the Q2 MOSFET.
Use large low inductance/low impedance plane to connect the following connections either using component
side or the solder side.
a) C14 to Q3 Drain and C3 to Q1 drain
b) Q3 Source to Q4 Drain and Q1 Source to D1
cathode
c) Q4 drain to L3 and D1 cathode to L2
d) L3 to the output capacitors, C16 and L2 to the
output capacitors, C1
e) C16 to the load, slot 1
f) Input filter L1 to the C16 and C3
g) C1 to Q2 drain
h) C17 to the Q2 source
I) A minimum of 0.2 inch width trace from the C18
capacitor to pin 16
Connect the rest of the components using the shortest
connection possible.
Note: It is better to place the 1.5V linear regulator
components close to the IRU3007 and then run a
trace from the output of the regulator to the load.
However, if this is not possible then the trace from
the linear drive output pin, pin 18 must be run away
from any high frequency data signals.
It is critical, to place high frequency ceramic capacitors close to the clock chip and termination resistors
to provide local bypassing.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 2.1
08/20/02
www.irf.com
15
IRU3007
(W) SOIC Package
28-Pin Surface Mount, Wide Body
H
A
B
C
R
E
DETAIL-A
PIN NO. 1
L
D
0.516 0.020 x 458
DETAIL-A
K
F
G
SYMBOL
A
B
C
D
E
F
G
I
J
K
L
R
T
I
T
J
28-PIN
MIN
MAX
17.73 17.93
1.27 BSC
0.66 REF
0.36
0.46
7.40
7.60
2.44
2.64
0.10
0.30
0.23
0.32
10.11 10.51
08
88
0.51
1.01
0.63
0.89
2.44
2.64
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
16
www.irf.com
Rev. 2.1
08/20/02
IRU3007
PACKAGE SHIPMENT METHOD
PKG
DESIG
W
PACKAGE
DESCRIPTION
SOIC, Wide Body
1
PIN
COUNT
PARTS
PER TUBE
PARTS
PER REEL
T&R
Orientation
28
27
1000
Fig A
1
1
Feed Direction
Figure A
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 2.1
08/20/02
www.irf.com
17