PHILIPS 74LVCH32244AEC

INTEGRATED CIRCUITS
DATA SHEET
74LVC32244A; 74LVCH32244A
32-bit buffer/line driver; 5 V
input/output tolerant; 3-state
Product specification
File under Integrated Circuits, IC24
1999 Aug 31
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC32244A;
74LVCH32244A
FEATURES
DESCRIPTION
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
The 74LVC(H)32244A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of
these devices in a mixed 3.3 and 5 V environment.
• Wide supply voltage range of 1.2 to 3.6 V
• CMOS low power consumption
• MULTIBYTE flow-trough standard pin-out architecture
• Low inductance multiple power and ground pins for
minimum noise and ground bounce
The 74LVC(H)32244A is a 32-bit non-inverting buffer/line
driver with 3-state outputs. The 3-state outputs are
controlled by the output enable inputs 1OE and 2OE.
A HIGH on input nOE causes the outputs to assume a
high-impedance OFF-state.
• Direct interface with TTL levels
• Bus hold on data inputs (74LVCH32244A only)
• Typical output ground bounce voltage:
VOLP <0.8 V at VCC = 3.3 V; Tamb = 25 °C
To ensure the high-impedance state during power-up or
power-down, input nOE should be tied to VCC through a
pull-up resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
• Typical output VOH undershoot voltage:
VOHV >2 V at VCC = 3.3 V; Tamb = 25 °C
• Power-off disabled outputs, permitting live insertion
• Plastic fine-pitch ball grid array package.
The 74LVCH32244A bus hold data input circuit eliminates
the need for external pull-up resistors to hold unused or
floating data inputs at a valid logic level (see Fig.3).
QUICK REFERENCE DATA
Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
tPHL/tPLH
propagation delay nAn to nYn
CI
input capacitance
CPD
power dissipation capacitance per buffer
CONDITIONS
3.0
5.0
pF
VI = GND to VCC; note 1
25
pF
1. CPD is used to determine the dynamic power dissipation (PD in µW).
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
1999 Aug 31
2
UNIT
CL = 50 pF; VCC = 3.3 V
Note
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
TYPICAL
ns
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC32244A;
74LVCH32244A
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nOE
nAn
nYn
L
L
L
L
H
H
H
X
Z
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
74LVC32244AEC
TEMPERATURE
RANGE
PINS
−40 to +85 °C
96
LFBGA96
plastic
SOT536-1
96
LFBGA96
plastic
SOT536-1
74LVCH32244AEC
PACKAGE MATERIAL
PINNING
SYMBOL
1999 Aug 31
DESCRIPTION
nAn
data inputs
nYn
data outputs
GND
ground (0 V)
nOE
3-state output enable inputs (active LOW)
VCC
DC supply voltage
3
CODE
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC32244A;
74LVCH32244A
MNA471
handbook, full pagewidth
6
1A1
1A3
2A1
2A3
3A1
3A3
4A1
4A2
5A1
5A3
6A1
6A3
7A1
7A3
8A1
8A2
5
1A0
1A2
2A0
2A2
3A0
3A2
4A0
4A3
5A0
5A2
6A0
6A2
7A0
7A2
8A0
8A3
4
2OE GND VCC GND GND VCC GND 3OE 6OE GND VCC GND GND VCC GND 7OE
3
1OE GND VCC GND GND VCC GND 4OE 5OE GND VCC GND GND VCC GND 8OE
2
1Y0
1Y2
2Y0
2Y2
3Y0
3Y2
4Y0
4Y3
5Y0
5Y2
6Y0
6Y2
7Y0
7Y2
8Y0
8Y3
1
1Y1
1Y3
2Y1
2Y3
3Y1
3Y3
4Y1
4Y2
5Y1
5Y3
6Y1
6Y3
7Y1
7Y3
8Y1
8Y2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Fig.1 Pin configuration.
1A0
handbook, full pagewidth
1Y0
1A1
1Y1
1A2
1Y2
1A3
1Y3
A5
A6
B5
B6
A3
C5
C6
D5
D6
A4
A2
E5
A1
E6
B2
F5
B1
F6
1OE
H4
2A0
2Y0
2A1
2Y1
2A2
2Y2
2A3
2Y3
2OE
C2
G5
C1
G6
D2
H6
D1
H5
H3
3A0
3Y0
3A1
3Y1
3A2
3Y2
3A3
3Y3
E2
J5
E1
J6
F2
K5
F1
K6
3OE
J3
4A0
4Y0
4A1
4Y1
4A2
4Y2
4A3
4Y3
G2
L5
G1
L6
H1
M5
H2
M6
4OE
J4
5A0
5Y0
5A1
5Y1
5A2
5Y2
5A3
5Y3
J2
N5
J1
N6
K2
P5
K1
P6
5OE
T4
6A0
6Y0
6A1
6Y1
6A2
6Y2
6A3
6Y3
6OE
L2
R5
L1
R6
M2
T6
M1
T5
T3
7A0
7Y0
7A1
7Y1
7A2
7Y2
7A3
7Y3
N2
N1
P2
P1
7OE
8A0
8Y0
8A1
8Y1
8A2
8Y2
8A3
8Y3
R2
R1
T1
T2
8OE
MNA472
Fig.2 Logic symbol.
1999 Aug 31
4
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
handbook, halfpage
74LVC32244A;
74LVCH32244A
VCC
data
input
to internal circuit
MNA473
Fig.3 Bus hold circuit.
1999 Aug 31
5
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC32244A;
74LVCH32244A
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN.
VCC
DC supply voltage
VI
DC input voltage
VO
DC output voltage range;
for max. speed performance
for low-voltage applications
2.7
MAX.
3.6
V
1.2
3.6
V
0
5.5
V
output HIGH or LOW state
0
VCC
V
3-state
0
5.5
V
Tamb
operating ambient temperature
see DC and AC characteristics
per device
−40
+85
°C
tr,tf (∆t/∆f)
input rise and fall times ratio
VCC = 1.2 to 2.7 V
0
20
ns/V
VCC = 2.7 to 3.6 V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VCC
DC supply voltage
V
VI
DC input voltage
note 1
−0.5
+6.5
V
IIK
DC input diode current
VI < 0
−
−50
mA
IOK
DC output diode current
VO > VCC or VO < 0; note 1
−
±50
mA
VO
DC output voltage
output HIGH or LOW state; note 1 −0.5
IO
DC output source or sink current
ICC, IGND
DC VCC or GND current
Tstg
storage temperature
PD
power dissipation per packages
VCC + 0.5 V
output 3-state; note 1
−0.5
+6.5
V
VO = 0 to VCC
−
±50
mA
−
±100
mA
−65
+150
°C
−
1000
mW
temperature range:
−40 to +85 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 70 °C the value of PD derates linearly with 1.8 mW/K.
1999 Aug 31
6
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC32244A;
74LVCH32244A
DC CHARACTERISTICS
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
Tamb (°C)
TEST CONDITIONS
SYMBOL
OTHER
VIH
−40 to +85
PARAMETER
HIGH-level input voltage
VCC (V)
−
−
−
−
−
−
GND
2.7 to 3.6 −
−
0.8
1.2
VOH
VOL
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
TYP.(1) MAX.
MIN.
VCC
2.7 to 3.6 2.0
VIL
UNIT
1.2
V
V
VI = VIH or VIL
IO = −12 mA
2.7
VCC − 0.5 −
−
IO = −100 µA
3.0
VCC − 0.2 VCC
−
IO = −18 mA
3.0
VCC − 0.6 −
−
IO = −24 mA
3.0
VCC − 0.8 −
−
IO = 12 mA
2.7
−
−
0.40
IO = 100 µA
3.0
−
−
0.20
IO = 24 mA
V
VI = VIH or VIL
V
3.0
−
−
0.55
II
input leakage current
VI = 5.5 V or GND;
note 2
3.6
−
±0.1
±5
µA
IOZ
3-state output OFF-state current
VI = VIH or VIL;
VO = 5.5 V or GND
3.6
−
0.1
±5
µA
Ioff
power off leakage supply
VI or VO = 5.5 V
0.0
−
0.1
±10
µA
ICC
quiescent supply current
VI = VCC or GND; IO = 0
3.6
−
0.1
40
µA
∆ICC
additional quiescent supply
current per input pin
VI = VCC − 0.6 V; IO = 0
2.7 to 3.6 −
5
500
µA
IBHL
bus hold LOW sustaining current
VI = 0.8 V;
notes 3, 4 and 5
3.0
75
−
−
µA
IBHH
bus hold HIGH sustaining current VI = 2.0 V;
notes 3, 4 and 5
3.0
−75
−
−
µA
IBHLO
bus hold LOW overdrive current
notes 3, 4 and 6
3.6
500
−
−
µA
IBHHO
bus hold HIGH overdrive current
notes 3, 4 and 6
3.6
−500
−
−
µA
Notes
1. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
2. For bus hold parts the bus hold circuit is switched off when VI exceeds VCC allowing 5.5 V on the input terminal.
3. Valid for data inputs of bus hold parts only (LVCH32xxx-A).
4. For data inputs only. Control inputs do not have a bus hold circuit.
5. The specified sustaining current at the data input holds the input below the specified VI level.
6. The specified overdrive current at the data input forces the data input to the opposite logic input level.
1999 Aug 31
7
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC32244A;
74LVCH32244A
AC CHARACTERISTICS
Ground = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
Tamb = −40 to +85 °C
TEST CONDITIONS
SYMBOL
PARAMETER
WAVEFORMS
tPHL/tPLH
tPZH/tPZL
tPHZ/tPLZ
propagation delay
nAn to nYn
see Figs 4 and 6
3-state output enable time
nOE to nYn
see Figs 5 and 6
3-state output disable time
nOE to nYn
see Figs 5 and 6
VCC (V)
MIN.
1.5
−
5.5
3.0 to 3.6
1.5
3.0
4.5
2.7
1.5
−
6.5
3.0 to 3.6
1.5
3.5
5.5
2.7
1.5
−
6.2
3.0 to 3.6
1.5
3.7
5.2
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
AC WAVEFORMS
handbook, halfpage VI
VM
GND
t PHL
t PLH
VOH
nYn
OUTPUT
VM
VOL
MNA474
VM = 1.5 V at VCC ≥ 2.7 V or
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.4 Input nAn to output nYn propagation delay times.
1999 Aug 31
8
UNIT
MAX.
2.7
Notes
nAn
INPUT
TYP.(1)
ns
ns
ns
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC32244A;
74LVCH32244A
VI
handbook, full pagewidth
nOE INPUT
VM
GND
t PLZ
t PZL
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
t PZH
t PHZ
VOH
VY
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
VM
outputs
enabled
outputs
enabled
outputs
disabled
MNA478
VM = 1.5 V at VCC ≥ 2.7 V or
VM = 0.5 × VCC at VCC < 2.7 V;
VX = VOL + 0.3 V at VCC ≥ 2.7 V or
VX = VOL + 0.1 V at VCC < 2.7 V;
VY = VOH − 0.3 V at VCC ≥ 2.7 V or
VY = VOH − 0.1 V at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 3-state enable and disable times.
S1
handbook, full pagewidth
VCC
PULSE
GENERATOR
VI
RL
500 Ω
VO
2 × VCC
open
GND
D.U.T.
CL
50 pF
RT
RL
500 Ω
MNA479
TEST
S1
VCC
Definitions for test circuit:
RL = load resistor.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance
Zo of the pulse generator.
VI
tPLH/tPHL
open
tPLZ/tPZL
2 × VCC
< 2.7 V
tPHZ/tPZH
GND
2.7 to 3.6 V 2.7 V
VCC
Fig.6 Load circuitry for switching times.
1999 Aug 31
9
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC32244A;
74LVCH32244A
PACKAGE OUTLINE
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm
SOT536-1
D
ball A1
index area
A2
A
E
A1
detail X
b
A
∅w M
ZD
e
y
v A
ZE
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
e
X
1 2 3 4 5 6
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
b
D
E
e
v
w
y
ZD
ZE
mm
1.5
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
0.8
0.2
0.15
0.1
0.93
0.58
0.93
0.58
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
5
10 mm
scale
EUROPEAN
PROJECTION
ISSUE DATE
98-11-25
99-06-03
SOT536-1
1999 Aug 31
0
10
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
SOLDERING
74LVC32244A;
74LVCH32244A
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Aug 31
11
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC32244A;
74LVCH32244A
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Aug 31
12
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
NOTES
1999 Aug 31
13
74LVC32244A;
74LVCH32244A
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
NOTES
1999 Aug 31
14
74LVC32244A;
74LVCH32244A
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
NOTES
1999 Aug 31
15
74LVC32244A;
74LVCH32244A
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India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
SCA 67
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245004/01/pp16
Date of release: 1999
Aug 31
Document order number:
9397 750 06258