IRF IR3502MTRPBF

IR3502
DATA SHEET
XPHASE3TM CONTROL IC
DESCRIPTION
TM
The IR3502 control IC combined with an XPHASE3 Phase IC provides a full featured and flexible way to
implement a complete VR11.0 and VR11.1 power solution. The IR3502 provides overall system control
TM
and interfaces with any number of Phase ICs, each driving and monitoring a single phase. The XPhase3
architecture results in a power supply that is smaller, less expensive, and easier to design while providing
higher efficiency than conventional approaches.
FEATURES
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1 to X phase operation with matching Phase IC
0.5% overall system set point accuracy
Daisy-chain digital phase timing provides accurate phase interleaving without external components
Programmable 250kHz to 9MHz clock oscillator frequency provides per phase switching frequency of
250kHz to 1.5MHz
Programmable Dynamic VID Slew Rate
Programmable VID Offset or No Offset
Programmable Load Line Output Impedance
High speed error amplifier with wide bandwidth of 30MHz and fast slew rate of 10V/us
Programmable constant converter output current limit during soft start
Hiccup over current protection with delay during normal operation
Central over voltage detection and latch with programmable threshold and communication to phase ICs
Over voltage signal output to system with overvoltage detection during powerup and normal operation
Load current reporting
Single NTC thermistor compensation for correct current reporting, OC Threshold, and Droop
Detection and protection of open remote sense line
Open control loop protection
IC bias linear regulator controller
Programmable VRHOT function monitors temperature of power stage through a NTC thermistor
Remote sense amplifier with true converter voltage sensing
Simplified VR Ready (VRRDY) output provides indication of proper operation
Small thermally enhanced 32L 5mm x 5mm MLPQ package
RoHS compliant
ORDERING INFORMATION
Device
IR3502MTRPBF
* IR3502MPBF
•
Package
32 Lead MLPQ
(5 x 5 mm body)
32 Lead MLPQ
(5 x 5 mm body)
Order Quantity
3000 per reel
100 piece strips
Samples only
Page 1 of 39
July 28, 2009
IR3502
CLKOUT
PHSIN
26
PHSOUT
27
28
VCCL
29
IIN
30
VCCLDRV
31
25
19
18
EAOUT
VN
FB
EAOUT
VSETPT
24
23
22
21
20
VDAC_BUFF
VO
17
VDRP
VDRP
17
16
15
14
13
12
11
9
10
16
FB
15
14
VO
VOSEN+
IIN
VOSEN-
VID1
18
VOSEN+
VSETPT
VDAC
IR3502
VOSEN-
19
GND
SS/DEL
HOTSET
20
ROSC
VRHOT
21
VRRDY
32
22
OCSET
VID2
VID0
23
ENABLE
CLKOUT
IMON
25
26
PHSIN
PHSOUT
27
28
VCCL
29
VCCLFB
30
VCCLDRV
31
VRRDY
VID3
9
8
IR3500
13
7
VDAC
12
6
SS/DEL
VID4
HOTSET
5
VID5
1
VID7
2
VID6
3
VID5
4
VID4
5
VID3
6
VID2
7
VID1
8
VID0
24
LGND
ROSC / OVP
11
4
VID6
VRHOT
3
10
2
VID7
ENABLE
1
VIDSEL
32
APPLICATION CIRCUIT
Figure 1 – PIN difference between IR3500 and IR3502
12V
+12V
Q2
VCCL
CVCCL
RVCCLDRV
IIN
PHSIN
PHSOUT
VRRDY
RMON
CLKOUT
26
25
CLKOUT
PHSOUT
28
27
PHSIN
IIN
VCCL
29
30
31
VDAC
IR3502
VID3
VSETPT
VN
VDRP
24
23
ROSC
CSS/DEL
22
21
RVDAC
20
RVSETPT
19
RTCMP3
CVDAC
VDAC
18
17
RTCMP1
RTHERM
RTCMP2
16
15
ENABLE
14
VID0
EAOUT
VID1
FB
VDAC_BUFF
VO
VID2
VOSEN+
8
VCCLDRV
IMON
7
SS/DEL
VID4
9
VID0
6
VID5
VOSEN-
VID1
5
GND
ROSC
13
VID2
4
VID6
HOTSET
VID3
3
VID7
12
VID4
2
11
VID5
1
VRHOT
VID6
ENABLE
VID7
VRRDY
RMON1
VOSEN-
10
CMON
32
IOUT
RDRP
VRHOT
RHOTSET1
RHOTSET3
CHOTSET
RFB1
RHOTSET2
RFB
CFB1
CEA
REA
EAOUT
CEA1
VOSEN+
VOSEN-
Figure 2 – IR3502 Application Circuit
Page 2 of 39
July 28, 2009
IR3502
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications are not implied.
o
Operating Junction Temperature……………..0 to 150 C
o
o
Storage Temperature Range………………….-65 C to 150 C
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
o
Reflow Temperature…………………………….260 C
PIN #
PIN NAME
VMAX
VMIN
ISOURCE
ISINK
1-8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VID7-0
ENABLE
VRHOT
HOTSET
VOSENVOSEN+
VO
FB
EAOUT
VDRP
VN
VDAC_BUFF
VSETPT
VDAC
SS/DEL
ROSC/OVP
LGND
CLKOUT
7.5V
3.5V
7.5V
7.5V
1.0V
7.5V
7.5V
7.5V
7.5V
7.5V
7.5V
3.5V
3.5V
3.5V
7.5V
7.5V
n/a
7.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
n/a
-0.3V
1mA
1mA
1mA
1mA
5mA
5mA
35mA
1mA
35mA
35mA
1mA
1mA
1mA
1mA
1mA
1mA
20mA
100mA
1mA
1mA
50mA
1mA
1mA
1mA
5mA
1mA
5mA
1mA
1mA
35mA
1mA
1mA
1mA
1mA
1mA
100mA
26
27
28
PHSOUT
PHSIN
VCCL
7.5V
7.5V
7.5V
-0.3V
-0.3V
-0.3V
10mA
1mA
1mA
10mA
1mA
20mA
29
IIN
7.5V
-0.3V
1mA
1mA
30
VCCLDRV
10V
-0.3V
1mA
50mA
31
VRRDY
VCCL + 0.3V
-0.3V
1mA
20mA
32
IMON
3.5V
-0.3V
25mA
1mA
Page 3 of 39
July 28, 2009
IR3502
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 8V≤Vin≤16V, VCCL = 6.8V±3.4%, -0.3V ≤ VOSEN- ≤
o
o
0.3V, 0 C ≤ TJ ≤ 100 C, 7.75KΩ ≤ ROSC ≤ 50.0 KΩ, CSS/DEL = 0.1µF +/-10%.
PARAMETER
VDAC Reference
System Set-Point Accuracy
TEST CONDITION
MIN
VID ≥ 1V
0.8V ≤ VID < 1V
0.5V ≤ VID < 0.8V
VSETPT connected to VDAC
Source & Sink Currents
VIDx Input Threshold
VIDx Input Bias Current
0V≤V(VIDx)≤2.5V.
VIDx OFF State Blanking Delay Measure time till VRRDY drives low
Oscillator
ROSC Voltage
CLKOUT High Voltage
I(CLKOUT)= -10 mA, measure V(VCCL)
– V(CLKOUT).
CLKOUT Low Voltage
I(CLKOUT)= 10 mA
PHSOUT Frequency
ROSC = 50.0 KΩ
PHSOUT Frequency
ROSC = 24.5 KΩ
PHSOUT Frequency
ROSC = 7.75 KΩ
PHSOUT High Voltage
I(PHSOUT)= -1 mA, measure V(VCCL)
– V(PHSOUT)
PHSOUT Low Voltage
I(PHSOUT)= 1 mA
PHSIN Threshold Voltage
Compare to V(VCCL)
VDAC Buffer Amplifier
Input Offset Voltage
V(VDAC_BUFF) – V(VDAC), 0.5V ≤
V(VDAC) ≤ 1.6V, < 1mA load
Source Current
0.5V ≤ V(VDAC) ≤ 1.6V
Sink Current
0.5V ≤ V(VDAC) ≤ 1.6V
Unity Gain Bandwidth
Note 1
Slew Rate
Note 1
Thermal Compensation Amplifier
Output Offset Voltage
0V ≤ V(IIN) – V(VDAC) ≤ 1.6V, 0.5V ≤
V(VDAC) ≤ 1.6V, Req/R2 = 2
Source Current
0.5V ≤ V(VDAC) ≤ 1.6V
Sink Current
0.5V ≤ V(VDAC) ≤ 1.6V
Unity Gain Bandwidth
Note 1, Req/R2 = 2
Slew Rate
Note 1
Current Report Amplifier
Output Offset Voltage
V(VDRP)–V(VDAC) = 0,225,450,900mV
Page 4 of 39
TYP
MAX
UNIT
-0.5
-5
-8
30
500
-1
0.5
%
mV
mV
44
600
0
1.3
0.5
+5
+8
58
700
1
2.1
0.570
0.595
225
450
1.35
250
500
1.50
µA
mV
µA
µs
0.620
1
V
V
1
275
550
1.65
1
V
kHz
kHz
MHz
V
V
%
30
50
1
70
-5
0
9
mV
0.3
3.5
0.44
13
3.5
1.5
0.6
20
mA
mA
MHz
-10
0
10
mV
3
0.3
2
8
0.4
4.5
5.5
15
0.5
7
mA
mA
MHz
52
67
37
V/µs
V/µs
July 28, 2009
mV
IR3502
PARAMETER
TEST CONDITION
Source Current
0.5V ≤ V(IMON) ≤ 0.9V
Sink Resistance
0.5V ≤ V(IMON) ≤ 0.9V
Unity Gain Bandwidth
Note 1
Input Filter Time Constant
Max Output Voltage
Soft Start and Delay
Start Delay (TD1)
Soft Start Time (TD2)
VID Sample Delay (TD3)
VRRDY Delay (TD4 + TD5)
OC Delay Time
V(VDRP) – V(DACBUFF) = 1.67 mV
SS/DEL to FB Input Offset With FB = 0V, adjust V(SS/DEL) until
Voltage
EAOUT drives high
Charge Current
Discharge Current
Charge/Discharge Current Ratio
Charge Voltage
Relative to Charge Voltage, SS/DEL rising
Delay Comparator Threshold
Relative to Charge Voltage, SS/DEL falling
Delay Comparator Threshold
Delay Comparator Input Filter
Delay Comparator Hysteresis
VID Sample Delay Comparator
Threshold
Discharge Comp. Threshold
Remote Sense Differential Amplifier
Unity Gain Bandwidth
Note 1
Input Offset Voltage
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Sink Current
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Source Current
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Slew Rate
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
VOSEN+ Bias Current
0.5 V < V(VOSEN+) < 1.6V
VOSEN- Bias Current
-0.3V ≤ VOSEN- ≤ 0.3V, All VID Codes
High Voltage
V(VCCL) – V(VO)
Low Voltage
V(VCCL)=7V
Error Amplifier
Input Offset Voltage
Measure V(FB) – V(VSETPT). Note 2
FB Bias Current
VSETPT Bias Current
ROSC= 24.5 KΩ
DC Gain
Note 1
Bandwidth
Note 1
Slew Rate
Note 1
Sink Current
Source Current
Maximum Voltage
Measure V(VCCL) – V(EAOUT)
Page 5 of 39
MIN
5
5
1.04
TYP
9
10
1
1
1.09
1.145
UNIT
mA
kΩ
MHz
µs
V
1.0
0.8
0.3
0.5
75
0.7
2.9
2.2
1.2
1.2
125
1.4
3.5
3.25
3.0
2.3
300
1.9
ms
ms
ms
ms
us
V
35.0
2.5
10
3.6
50
85
70.0
6.5
16
4.2
125
160
µA
µA
µA/µA
V
mV
mV
10
2.8
52.5
4.5
12
4.0
80
120
5
30
3.0
60
3.2
µs
mV
V
150
200
275
mV
3.0
-3
0.4
3
2
6.4
0
1
9
4
MHz
mV
mA
mA
V/us
1.5
160
2
9.0
3
2
20
8
100
275
2.5
50
-1
-1
23.00
100
20
7
0.40
5
500
MAX
15
17
0
1
0
1
24.25 25.50
110
120
30
40
12
20
0.85
1.00
8
12
780
950
July 28, 2009
µA
µA
V
mV
mV
µA
µA
dB
MHz
V/µs
mA
mA
mV
IR3502
PARAMETER
Minimum Voltage
Open Voltage Loop Detection
Threshold
Open Voltage Loop Detection
Delay
Enable Input
VR 11 Threshold Voltage
VR 11 Threshold Voltage
VR 11 Hysteresis
Bias Current
Blanking Time
TEST CONDITION
MIN
Measure V(VCCL)- V(EAOUT), Relative
to Error Amplifier maximum voltage.
Measure PHSOUT pulse numbers from
V(EAOUT) = V(VCCL) to VRRDY = low.
125
ENABLE rising
ENABLE falling
825
775
25
-5
75
850
800
50
0
250
875
825
75
5
400
mV
mV
mV
-40
-25
2
1.17
4096
2048
1024
-10
mV
0V ≤ V(ENABLE) ≤ 3.3V
Noise Pulse < 100ns will not register an
ENABLE state change. Note 1
Over-Current Comparator
Input Offset Voltage
1V ≤ V(IIN) ≤ 3.3V
Input Filter Time Constant
Over-Current Threshold
VDRP-VDAC_BUFF
Over-Current Delay Counter
ROSC = 7.75 KΩ (PHSOUT=1.5MHz)
Over-Current Delay Counter
ROSC = 15.0 KΩ (PHSOUT=800kHz)
Over-Current Delay Counter
ROSC = 50.0 KΩ (PHSOUT=250kHz)
Over-Current Limit Amplifier
Input Offset Voltage
Transconductance
Note 1
Sink Current
Unity Gain Bandwidth
Note 1
Over Voltage Protection (OVP) Comparators
Threshold at Power-up
Measure at 1.5V VCCLDRV
Threshold during Normal
Compare to V(VDAC)
Operation
OVP Release Voltage during
Compare to V(VDAC)
Normal Operation
Threshold during Dynamic VID
down
Dynamic VID Detect Comparator
Threshold
Propagation Delay to IIN
Measure time from V(VO) > V(VDAC)
(250mV overdrive) to V(IIN) transition to
> 0.9 * V(VCCL).
IIN Pull-up Resistance
Propagation Delay to OVP
Measure time from V(VO) > V(VDAC)
(250mV overdrive) to V(ROSC/OVP)
transition to >1V.
OVP High Voltage
Measure V(VCCL)-V(ROSC/OVP)
OVP Power-up High Voltage
ROSC = 7.75 KΩ. Measure
V(VCCLDRV)-V(ROSC/OVP) @ 1.5V
OVP Power-up High Voltage
ROSC = 24.5 KΩ. Measure
V(VCCLDRV)-V(ROSC/OVP) @ 1.5V
Page 6 of 39
TYP
120
300
MAX
250
600
8
1.07
-10
0.50
35
0.75
UNIT
mV
mV
Pulses
0
1.00
55
2.00
1.27
10
1.75
75
3.00
µA
ns
µs
V
Cycle
Cycle
Cycle
mV
mA/V
uA
kHz
1.1
105
1.21
125
1.30
145
V
mV
-13
3
20
mV
1.70
1.73
1.75
V
25
50
75
mV
90
180
ns
5
90
0
.100
0
.240
15
180
Ω
ns
1.2
.375
V
V
0.2
July 28, 2009
IR3502
PARAMETER
VRRDY Output
Output Voltage
Leakage Current
Open Sense Line Detection
Sense Line Detection Active
Comparator Threshold Voltage
Sense Line Detection Active
Comparator Offset Voltage
VOSEN+ Open Sense Line
Comparator Threshold
VOSEN- Open Sense Line
Comparator Threshold
Sense Line Detection Source
Currents
VRHOT Comparator
Threshold Voltage
HOTSET Bias Current
Hysteresis
Output Voltage
VRHOT Leakage Current
VCCL Regulator Amplifier
VCCL Output Voltage
VCCLDRV Sink Current
UVLO Start Threshold
UVLO Stop Threshold
Hysteresis
General
VCCL Supply Current
TEST CONDITION
MIN
TYP
MAX
UNIT
150
0
300
10
mV
150
200
250
mV
30
55
80
mV
87.5
90.0
92.5
%
0.36
0.40
0.44
V
200
500
700
uA
1.584
-1
75
1.600
0
100
150
0
1.616
1
125
400
10
V
6.576
10
6.12
5.168
0.85
6.8
30
6.392
5.44
0.95
7.031
6.664
5.712
1.05
V
mA
V
V
V
4
8
12
mA
I(VRRDY) = 4mA
V(VRRDY) = 5.5V
V(VO) < [V(VOSEN+) – V(LGND)] / 2
Compare to V(VCCL)
V(VO) = 100mV
I(VRHOT) = 30mA
V(VRHOT) = 5.5V
Compare to V(VCCL)
Compare to V(VCCL)
Note 1: Guaranteed by design, but not tested in production
Note 2: VDAC Output is trimmed to compensate for Error Amplifier input offsets errors
Page 7 of 39
July 28, 2009
µA
µA
mV
mV
µA
IR3502
PIN DESCRIPTION
PIN#
1-8
9
PIN SYMBOL
VID7-0
ENABLE
10
VRHOT
11
HOTSET
12
13
14
15
16
17
VOSENVOSEN+
VO
FB
EAOUT
VDRP
18
19
20
VN
VDAC_BUFF
VSETPT
21
VDAC
22
SS/DEL
23
ROSC/OVP
24
25
LGND
CLKOUT
26
PHSOUT
27
28
29
PHSIN
VCCL
IIN
30
VCCLDRV
31
VRRDY
32
IMON
Page 8 of 39
PIN DESCRIPTION
Inputs to VID D to A Converter.
Enable input. A logic low applied to this pin puts the IC into fault mode. Do not float
this pin as the logic state will be undefined.
Open collector output of the VRHOT comparator which drives low if HOTSET pin
voltage is lower than 1.6V. Connect external pull-up.
A resistor divider including thermistor senses the temperature, which is used for
VRHOT comparator.
Remote sense amplifier input. Connect to ground at the load.
Remote sense amplifier input. Connect to output at the load.
Remote sense amplifier output. Used for OV detection
Inverting input to the Error Amplifier.
Output of the error amplifier.
Buffered, scaled and thermally compensated IIN signal. Connect an external RC
network to FB to program converter output impedance.
Node for DCR thermal compensation network.
Buffered VDAC.
Error amplifier non-inverting input. Converter output voltage can be decreased from
the VDAC voltage with an external resistor connected between VDAC and this pin
(there is an internal sink current at this pin).
Regulated voltage programmed by the VID inputs. Connect an external RC network
to LGND to program dynamic VID slew rate and provide compensation for the
internal buffer amplifier.
Programs converter startup and over current protection delay timing. It is also used
to compensate the constant output current loop during soft start. Connect an
external capacitor to LGND to program.
Connect a resistor to LGND to program oscillator frequency and VSETPT bias
current. Oscillator frequency equals switching frequency per phase. The pin voltage
is 0.6V during normal operation and higher than 1.6V if an over-voltage condition is
detected.
Local Ground for internal circuitry and IC substrate connection.
Clock frequency is the switching frequency multiplied by phase number. Connect to
CLKIN pins of phase ICs.
Phase clock output at switching frequency per phase. Connect to PHSIN pin of the
first phase IC.
Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.
Voltage regulator and IC power input. Connect a decoupling capacitor to LGND.
Average current input from the phase IC(s). This pin is also used to communicate
over voltage condition to phase ICs.
Output of the VCCL regulator error amplifier to control external transistor. The pin
senses 12V power supply through a resistor.
Open collector output that drives low during startup and under any external fault
condition. Connect external pull-up.
Voltage at this pin is proportional to load current.
July 28, 2009
IR3502
SYSTEM THEORY OF OPERATION
System Description
The system consists of one control IC and a scalable array of phase converters, each requiring one phase IC. The
control IC communicates with the phase ICs using three digital buses, i.e., CLOCK, PHSIN, PHSOUT and three
analog buses, i.e., VDAC, EA, IIN. The digital buses are responsible for switching frequency determination and
accurate phase timing control without any external component. The analog buses are used for PWM control and
current sharing among interleaved phases. The control IC incorporates all the system functions, i.e., VID, CLOCK
signals, error amplifier, fault protections, current monitor, etc. The Phase IC implements the functions required by
each phase of the converter, i.e., the gate drivers, PWM comparator and latch, over-voltage protection, Phase
disable circuit, current sensing and sharing, etc.
GATE DRIVE
VOLTAGE
CONTROL IC
VIN
PHSOUT
PHASE IC
CLOCK GENERATOR
CLKOUT
VCC
CLKIN
CLK Q
VCCH
D
PHSOUT
1
PHSIN
2
RESET
U246
DOMINANT
D
PWM
COMPARATOR
GATEH
Q
CBST
R
VOUT
COUT
-
EAIN
+
VOSNS+
SW
OFF
CLK Q
3
PHSIN
VID6
VCCL
DFFRH
GND
PWM LATCH
GATEL
ENABLE
+
+
VID6
-
REMOTE SENSE
AMPLIFIER
VID6
-
PSI
CURRENT
SENSE
AMPLIFIER
ISHARE
-
VID6
VID6
-
+
+
-
3K
RCOMP
RFB
CCOMP
FB
RVSETPT
CFB
RCS
PHSOUT
PHASE IC
RDRP
CDRP
IMON
VCC
CLK Q
CLKIN
D
VDAC
1
2
VCCH
RESET
U248
DOMINANT
PHSIN
GATEH
D
VN
PWM
COMPARATOR
Q
EAIN
CBST
VID6
CLK Q
R
VDRP
+
SW
OFF
3
Thermal
Compensation
+
VDRP
AMP
CCS
CSIN-
DACIN
RDRP1
VSETPT
IVSETPT
CSIN+
+
VID6
VID6 +
RFB1
-
+
-
+
EAOUT
+
IROSC
PSI
SHARE ADJUST
ERROR AMPLIFIER
LGND
VDAC
VOSNS-
-
VDAC
ERROR
AMPLIFIER
PGND
OFF
+
RAMP
DISCHARGE
CLAMP
VO
BODY
BRAKING
COMPARATOR
DFFRH
VCCL
PWM LATCH
-
RTHRM
ENABLE
IIN
+
VID6
-
RAMP
DISCHARGE
CLAMP
GATEL
BODY
BRAKING
COMPARATOR
VID6
PGND
OFF
-
+
PSI
PSI
SHARE ADJUST
ERROR AMPLIFIER
CURRENT
SENSE
AMPLIFIER
+
-
+
CSIN+
VID6
VID6 +
+
DACIN
CCS
RCS
-
-
3K
VID6
VID6
+
ISHARE
CSIN-
Figure 3 System Block Diagram
PWM Control Method
TM
The PWM block diagram of the XPhase3 architecture is shown in Figure 3. Feed-forward voltage mode control
with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the control IC is
used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The
PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage.
The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace
voltage drop related to changes in load current.
Frequency and Phase Timing Control
The oscillator is located in the control IC and the system clock frequency is programmable from 250kHz to 9MHZ by
an external resistor. The control IC system clock signal CLKOUT is connected to CLKIN of all the phase ICs. The
phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output PHSOUT is
Page 9 of 39
July 28, 2009
IR3502
connected to the phase clock input PHSIN of the first phase IC, and PHSOUT of the first phase IC is connected to
PHSIN of the second phase IC, etc. The PHSOUT of the last phase IC is connected back to PHSIN of the control
IC.
During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the
feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 4
shows the phase timing for a four phase converter. The switching frequency is set by the resistor ROSC. The clock
frequency equals the number of phase times the switching frequency.
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC1
PWM Latch SET
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
Figure 4 Four Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the phase IC. With the PHSIN voltage high, upon receiving the falling edge of a
clock pulse, the PWM latch is set. The PWMRMP voltage begins to increase; the low side driver is turned off, and
the high side driver is turned on after the non-overlap time. When the PWMRMP voltage exceeds the error
amplifier’s output voltage, the PWM latch is reset. This turns off the high side driver and then turns on the low side
driver after the non-overlap time. Along with that, it activates the ramp discharge clamp, which quickly discharges
the PWMRMP capacitor to the output voltage of share adjust amplifier in phase IC until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode
input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required.
It also favors response to a load step decrease which is appropriate, given the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
The error amplifier is a high speed amplifier with wide bandwidth and fast slew rate incorporated in the control IC. It
is not unity gain stable.
This control method is designed to provide “single cycle transient response,” where the inductor current changes in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in the
ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC.
Figure 5 depicts PWM operating waveforms under various conditions.
Page 10 of 39
July 28, 2009
IR3502
PHASE IC
CLOCK
PULSE
EAIN
PWMRMP
VDAC
GATEH
GATEL
STEADY-STATE
OPERATION
Body Braking
TM
DUTY CYCLE INCREASE
DUE TO LOAD
INCREASE
DUTY CYCLE DECREASE
DUE TO VIN INCREASE
(FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
(VCCLUV, OCP, VID=11111X)
STEADY-STATE
OPERATION
Figure 5 PWM Operating Waveforms
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
TSLEW =
L * ( I MAX − I MIN )
VO
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in
response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the
synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout +
VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient
decrease is now;
TSLEW =
L * ( I MAX − I MIN )
VO + VBODYDIODE
Since the voltage drop in the body diode is often comparable to the output voltage, the inductor current slew rate
can be increased significantly. This patented technique is referred to as “body braking” and is accomplished through
the “body braking comparator” located in the phase IC. If the error amplifier’s output voltage drops below the output
voltage of the share adjust amplifier in the phase IC, this comparator turns off the low side gate driver, enabling the
bottom FET body diode to take over. There is 100mV upslope and 200mV down slope hysteresis for the body
braking comparator.
Lossless Average Inductor Current Sensing
Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor
and measuring the voltage across the capacitor, as shown in Figure 6. The equation of the sensing network is,
vC ( s ) = vL ( s )
1
RL + sL
= iL ( s )
1 + sRCS CCS
1 + sRCS CCS
Usually the resistor Rcs and capacitor Ccs are chosen, such that, the time constant of Rcs and Ccs equals the time
constant of the inductor, which is the inductance L over the inductor DCR RL. If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
Page 11 of 39
July 28, 2009
IR3502
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of
inductor DC current, but affects the AC component of the inductor current.
vL
iL
Current
Sense Amp
L
RL
RC
CC
S
S
VO
CO
vcC
S
CSOUT
Figure 6 Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current
being delivered to the load is obtained rather than peak or sampled information about the switch currents. The
output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in
series with the inductor, this is the only sense method that can support a single cycle transient response. Other
methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer
from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency
variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and
the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier
bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional
sources of peak-to-average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 6. Its gain is
nominally 33 at 25ºC, and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop
feedback path.
The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before
clipping. The output of the current sense amplifier is summed with the VDAC voltage and sent to the control IC and
other phases through an on-chip 3KΩ resistor connected to the IIN pin. The IIN pins of all the phases are tied
together and the voltage on the share bus represents the average current through all the inductors and is used by
the control IC for voltage positioning and current limit protection. The input offset of this amplifier is calibrated to +/1mV in order to reduce the current sense error.
The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input
offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This
calibration algorithm creates ripple on IIN bus with a frequency of fsw/(32*28) in a multiphase architecture.
Average Current Share Loop
Current sharing between the phases of the converter is achieved by the average current share loop in each phase
IC. The output of the current sense amplifier is compared with average current at the share bus. If current in a
phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of
the PWM ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average
current, the share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its
duty cycle and output current. The current share amplifier is internally compensated; such that, the crossover
frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact.
Page 12 of 39
July 28, 2009
IR3502
IR3502 THEORY OF OPERATION
Block Diagram
The block diagram of the IR3502 is shown in Figure 7, and specific features are discussed in the following sections.
VID Control
The control IC allows the processor voltage to be set by a parallel eight bit digital VID bus. The VID codes set the
VDAC as shown in Table 1. The VID pins require an external bias voltage and should not be floated. The VID input
comparators monitor the VID pins and control the Digital-to-Analog Converter (DAC), whose output is sent to the
VDAC buffer amplifier. The output of the buffer amplifier is the VDAC pin. The VDAC voltage, input offsets of error
amplifier and remote sense differential amplifier are post-package trimmed to achieve 0.5% system set-point
accuracy for VID range between 1V to 1.6V. A set-point accuracy of ±5mV and ±8mV is achieved for VID ranges of
0.8V-1V and 0.5V-0.8V respectively. The actual VDAC voltage does not determine the system accuracy, which has
a wider tolerance.
The IR3502 can accept changes in the VID code while operating and vary the VDAC voltage accordingly. The slew
rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and LGND pin. A
resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier. Digital VID
transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush
currents in the input and output capacitors and overshoot of the output voltage.
Adaptive Voltage Positioning
Adaptive voltage positioning is needed to optimize the output voltage deviations during load transients and the
power dissipation of the load at heavy load. The circuitry related to voltage positioning is shown in Figure 8. The
output voltage is set by the reference voltage VSETPT at the positive input to the error amplifier. This reference
voltage can be programmed to have a constant DC offset below the VDAC by connecting RSETPT between VDAC
and VSETPT. The IVSETPT is controlled by the ROSC.
The average load current information for all the phases is fed back to the control IC through the IIN pin. As shown in
Figure 8, this information is thermally compensated with some gain by a set of buffer and thermal compensation
amplifiers to generate the voltage at the VDRP pin. The VDRP pin is connected to the FB pin through the resistor
RDRP. Since the error amplifier will force the loop to maintain FB to be equal to the VDAC reference voltage, an
additional current will flow into the FB pin equal to (VDRP-VDAC) / RDRP. When the load current increases, the
VDRP voltage increases accordingly. More current flows through the feedback resistor RFB and causes the output
to have more droop. The positioning voltage can be programmed by the resistor RDRP so that the droop impedance
produces the desired converter output impedance. The offset and slope of the converter output impedance are
referenced to and therefore independent of the VDAC voltage.
Inductor DCR Temperature Compensation
A negative temperature coefficient (NTC) thermistor should be used for inductor DCR temperature compensation.
The thermistor and tuning resistor network connected between the VN and VDRP pins provides a single NTC thermal
compensation. The thermistor should be placed close to the power stage to accurately reflect the thermal
performance of the inductor DCR. The resistor in series with the thermistor is used to reduce the nonlinearity of the
thermistor.
Remote Voltage Sensing
VOSEN+ and VOSEN- are used for remote sensing and connected directly to the load. The remote sense differential
amplifier with high speed, low input offset and low input bias current ensures accurate voltage sensing and fast
transient response. There is finite input current at both pins VOSEN+ and VOSEN- due to the internal resistor of the
differential amplifier. This limits the size of the resistors that can be used in series with these pins for acceptable
regulation of the output voltage.
Page 13 of 39
July 28, 2009
IR3502
Figure 7 Block Diagram
Page 14 of 39
July 28, 2009
IR3502
TABLE 1 VR11 VID TABLE (PART1)
Hex (VID7:VID0)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Page 15 of 39
Dec (VID7:VID0)
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111
00110000
00110001
00110010
00110011
00110100
00110101
00110110
00110111
00111000
00111001
00111010
00111011
00111100
00111101
00111110
00111111
Voltage
Fault
Fault
1.60000
1.59375
1.58750
1.58125
1.57500
1.56875
1.56250
1.55625
1.55000
1.54375
1.53750
1.53125
1.52500
1.51875
1.51250
1.50625
1.50000
1.49375
1.48750
1.48125
1.47500
1.46875
1.46250
1.45625
1.45000
1.44375
1.43750
1.43125
1.42500
1.41875
1.41250
1.40625
1.40000
1.39375
1.38750
1.38125
1.37500
1.36875
1.36250
1.35625
1.35000
1.34375
1.33750
1.33125
1.32500
1.31875
1.31250
1.30625
1.30000
1.29375
1.28750
1.28125
1.27500
1.26875
1.26250
1.25625
1.25000
1.24375
1.23750
1.23125
1.22500
1.21875
Hex (VID7:VID0)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Dec (VID7:VID0)
01000000
01000001
01000010
01000011
01000100
01000101
01000110
01000111
01001000
01001001
01001010
01001011
01001100
01001101
01001110
01001111
01010000
01010001
01010010
01010011
01010100
01010101
01010110
01010111
01011000
01011001
01011010
01011011
01011100
01011101
01011110
01011111
01100000
01100001
01100010
01100011
01100100
01100101
01100110
01100111
01101000
01101001
01101010
01101011
01101100
01101101
01101110
01101111
01110000
01110001
01110010
01110011
01110100
01110101
01110110
01110111
01111000
01111001
01111010
01111011
01111100
01111101
01111110
01111111
July 28, 2009
Voltage
1.21250
1.20625
1.20000
1.19375
1.18750
1.18125
1.17500
1.16875
1.16250
1.15625
1.15000
1.14375
1.13750
1.13125
1.12500
1.11875
1.11250
1.10625
1.10000
1.09375
1.08750
1.08125
1.07500
1.06875
1.06250
1.05625
1.05000
1.04375
1.03750
1.03125
1.02500
1.01875
1.01250
1.00625
1.00000
0.99375
0.98750
0.98125
0.97500
0.96875
0.96250
0.95625
0.95000
0.94375
0.93750
0.93125
0.92500
0.91875
0.91250
0.90625
0.90000
0.89375
0.88750
0.88125
0.87500
0.86875
0.86250
0.85625
0.85000
0.84375
0.83750
0.83125
0.82500
0.81875
IR3502
TABLE 1 VR11 VID TABLE (PART 2)
Hex (VID7:VID0)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Page 16 of 39
Dec (VID7:VID0)
10000000
10000001
10000010
10000011
10000100
10000101
10000110
10000111
10001000
10001001
10001010
10001011
10001100
10001101
10001110
10001111
10010000
10010001
10010010
10010011
10010100
10010101
10010110
10010111
10011000
10011001
10011010
10011011
10011100
10011101
10011110
10011111
10100000
10100001
10100010
10100011
10100100
10100101
10100110
10100111
10101000
10101001
10101010
10101011
10101100
10101101
10101110
10101111
10110000
10110001
10110010
10110011
10110100
10110101
10110110
10110111
10111000
10111001
10111010
10111011
10111100
10111101
10111110
10111111
Voltage
0.81250
0.80625
0.80000
0.79375
0.78750
0.78125
0.77500
0.76875
0.76250
0.75625
0.75000
0.74375
0.73750
0.73125
0.72500
0.71875
0.71250
0.70625
0.70000
0.69375
0.68750
0.68125
0.67500
0.66875
0.66250
0.65625
0.65000
0.64375
0.63750
0.63125
0.62500
0.61875
0.61250
0.60625
0.60000
0.59375
0.58750
0.58125
0.57500
0.56875
0.56250
0.55625
0.55000
0.54375
0.53750
0.53125
0.52500
0.51875
0.51250
0.50625
0.50000
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
Hex (VID7:VID0)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Dec (VID7:VID0)
11000000
11000001
11000010
11000011
11000100
11000101
11000110
11000111
11001000
11001001
11001010
11001011
11001100
11001101
11001110
11001111
11010000
11010001
11010010
11010011
11010100
11010101
11010110
11010111
11011000
11011001
11011010
11011011
11011100
11011101
11011110
11011111
11100000
11100001
11100010
11100011
11100100
11100101
11100110
11100111
11101000
11101001
11101010
11101011
11101100
11101101
11101110
11101111
11110000
11110001
11110010
11110011
11110100
11110101
11110110
11110111
11111000
11111001
11111010
11111011
11111100
11111101
11111110
11111111
July 28, 2009
Voltage
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
TBS
FAULT
FAULT
IR3502
Control IC
Error
Amplifier
+
EAOUT
Phase IC
VDAC1
-
+
FB
RFB
3k
-
RDRP
VDAC
100k
CSIN+
IOUT
CSIN-
Current
Sense
Amplifier
VDAC
200k
IIN
VDAC
Buffer
+
Thermal
Comp
Amplifier
-
+
RTCMP1
RTHERM
VDRP
RTCMP2
-
Phase IC
VN
+
CSIN+
IOUT
DAC_BUFF
3k
-
RTCMP3
VO
Remote
Sense
Amplifier
+
-
CSIN-
Current
Sense
Amplifier
VDAC
VOSEN+
VOSEN-
Figure 8 Adaptive voltage positioning with thermal compensation.
Start-up Sequence
The IR3502 has a programmable soft-start function to limit the surge current during the converter start-up. A
capacitor connected between the SS/DEL and LGND pins controls soft start timing, over-current protection delay
and hiccup mode timing. A charge current of 52.5uA and discharge current of 4uA control the up slope and down
slope of the voltage at the SS/DEL pin respectively. Figure 9 depicts start-up sequence of converter with VR 11.1
VID. If there is no fault, as the ENABLE is asserted, the SS/DEL pin will start charging. The error amplifier output
EAOUT is clamped low until SS/DEL reaches 1.4V. The error amplifier will then regulate the converter’s output
voltage to match the SS/DEL voltage less the 1.4V offset until the converter output reaches the 1.1V boot voltage.
The SS/DEL voltage continues to increase until it rises above the 3.0V threshold of VID delay comparator. The VID
set inputs are then activated and VDAC pin transitions to the level determined by the VID inputs. The SS/DEL
voltage continues to increase until it rises above 3.92V and allows the VRRDY signal to be asserted. SS/DEL finally
settles at 4.0V, indicating the end of the soft start. The remote sense amplifier has a very low operating range of 50
mV in order to achieve a smooth soft start of output voltage without bump.
The VCCL under voltage lock-out, VID fault modes, over current, as well as a low signal on the ENABLE input
immediately sets the fault latch, which causes the EAOUT pin to drive low turning off the phase IC drivers. The
VRRDY pin also drives low and SS/DEL begin to discharge until the voltage reaches 0.2V. If the fault has cleared
the fault latch will be reset by the discharge comparator allowing a normal soft start to occur.
Other fault conditions, such as over voltage, open sense lines, open loop monitor, and open daisy chain, set
different fault latches, which start discharging SS/DEL, pull down EAOUT voltage and drive VRRDY low. However,
the latches can only be reset by cycling VCCL power.
Page 17 of 39
July 28, 2009
IR3502
VCC
(12V)
ENABLE
VID
1.1V
VDAC
4.0V
3.92V
3V
1.4V
SS/DEL
EAOUT
VOUT
VRRDY
SOFT START
TIME (TD2)
START DELAY (TD1)
VID SAMPLE
TIME (TD3)
VRRDY DELAY
TIME (TD4+TD5)
TD4
NORMAL OPERATION
TD5
Figure 9 Start-up sequence of converter with boot voltage
Current Monitor (IMON)
The control IC generates a current monitor signal IMON using the VDRP voltage and the VDAC reference, as
shown in Figure 10. This voltage is thermally compensated for the inductor DCR variation. The voltage at this pin
reports the average load current information without being referenced to VDAC. The slope of the IMON signal with
respect to the load current can be adjusted with the resistors RTCMP2 and RTCMP3. The IMON signal is clamped
at 1.03V in order to facilitate direct interfacing with the CPU.
Control IC
VDAC
Buffer
+
VDAC
-
100k
200k
-
DAC_BUFF
VDRP
Buffer
IIN
+
Thermal
Comp
Amplifier
From Phase ICs
RTCMP1
RTHERM
+
VDRP
RTCMP2
-
VN
RTCMP3
DAC_BUFF
200k
200k
-
VDRP
200k
+
1.03
IMON
0
200k
50mV
Figure 10 Current report signal (IMON) implementation
Page 18 of 39
July 28, 2009
IR3502
Constant Over-Current Control during Soft Start
The over current limit is fixed by 1.17V above the VDAC. If the VDRP pin voltage, which is proportional to the
average current plus VDAC voltage, exceeds (VDAC+1.17V) during soft start, the constant over-current control is
activated. Figure 11 shows the constant over-current control with delay during soft start. The delay time is set by the
ROSC resistor, which sets the number of switching cycles for the delay counter. The delay is required since overcurrent conditions can occur as part of normal operation due to inrush current. If an over-current occurs during soft
start (before VRRDY is asserted), the SS/DEL voltage is regulated by the over current amplifier to limit the output
current below the threshold set by OC limit voltage. If the over-current condition persists after delay time is reached,
the fault latch will be set pulling the error amplifier’s output low and inhibiting switching in the phase ICs. The
SS/DEL capacitor will discharge until it reaches 0.2V and the fault latch is reset allowing a normal soft start to occur.
If an over-current condition is again encountered during the soft start cycle, the constant over-current control actions
will repeat and the converter will be in hiccup mode. The delay time is controlled by a counter which is triggered by
clock. The counter values vary with switching frequency per phase in order to have a similar delay time for different
switching frequencies.
ENABLE
INTERNAL
OC DELAY
SS/DEL
4.0V
3.92V
3.88V
1.1V
EA
VOUT
VRRDY
OCP THRESHOLD
=VDAC_BUFF+1.17V
IOUT
START-UP WITH
OUTPUT SHORTED
HICCUP OVER-CURRENT
PROTECTION (OUTPUT
SHORTED)
NORMAL
START-UP
OCP
DELAY
OVER-CURRENT
NORMAL NORMAL
PROTECTION
START-UP OPERATION POWER-DOWN
(OUTPUT SHORTED)
(OUTPUT
NORMAL
OPERATION SHORTED)
Figure 11 Constant over-current control waveforms during and after soft start.
Over-Current Hiccup Protection after Soft Start
The over current limit is fixed at 1.17V above the VDAC. Figure 11 shows the constant over-current control with
delay after VRRDY is asserted. The delay is required since over-current conditions can occur as part of normal
operation due to load transients or VID transitions.
If the VDRP pin voltage, which is proportional to the average current plus VDAC voltage, exceeds (VDAC+1.17V)
after VRRDY is asserted, it will initiate the discharge of the capacitor at SS/DEL. The magnitude of the discharge
current is proportional to the voltage difference between VDRP and (VDAC+1.17V) and has a maximum nominal
value of 55uA. If the over-current condition persists long enough for the SS/DEL capacitor to discharge below the
120mV offset of the delay comparator, the fault latch will be set pulling the error amplifier’s output low and inhibiting
switching in the phase ICs and de-asserting the VRRDY signal. The output current is not controlled during the delay
time. The SS/DEL capacitor will discharge until it reaches 200 mV and the fault latch is reset allowing a normal soft
Page 19 of 39
July 28, 2009
IR3502
start to occur. If an over-current condition is again encountered during the soft start cycle, the over-current action
will repeat and the converter will be in hiccup mode.
Linear Regulator Output (VCCL)
The IR3502 has a built-in linear regulator controller, and only an external NPN transistor is needed to create a linear
regulator. The voltage of VCCL is fixed at 6.8V with the feedback resistive divider internal to the IC. The regulator
output powers the gate drivers of the phase ICs and circuits in the control IC, and the voltage is usually
programmed to optimize the converter efficiency. The linear regulator can be compensated by a 4.7uF capacitor at
the VCCL pin. As with any linear regulator, due to stability reasons, there is an upper limit to the maximum value of
capacitor that can be used at this pin and it’s a function of the number of phases used in the multiphase architecture
and their switching frequency. Figure 12 shows the stability plots for the linear regulator with 5 phases switching at
750 kHz.
VCCL Under Voltage Lockout (UVLO)
The IR3502 has no under voltage lockout for converter input voltage (VCC), but monitors the VCCL voltage instead,
which is used for the gate drivers of phase ICs and circuits in control IC and phase ICs. During power up, the fault
latch will be reset if VCCL is above 94% of 6.8V. If VCCL voltage drops below 80% of 6.8V, the fault latch will be
set.
Figure 12 VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz.
Over Voltage Protection (OVP)
Output over-voltage happens during normal operation if a high side MOSFET short occurs or if output voltage is out of
regulation. The over-voltage protection comparator monitors VO pin voltage. If VO pin voltage exceeds VDAC by
130mV after SS, as shown in Figure 13, IR3502 raises ROSC/OVP pin voltage above to V(VCCL) - 1V, which sends
over voltage signal to system. During startup, the threshold is 130 mV above last VID and reverts back to
VBOOT+130mV during boot mode. The ROSC/OVP pin can also be connected to a thyrister in a crowbar circuit,
which pulls the converter input low in over voltage conditions. The over voltage condition also sets the over voltage
fault latch, which pulls error amplifier output low to turn off the converter output. At the same time IIN pin (IIN of phase
ICs) is pulled up to VCCL to communicate the over voltage condition to phase ICs, as shown in Figure 13. In each
phase IC, the OVP circuit overrides the normal PWM operation and will fully turn-on the low side MOSFET within
approximately 150ns. The low side MOSFET will remain on until IIN pin voltage drops below V(VCCL) - 800mV, which
signals the end of over voltage condition. An over voltage fault condition is latched in the IR3502 and can only be
cleared by cycling power to the IR3502 VCCL.
Page 20 of 39
July 28, 2009
IR3502
OUTPUT
VOLTAGE
(VO)
OVP
THRESHOLD
130mV
VCCL-800 mV
IIN
(ISHARE)
GATEH
(PHASE IC)
GATEL
(PHASE IC)
FAULT
LATCH
ERROR
AMPLIFIER
OUTPUT
(EAOUT)
VDAC
NORMAL OPERATION
OVP CONDITION
AFTER
OVP
Figure 13 Over-voltage protection during normal operation
12V
VCC
VCCL+0.7V
VCCL+0.7V
12V
VCCLDRV
1.8V
OUTPUT
VOLTAGE
(VOSEN+)
VCCL UVLO
ROSC/OVP
1.6V
Figure 14 Over-voltage protection during power-up.
Page 21 of 39
July 28, 2009
IR3502
12V
VCCL+0.7V
VCC
VCCL+0.7V
VCCLDRV
1.8V
OUTPUT
VOLTAGE
(VOSEN+)
1.73V
VCCL UVLO
ROSC/OVP
1.6V
Figure 15 Over-voltage protection with pre-charging converter output Vo > 1.73V
12V
VCC
VCCL+0.7V
VCCL+0.7V
VCCLDRV
OUTPUT
VOLTAGE
(VOSEN+)
1.73V
VID + 0.13V
VCCL UVLO
VCCL - 1V
ROSC/OVP
0.6V
3.92V (4V-0.08V)
SS/DEL
Figure 16 Over-voltage protection with pre-charging converter output VID + 0.13V <Vo < 1.73V
Page 22 of 39
July 28, 2009
IR3502
In the event of a high side MOSFET short before power up, the OVP flag is activated with as little supply voltage as
possible, as shown in Figure 14. The VOSEN+ pin is compared against a fixed voltage of 1.73V (typical) for OVP
conditions at power-up. The ROSC/OVP pin will be pulled higher than 1.6V with VCCLDRV voltage as low as 1.8V.
An external MOSFET or comparator should be used to disable the silver box, activate a crowbar, or turn off the supply
source. The 1.8V threshold is used to prevent false over-voltage triggering caused by pre-charging of output
capacitors.
Pre-charging of converter may trigger OVP. If the converter output is pre-charged above 1.73V as shown in Figure 15,
ROSC/OVP pin voltage will be higher than 1.6V when VCCLDRV voltage reaches 1.8V. ROSC/OVP pin voltage will
be VCCLDRV-1V and rise with VCCLDRV voltage until VCCL is above UVLO threshold, after which ROSC/OVP pin
voltage will be VCCL-1V. The converter cannot start unless the over voltage condition stops and VCCL is cycled. If
the converter output is pre-charged 130mV above VDAC but lower than 1.73V, as shown in Figure 16, the converter
will soft start until SS/DEL voltage is above 3.92V (4.0V-0.08V). Then, over voltage comparator is activated and fault
latch is set.
VID
(FAST
VDAC)
VDAC
OV
THRESHOLD
1.73V
VDAC + 130mV
OUTPUT
VOLTAGE
(VO)
VDAC
50mV
50mV
NORMAL
OPERATION
VID DOWN
LOW VID
VID UP
NORMAL
OPERATION
Figure 17 Over-voltage protection during dynamic VID
During dynamic VID down, OVP may be triggered when output voltage can not follow VDAC voltage change at light
load with large output capacitance. Therefore, over-voltage threshold is raised to 1.73V from VDAC+130mV
whenever dynamic VID is detected and the difference between output voltage and VDAC is more than 50mV, as
shown in Figure 19. The over-voltage threshold is changed back to VDAC+130mV if the difference is smaller than
50mV.
VID Fault Codes
VID codes of 0000000X and 1111111X for VR11 will set the fault latch and disable the error amplifier. A 1.3us delay
is provided to prevent a fault condition from occurring during Dynamic VID changes. A VID FAULT condition is
latched for VR 11 with boot voltage and can only be cleared by cycling power to VCCL or re-issuing ENABLE.
Voltage Regulator Ready (VRRDY)
The VRRDY pin is an open-collector output and should be pulled up to a voltage source through a resistor. After the
soft start completion cycle, the VRRDY remains high until the output voltage is in regulation and SS/DEL is above
3.92V. The VRRDY pin becomes low if the fault latch, over voltage latch, open sense line latch, or open daisy chain
Page 23 of 39
July 28, 2009
IR3502
latch is set. A high level at the VRRDY pin indicates that the converter is in operation and has no fault, but does not
ensure the output voltage is within the specification. Output voltage regulation within the design limits can logically
be assured however, assuming no component failure in the system.
Open Voltage Loop Detection
The output voltage range of error amplifier is detected all the time to ensure the voltage loop is in regulation. If any
fault condition forces the error amplifier output above VCCL-1.08V for 8 switching cycles, the fault latch is set. The
fault latch can only be cleared by cycling power to VCCL.
Open Remote Sense Line Protection
If either remote sense line VOSEN+ or VOSEN- or both are open, the output of remote sense amplifier (VO) drops.
The IR3502 monitors VO pin voltage continuously. If VO voltage is lower than 200 mV, two separate pulse currents
are applied to VOSEN+ and VOSEN- pins respectively to check if the sense lines are open. If VOSEN+ is open, a
voltage higher than 90% of V(VCCL) will be present at VOSEN+ pin and the output of open line detect comparator
will be high. If VOSEN- is open, a voltage higher than 700mV will be present at VOSEN- pin and the output of openline-detect comparator will be high. The open sense line fault latch is set, which pulls error amplifier output low
immediately and shut down the converter. The SS/DEL voltage is discharged and the fault latch can only be reset
by cycling VCCL power. During dynamic VID down, OVP may be triggered when output voltage can not follow
VDAC voltage change at light load with large output capacitance. Therefore, over-voltage threshold is raised to
1.73V from VDAC+130mV whenever dynamic VID is detected and the difference between output voltage and VDAC
is more than 50mV, as shown in Figure 17. The over-voltage threshold is changed back to VDAC+130mV if the
difference is smaller than 50mV.
Open Daisy Chain Protection
IR3502 checks the daisy chain every time it powers up. It starts a daisy chain pulse on the PHSOUT pin and detects
the feedback at PHSIN pin. If no pulse comes back after 32 CLKOUT pulses, the pulse is restarted again. If the
pulse fails to come back the second time, the open daisy chain fault is registered, and SS/DEL is not allowed to
charge. The fault latch can only be reset by cycling the power to VCCL.
After powering up, the IR3502 monitors PHSIN pin for a phase input pulse equal or less than the number of phases
detected. If PHSIN pulse does not return within the number of phases in the converter, another pulse is started on
PHSOUT pin. If the second started PHSOUT pulse does not return on PHSIN, an open daisy chain fault is
registered.
Enable Input
The ENABLE pin below 0.8V sets the Fault Latch and a voltage above 0.85V enables the soft start of the converter.
Thermal Monitoring (VRHOT)
A resistor divider including a thermistor at HOTSET pin sets the VRHOT threshold. The thermistor is usually placed
at the temperature sensitive region of the converter, and is linearized by a series resistor. The IR3502 compare
HOTSET pin voltage with a reference voltage of 1.6V. The VRHOT pin is an open-collector output and should be
pulled up to a voltage source through a resistor. If the thermal trip point is reached the VRHOT output drives low.
The hysteresis of the VRHOT comparator helps eliminate toggling of VRHOT output.
The overall system must be considered when designing for OVP. In many cases the over-current protection of the
AC-DC or DC-DC converter supplying the multiphase converter will be triggered and provide effective protection
without damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If
this is not possible, a fuse can be added in the input supply to the multiphase converter.
Page 24 of 39
July 28, 2009
IR3502
Phase Number Determination
After a daisy chain pulse is started, the IR3502 checks the timing of the input pulse at PHSIN pin to determine the
phase number. This information is used to have symmetrical phase delay between phase switching without the
need of any external component.
Single Phase Operation
In an architecture where only a single phase is needed the switching frequency is determined by the clock
frequency.
CURRENT SHARE LOOP COMPENSATION
The internal compensation of current share loop ensures that crossover frequency of the current share loop is at
least one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated. The
crossover frequency of current share loop is approximately 8 kHz.
Fault Operation Table
The Fault Table below describes the different faults that can occur and how IR3500A would react to protect the
supply and the load from possible damage. The fault types that can occur are listed in row 1. Row 2 has the method
that a fault is cleared. The first 5 faults are latched in the UV fault latch and the VCCL power has to be recycled by
switching off the input and switching it back on for the converter to work again. The rest of the faults (except for
UVLO Vout) are latched in the SS fault latch and does not need to recycle the VCCL power in order to resume
normal operation once the fault condition clears. Most of the faults disable the error amplifier (EA) and discharge the
soft start capacitor. All the faults flag VRRDY. VRRDY returns back to high when the faults are cleared. The delay
row shows reaction time after detecting a fault condition. Delays are provided to minimize the possibility of nuisance
faults.
Fault Type
Open
Daisy
Fault
Clearing
Method
Error Amp
Disabled
ROSC/OVP
& IIN drive
high until
OV clears
SS/DEL
Discharge
Flags
VRRDY
Delay?
Open
Control
Loop
Open
Sense
Line
Over
Voltage
VID
Disable
Recycle VCCL
VCCL
UVLO
OC Before
Start-up
OC After
Start-up
Resume Normal Operation when Condition Clears
Yes
No
Yes
No
Yes
Yes
32 Clock
Pulses
Page 25 of 39
8
PHSOUT
Pulses
No
No
1.3us
Blank
Time
250 ns
Blank
Time
No
PHSOUT
Pulses. Count
Programmed by
ROSC value
SS/DEL Discharge
Threshold
July 28, 2009
IR3502
DESIGN PROCEDURES - IR3502 AND IR3507 CHIPSET
IR3502 EXTERNAL COMPONENTS
Oscillator Resistor Rosc
The oscillator of IR502 generates square-wave pulses to synchronize the phase ICs. The switching frequency of
the each phase converter equals the PHSOUT frequency, which is set by the external resistor ROSC according to
the curve in Figure 18. The CLKOUT frequency equals the switching frequency multiplied by the phase number.
The Rosc sets the reference current used for no load offset which is given by Figure 19 and equals:
ISETPT =
0.595
Rosc
(1)
Soft Start Capacitor CSS/DEL
The soft start capacitor CSS/DEL programs five different time parameters. They include soft start delay time, soft
start time, VID sample delay time, VR ready delay time and over-current fault latch delay time after VR ready.
For the converter using VID with boot voltage, the SS/DEL pin voltage controls the slew rate of the converter
output voltage, as shown in Figure 9. After the ENABLE pin voltage rises above 0.85V, there is a soft-start delay
time TD1, after which the error amplifier output is released to allow the soft start of output voltage. The soft start
time TD2 represents the time during which converter voltage rises from zero to 1.1V. The VID sample delay time
(TD3) is the time period when VID stays at boot voltage of 1.1V. VID rise or fall time (TD4) is the time when VID
changes from boot voltage to the final voltage. The VR ready delay time (TD5) is the time period from VR
reaching the final voltage to the VR ready signal being issued, which is determined by the delay comparator
threshold.
CSS/DEL = 0.1uF meets all the specifications of TD1 to TD5, which are determined by (2) to (6) respectively.
TD3 =
TD 4 =
TD5 =
Page 26 of 39
TD1 =
C SS / DEL *1.4 C SS / DEL *1.4
=
I CHG
52.5 *10 −6
TD 2 =
C SS / DEL *1.1 C SS / DEL *1.1
=
I CHG
52.5 *10 −6
(2)
(3)
C SS / DEL * (3 − 1.4 − 1.1) C SS / DEL * 0.7
=
I CHG
52.5 * 10 −6
C SS / DEL * V DAC − 1.1
I CHG
=
(4)
C SS / DEL * V DAC − 1.1
(5)
52.5 *10 − 6
C SS / DEL * (3.92 − 3)
C
* 0.92
− TD4 = SS / DEL −6 − TD4
I CHG
52.5 * 10
(6)
July 28, 2009
IR3502
CSS / DEL =
TD 2 * I CHG TD 2 * 52.5 *10 −6
=
VO
VO
(7)
The soft start delay time (TD1) and VR ready delay time (TD3) are determined by (8) to (9) respectively.
C
*1.4 CSS / DEL *1.4
TD1 = SS / DEL
=
I CHG
52.5 *10− 6
TD3 =
C SS / DEL * ( 4.0 − VO ) C SS / DEL * ( 4.0 − VO )
=
I CHG
52.5 *10 −6
(8)
(9)
Once CSS/DEL is chosen, the minimum over-current fault latch delay time tOCDEL is fixed and can be quantified as
t OCDEL =
C SS / DEL * 0.12 C SS / DEL * 0.12
=
I DISCHG
55 * 10 −6
(10)
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
The slew rate of VDAC slope SRDOWN can be programmed by the external capacitor CVDAC as defined in (11),
where ISINK is the sink current of VDAC pin. The slew rate of VDAC up-slope is the same as that of down-slope.
The resistor RVDAC is used to compensate VDAC circuit and can be calculated as follows
CVDAC =
RVDAC =
I SINK
44 *10 −6
=
SR DOWN
SR DOWN
(11)
1
2 ⋅ π ⋅ 900kHz ⋅ CVDAC
(12)
Current Report Gain and Thermal Compensation
Intel VR11.1 specifications require IMON to report the core maximum load current of the CPU be reported as 1 V
nominal. The core maximum current can be different for different platforms. The IMON tuning resistors can
therefore be adjusted and thermally compensated to adjust the load current gain with respect to the IMON. The
expressions that govern the relationship between load current, IMON, and VDRP at room temperature are given
by
1  R L _ room ⋅ Gcs
VDRP = VDAC + ⋅ 
3 
n
1  R L _ room ⋅ G cs
IMON = 50mV + ⋅ 
3 
n
  ( RTCMP2) II ( RTCMP1 + RTHERM _ room) 
 ⋅ 1 +
⋅Io
 
RTCMP3


(13)
  ( RTCMP 2) II ( RTCMP1 + RTHERM _ room) 
 ⋅ 1 +
 ⋅ Io
 
RTCMP3


(14)
The change in inductor DCR with temperature is compensated by an equivalent variation in the RTHERM. The
following equations derive the RTCMP1 and RTCMP2 if RTCMP3 and the thermistor (RTHERM and βTHERM) are
fixed.
RL _ MAX = RL _ room ∗ [1 + 3850 *10 −6 ∗ (TL _ MAX − Troom )]
K THERM _ room =
Page 27 of 39
(15)
( R L _ room ⋅ Gcs )
( RL _ max ⋅ Gcs )
(1 − 50mV )
, K c _ room =
, K c _ t max =
n
n
I o max
July 28, 2009
(16)
IR3502
 3 ⋅ K THERM _ room

Rt _ room = 
− 1 ⋅ RTCMP3


K c _ room


 3 ⋅ K THERM _ room

Rt _ t max = 
− 1 ⋅ RTCMP3


K c _ t max



RTHERM t max = RTHERM room ⋅ e
BTH = RTHERM
room
+ RTHERM
CTH = RTHERM room ⋅ RTHERM t max
RTCMP1 =
− BTH +
1
1
−
 273+ Tmax 273 +Troom
β THERM ⋅
(17)
(18)




(19)
(20)
t max


 RTHERM room − RTHERM t max
−
1
1
−

Rt _ t max Rt _ room







(21)
(BTH )2 − 4 ⋅ CTH
(22)
2
RTCMP2 =
1
(23)
 1

1


−
R

 t _ t max Rt _ t max + RTCMP1 
Droop Resistor
The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant
temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from (15),
where RL_tmax and RL_room are the inductor DCR at maximum temperature Tmax and room temperature Troom.
respectively. After the thermal compensation is achieved using the procedure given above, the droop resistance
can be calculated using the following equation.
R DRP =
1 R FB  GCS ∗ R L _ ROOM
∗
∗
3 Ro 
n
R
 

 ∗ 1 + t _ room 
  RTCMP3 
(24)
Over-current Threshold
Once the current report gain and the thermal compensation are calculated the OCP threshold is calculated using the
following expression.
I OCP =
(25)
1.17
1  R L _ room ⋅ Gcs
⋅
3 
n
  ( RTCMP2) II ( RTCMP1 + RTHERM _ room) 
 ⋅ 1 +

 
RTCMP3


No Load Output Voltage Setting Resistor RVSETPT,
A resistor between VSETPT pin and VDAC is used to create output voltage offset VO_NLOFST, which is the
difference between VDAC voltage and output voltage at no load condition. RVSETPT is determined by (26), where
IVSETPT is the current flowing out of VSETPT pin as shown in Figure 19.
RVSETPT =
Page 28 of 39
VO _ NLOFST
(26)
IVSETPT
July 28, 2009
IR3502
Thermistor RTHERM and Over Temperature Setting Resistors RHOTSET1 and RHOTSET2
The threshold voltage of VRHOT comparator is fixed at 1.6V, and a negative temperature coefficient (NTC)
thermistor RTHERM is required to sense the temperature of the power stage. If we pre-select RTHERM, the NTC
thermistor resistance at allowed maximum temperature TMAX is calculated from (27).
RTMAX = RTHERM * EXP[ BTHERM * (
1
T L _ MAX
−
1
T _ ROOM
(27)
)]
Select the series resistor RHOTSET2 to linearize the NTC thermistor, which has non-linear characteristics in the
operational temperature range. Then calculate RHOTSET1 corresponding to the allowed maximum temperature
TMAX from (28).
R HOTSET 1 =
( RTMAX + R HOTSET 2 ) * (VCCL − 1.6)
1.6
(28)
VCCL Capacitor CVCCL
The capacitor is selected based on the stability requirement of the linear regulator and the load current to be
driven. The linear regulator supplies the bias and gate drive current of the phase ICs. A 4.7uF normally ensures
stable VCCL performance for Intel VR11 applications.
VCCL Regulator Drive Resistor RVCCLDRV
The drive resistor is primarily dependent on the load current requirement of the linear regulator and the
minimum input voltage requirements. The following equation gives an estimate of the average load current of
the switching phase ICs.
[
]
I drive _ avg = (Q gb + Q gt ) ⋅ f sw + 10 mA ⋅ n
(29)
Qgb and Qgt are the gate charge of the top and bottom FET. For a minimum input voltage and a maximum
VCCL, the maximum RVCCLDRV required to use the full pull-down current of the VCCL driver is given by
RVCCLDRV =
V I (min) − 0.7 − 6.8V
I drive _ avg / β min
(30)
Due to limited pull down capability of the VCCLDRV pin, make sure the following condition is satisfied.
VI (max) − 0.7 − 6.8V
< 10mA
RVCCLDRV
(31)
In the above equation, VI( min) and VI( max) is the minimum and maximum anticipated input voltage. If the
above condition is not satisfied there is a need to use a device with higher βmin or Darlington configuration can
be used instead of a single NPN transistor.
Current Monitor Filter
A filter is added to isolate the CPU from rapid changes in the load current and trigger false response. A filter with
300 us time constant provides adequate delay for Intel VR11.1 response. A 1k resistor between IMON and local
ground helps equalize the source and sink current of the IMON pin.
Page 29 of 39
July 28, 2009
IR3502
DESIGN EXAMPLE – HIGH FREQUENCY CONVERTER (FIG. 20)
SPECIFICATIONS
Input Voltage: VI=12 V
DAC Voltage: VDAC=1.2 V
No Load Output Voltage Offset: VO_NLOFST=10 mV
Continuous Output Current: IOTDC=110 A
Maximum DC Output Current: IOMAX=140 A
Current Report Gain =0.95 V represents IOMAX
Output Impedance: RO=0.8 mΩ
Soft Start Delay Time: TD1=0-5ms
Soft Start Time: TD2=0.05ms-10ms
VID Sample Delay Time: TD3=0.05-3ms
VID Rise Time: TD4=0-3.5ms
VR Ready Delay Time: TD5=0.05ms-3ms
Maximum Over Current Delay Time: tOCDEL<2.5ms
Dynamic VID Up-Slope Slew Rate: SRup=10mV/us
Over Temperature Threshold: TMAX=100 ºC
POWER STAGE
Phase Number: n=5
Switching Frequency: fSW = 700 kHz
Output Inductors: L=70 nH, RL=0.35 mΩ (Including solder resistance)
Output Capacitors: Ceramic: C=22uF, Number Nc=50
SP: C=220uF, Number Nsp=2
IR3502 EXTERNAL COMPONENTS
Oscillator Resistor Rosc
Once the switching frequency is chosen, ROSC can be determined from the curve in Figure 18 of this data sheet.
For a switching frequency of 700kHz per phase, choose ROSC = 17.4 kΩ. The reference current is given by 30uA.
Soft Start Capacitor CSS/DEL
Determine the soft start capacitor to meet the specifications of the delay time.
Choose CSS/DEL=0.1uF. The soft start delay time is
C SS / DEL * 1.4 0.1 * 10 −6 * 1.4
=
= 2.67 mS
I CHG
52.5 * 10 −6
TD1 =
The soft start time is
TD 2 =
C SS / DEL *1.1 0.1*10 −6 *1.1
=
= 2.1mS
I CHG
52.5 *10 − 6
The VID sample delay time is
TD3 =
C SS / DEL * (3.2 − 1.4 − 1.1) 0.1*10 −6 * 0.7
=
= 1.33mS
I CHG
52.5 *10 −6
VID rise time is
Page 30 of 39
July 28, 2009
IR3502
TD 4 =
C SS / DEL * V DAC − 1.1
=
I CHG
The VR ready delay time is
TD 5 =
0.1*10 −6 * 1.3 − 1.1
52.5 *10 − 6
= 0.38mS
C SS / DEL * (3.92 − 3)
0.1 * 10 −6 * 0.92
− TD 4 =
− TD 4 = 1.37 mS
I CHG
52.5 * 10 − 6
Minimum over current fault latch delay time is
C SS / DEL * 0.12 0.1 * 10 −6 * 0.12
=
= 0.21ms
I OCDISCHG
55 * 10 −6
t OCDEL =
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
Calculate the VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate. The
up-slope slew rate is the same as the down-slope slew rate.
CVDAC =
I SINK
44 * 10 −6
=
= 4.4nF
SR DOWN 10 * 10 −3 / 10 − 6
A 3.3 nF capacitor can be used. A series resistor is used to stabilize the VDAC buffer.
RVDAC =
1
= 53Ω A 50 Ω resistor is selected.
2 ⋅ π ⋅ 900kHz ⋅ CVDAC
No Load Output Voltage Setting Resistor RVSETPT
From Figure 19, the bias current of VSETPT pin is 30 uA with ROSC=17.4 kΩ.
RVSETPT =
VO _ NLOFST
I VSETPT
10 *10 −3
=
= 330Ω
30 * 10 − 6
Current Report Gain and Thermal Compensation
The reporting gain specifies the max load current in form of a voltage. For this example, the 140 A represents 0.95 V
at IMON. If the thermal effects are neglected (14) can be used to find the reporting gain. However, as the inductor
DCR increases with temperature, the thermal compensation string (RTCMP1, RTCMP2, and RTHERM) can be used
to compensate this change in DCR.
Assuming Troom =25 Deg, Tmax=100 Deg the change in DCR is found our using (15)
RL _ MAX = 0.35m ∗ [1 + 3850 *10 −6 ∗ (100 − 25)] = 0.45mΩ
Preselect RTCMP3=1 kΩ, and RTHERM_room=10 kΩ with βTHERM=3380K RTCMP1 and RTCMP2 can be found out using
(16)-(23)
RTCMP1=8.837 kΩ
RTCMP2=8.457 kΩ
Page 31 of 39
July 28, 2009
IR3502
Droop Resistor
Based on the above calculation RDRP can be selected to obtain specific output impedance.
Pre-select RFB=1 kΩ and using Ro=0.8 mΩ, Gcs=33.5 along with the converter parameters can be plugged into (24) to
find out RDRP.
R DRP =
1 1kΩ  33.5 ∗ 0.35m   5.618k 
∗
∗
= 7.5kΩ
 ∗ 1 +
3 0.8mΩ 
5
1k 
 
Over Current Threshold
The OCP is fixed at 1.17 V above the VDAC voltage. Therefore, it can be determined as follows
I OCP =
1.17
 1  0.35m ⋅ 33.5   (8.457k ) II (8.837k + 10k ) 

 ⋅ 1 +
 ⋅
5
1k
 

3 
= 218.9 A
VCCL Drive Resistor RVCCLDRV
The maximum drive current for the linear regulator is dependent on the type of MosFET used. For this
example, it’s assumed that IR6622 and IRF6628 are used as the control and sync FET respectively.
I drive _ avg = [(30 .3n + 11n ) ⋅ 700 k + 10 mA ] ⋅ 5 = 195 mA
The minimum input voltage is assumed to be 10.5 V and VCCL is fixed at 6.5V for this design.
RVCCLDRV =
10.5V − 0.7V − 6.5V
= 700Ω
195mA / 30
Choose a transistor with β(min) of 50. The maximum input voltage is assumed 13.5 V,
13.5V − 0.7 − 6.5
= 9 mA < 10 mA
700Ω
Thermistor RTHERM and Over Temperature Setting Resistors RHOTSET1 and RHOTSET2
Choose NTC thermistor RTHERM=2.2kΩ, which has a constant of BTHERM=3520, and the NTC thermistor
resistance at the allowed maximum temperature TMAX is,
RTMAX = RTHERM * EXP[ BTHERM * (
1
1
1
1
−
)] = 2.2 *10 3 * EXP[3520 * (
−
)] = 142Ω
T L _ MAX T _ ROOM
273 + 115 273 + 25
Select RHOTSET2 = 931Ω to linearize the NTC, which has non-linear characteristics in the operational temperature
range. Then calculate RHOTSET1 corresponding to the allowed maximum temperature TMAX.
R HOTSET 1 =
( RTMAX + R HOTSET 2 ) * (VCCL − 1.6) (142 + 931) * (7 − 1.6)
=
= 3.63kΩ , choose RHOTSET1=3.65kΩ.
1.6
1.6
Page 32 of 39
July 28, 2009
IR3502
IR3502 Frequency vs. ROSC Resistor
55
50
45
RROSC (KOhm)
40
35
RROSC
Nominal Spec
30
25
20
15
10
5
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
Frequency (KHz)
Figure 18: Frequency variation with ROSC.
I(VSETPT) vs. 1/RROSC
90.0
80.0
70.0
I(VSETPT) (uA)
60.0
I(VSETPT)
Min V(ISETPT)
Nom V(ISETPT)
Max V(ISETPT)
50.0
40.0
30.0
20.0
10.0
0.0
0.000
0.020
0.040
0.060
0.080
0.100
0.120
0.140
1/RROSC (1/KOhm)
Figure 19: ISETPT with ROSC.
Page 33 of 39
July 28, 2009
IR3502
12VF
C15
10uF
C16
10uF
C13
0.1uF
VCCL
C17
C1 8
0.1uF
0 .1 uF
4
1
2
6
7
VC C
3
4
C14
0.1uF
SW1
1
GL1
5
1
2
72nH
3
4
9
VCCP
C19
10uF
L12
Q12
IRF6629 MX
PA0512.700
10
6
2
L11
No Stuff
11
NC2
GAT EL
PGN D
C LKIN
PH SOUT
N C1
R19
0
No Stuf f
VCCL
12
VCCL
PHSIN
C11
0.1uF
2.32k
BOOST
LGND
5
Q11
IRF6622 SQ
5
13
1
2
6
7
18
16
17
C SIN -
IR3507
GH1
14
GATEH
DACIN
R20
15
SW
PSI
3
PHSOUT
C12
0.1uF
IOUT
2
8
0
7
R21
No Stuf f
VDAC
C SIN +
1
ISHARE
PSI_L
EAIN
NC3
U11
19
20
EA
CLOCK
12VF
C22
10uF
C26
10uF
C23
0.1uF
VCCL
C2 7
C25
0 .1u F
0.1 uF
VCCL=6.8V
0
PHSIN
16
1
2
6
7
VC C
3
4
Q13
IRF6629 MX
5
2
FB
1
2
6
7
VCCL
NC2
Q16
IRF6622 SQ
5
12
C30
0.1uF
SW1
1
Q15
IRF6629 MX
1
2
GL1
5
VCCP
L15
No Stuff
11
C37
10uF
L16
2
72nH
PA0512.700
C106
100pF
CLOCK
0
12VF
C40
10uF
C102
1500pF
VCCL
C104
47pF
C44
10uF
C41
0.1uF
EA
VCCL
C4 5
C4 3
0.1 uF
0 .1u F
10 ohm
5
1
2
6
7
BOOST
LGND
VCCL
PHSIN
GH1
14
Q18
IRF6622 SQ
5
C38
0.1uF
2.32k
13
12
VCCL
C39
0.1uF
SW1
1
GL1
Q17
IRF6629 MX
5
2
VCCP
L17
No Stuff
11
C46
10uF
L18
1
2
72nH
3
4
NC1
NC2
R29
15
3
4
17
16
VC C
IR3507
DACIN
6
VOSEN-
19
GATEH
R28
0
No Stuf f
VOSEN+
0
SW
PSI
1
2
6
7
4
0
IOUT
GAT EL
3
VDAC
TP9
VOSEN+
R163
2
P GN D
0
C LKIN
R30
9
1
ISHARE
PSI_L
C42
0.1uF
PA0512.700
10
C101
0.1uF
C SIN-
10.0K
No Stuf f
C SIN +
NC 3
U20
RT3
18
EA
C103
2200pF
EAIN
R109
4.32k
P HSOU T
1.0k
8
R105
R153
4.99k
No Stuf f
RT1
2.2k
7
R102
3.65k
R103
931
C29
0.1uF
2.32k
13
3
4
PGN D
PHSIN
GAT E L
LGND
GH1
3
4
BOOST
R26
15
14
1
2
6
7
17
16
CSIN +
VC C
18
19
IR3507
DACIN
R25
0
No Stuf f
ISHARE
EAIN
GATEH
R106
Vo
R162
CLOCK
0
12VF
C49
10uF
C53
10uF
C50
0.1uF
VCCL
C54
C5 2
0.1 uF
0 .1 uF
PHSIN
1
2
6
7
NC2
Q20
IRF6622 SQ
5
12
VCCL
C48
0.1uF
SW1
1
GL1
Q19
IRF6629 MX
5
2
VCCP
L19
No Stuff
11
C55
10uF
L20
1
2
72nH
CLOCK
Figure 20: Design Example Schematic.
Page 34 of 39
C47
0.1uF
2.32k
13
3
4
GAT EL
VCCL
PHSIN
PGN D
LGND
GH1
14
3
4
BOOST
R32
15
1
2
6
7
18
17
16
VC C
C SIN-
IR3507
DACIN
6
R31
0
No Stuf f
GATEH
C LKIN
5
SW
PSI
9
4
IOUT
8
3
C51
0.1uF
10
2
C SIN +
20
NC 3
0
VDAC
PH SOU T
R33
NC1
1
ISHARE
PSI_L
EAIN
U21
19
EA
7
R165
SW
PSI
TP2
R155 EA
0
3V3
R148
0
No Stuf f
EA
7.5k
5
0
R108
8.45k
No Stuf f
R110
20
1
10.0K
IOUT
9
C105
22nF
No Stuf f
R154
4
TP4
R158 ISHARE
RT
R111 1k
FB
0.1 uF
C33
0.1uF
10
R107
8.87k
2
3
VN
VDRP
C34
0 .1u F
2
0
VDAC
18
R101
20.0k
R27
1k
17
TP3
FB
1
ISHARE
PSI_L
C SIN -
R130
0 ohm
No Stuf f
NC 3
No Stuf f
C109
0.1uF
No Stuf f
CLKIN
0
VDAC
191 No Stuf f
R112
R123
10.0k
No Stuf f
PHSOU T
C107
3300pF
330
U18
1
C3 6
EA
Q4
CSDD-25M
No Stuf f
3
No Stuff
8
49.9
No Stuf f
4
6
TP5
R156 VDAC
7
R113
R152
VCCL
FDC6320C
C35
10uF
C32
0.1uF
6
EAOU T
R121
0
RT2
ENABLE
VRHOT
OVP
17.4k
C108
0.1uF
R114
19
16
FB
15
VOSEN -
VO
VDRP
VOSEN +
VN
VID0
TP1
VRHOT
2
PA0512.700
C31
10uF
Q5
NC 1
21
20
R122
20.0k
No Stuf f
3
5
25
C LKOU T
28
26
P HSIN
PH SOU T
27
30
29
IIN
VC C L
IM ON
VID1
14
8
22 SS
VDAC_BUFF
13
7
VID0_CPU
VID2
fsw =700kHz
R115
VSETPT
TP6
OVP
R157
OVP
23
VDAC
IR3502
VID3
9
VID1_CPU
0
SS/DEL
VID4
TP7
R159 SS
24
GND
VID5
12
VID2_CPU
6
31
32
5
VR RD Y
4
VID3_CPU
VCC LDR V
VID4_CPU
SS
ROSC
H OT SET
3
1
12VF
CLOCK
VID6
VR H OT
VID5_CPU
VID7
EN ABLE
2
11
1
VID6_CPU
10
VID7_CPU
C28
10uF
L14
72nH
PHSOUT
R124 3.0k
U105
VCCP
L13
No Stuff
1
2
6
7
18
17
C SIN -
C SIN +
GAT EL
GL1
ISHARE
1.0k
VR_IOUT
C187
0.1u
C21
0.1uF
11
NC2
2
CLOCK
R151 0
698
R120
VOSEN-
R22
0
No Stuf f
15A
VCCL
R118
20.0k
R160
0
TP11
VCCL
R161
R150
4.53k
No Stuf f
20
TP12
VCCP_VRRDY PWRGD
TP29
IMON
R149
20.0k
C110 No Stuf f
0.1uF
C111
4.7uF
VCCL
12
VCCL
PHSIN
1
3
4
Q6
CJD200
R119
LGND
6
3V3
5
C20
0.1uF
2.32k
SW1
10
4
12VF
F2
15A
Q14
IRF6622 SQ
5
13
BOOST
PGND
F1
N C1
CTLT853-M833
No Stuf f
12VL
IR3507
GH1
14
GATEH
DACIN
R23
15
SW
PSI
C LKIN
3
VDAC
C24
0.1uF
IOUT
9
2
8
0
PH SOUT
R24
7
1
ISHARE
PSI_L
Q8
EAIN
NC3
U17
19
20
EA
July 28, 2009
PA0512.700
IR3502
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC.
VO
VCCL
VOSNS +
IIN
VOSNS –
To SYSTEM
VID0
VID1
VID2
VID3
VID4
VID5
VID6
To
Phase ICs
Analog
Ccp1
Rcp
Ccp
Rhotset1
ENABLE
VID7
IMON
Rhotset2
HOTSET
VRHOT
Cfb
PHSIN
Voltage
Remote
Sense
FB
Rfb1
PHSOUT
VRRDY
Rmon1
Rtcmp3
Rdrp
EAOUT
Rfb
CLKOUT
VCCLDRV
Page 35 of 39
To Rtherm
VDRP
VN
VDAC_BUFF
Rtcmp2
Rctmp1
vcc
Rsetpt
VSETPT
VDAC
SS/DEL
GND
ROSC
Rosc
Css/Del
Rvdac
Cvdac
To
Phase ICs
Digital
Rmon
•
•
Cmon
•
To Regulator
•
Dedicate at least one middle layer for a ground plane LGND.
Connect the ground tab under the control IC to LGND plane through a via.
Place VCCL decoupling capacitor VCCL as close as possible to VCCL and LGND pins.
Place the following critical components on the same layer as control IC and position them as close as possible
to the respective pins, ROSC, RVDAC, CVDAC, and CSS/DEL. Avoid using any via for the connection.
Place the compensation components on the same layer as control IC and position them as close as possible to
EAOUT, FB, VO and VDRP pins. Avoid using any via for the connection.
Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over
the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.
Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes.
Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation
components.
Cvccl2
•
•
•
•
To VCCL
To Thermistor
LGND
PLANE
July 28, 2009
IR3502
PCB Metal and Component Placement
• Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should
be ≥ 0.2mm to minimize shorting.
• Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm
inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard
extension will accommodate any part misalignment and ensure a fillet.
• Center pad land length and width should be equal to maximum part pad length and width. However, the
minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥
0.23mm for 3 oz. Copper)
• Four 0.3mm diameter vias shall be placed in the pad land spaced at 1.2mm, and connected to ground to
minimize the noise effect on the IC and to transfer heat to the PCB.
• No PCB traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so
can cause the IC to rise up from the PCB resulting in poor solder joints to the IC leads.
Page 36 of 39
July 28, 2009
IR3502
Solder Resist
• The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder
resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non
Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.
• The minimum solder resist width is 0.13mm.
• At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a
fillet so a solder resist width of ≥ 0.17mm remains.
• The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto
the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable
to have the solder resist opening for the land pad to be smaller than the part pad.
• Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high
aspect ratio of the solder resist strip separating the lead lands from the pad land.
• The four vias in the land pad should be tented or plugged from bottom board side with solder resist.
Page 37 of 39
July 28, 2009
IR3502
Stencil Design
• The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.
Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm
pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower;
openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release.
• The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead
land.
• The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit
approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad
the part will float and the lead lands will be open.
• The maximum length and width of the land pad stencil aperture should be equal to the solder resist
opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the
lead lands when the part is pushed into the solder paste.
Page 38 of 39
July 28, 2009
IR3502
PACKAGE INFORMATION
o
o
32L MLPQ (5 x 5 mm Body) – θJA = 24.4 C/W, θJC =0.86 C/W
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. www.irf.com
www.irf.com
Page 39 of 39
July 28, 2009