Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 • Parity and FCS (frame check sequence LRC or CRC) generation DESCRIPTION The Philips Semiconductors SCN26562 Dual Universal Serial Communications Controller (DUSCC) is a single-chip MOS-LSI communications device that provides two independent, multi-protocol, full-duplex receiver/transmitter channels in a single package. It supports bit-oriented and character-oriented (byte count and byte control) synchronous data link controls as well as asynchronous protocols. The SCN26562 interfaces to synchronous bus MPUs and is capable of program-polled, interrupt driven, block-move or DMA data transfers. and checking • Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1, Manchester • Programmable channel mode: full- and half-duplex, auto-echo, or local loopback • Programmable data transfer mode: polled, interrupt, DMA, wait • DMA interface The operating mode and data format of each channel can be programmed independently. Each channel consists of a receiver, a transmitter, a 16-bit multi-function counter/timer, a digital phase-locked loop (DPLL), a parity/CRC generator and checker, and associated control circuits. The two channels share a common bit rate generator (BRG), operating directly from a crystal or an external clock, which provides 16 common bit rates simultaneously. The operating rate for the receiver and transmitter of each channel can be independently selected from the BRG, the DPLL, the counter/timer, or from an external 1X or 16X clock, making the DUSCC well suited for dual-speed channel applications. Data rates up to 4Mbits per second are supported. – Single- or dual-address dual transfers – Half- or full-duplex operation – Automatic frame termination on counter/timer terminal count or DMA EOPN input • Interrupt capabilities – Vector output (fixed or modified by status) – Programmable internal priorities – Maskable interrupt conditions • Multi-function programmable 16-bit counter/timer – Bit rate generator The transmitter and receiver each contain a four-deep FIFO with appended transmitter command and receiver status bits and a shift register. This permits reading and writing of up to four characters at a time, minimizing the potential of receiver overrun or transmitter underrun, and reducing interrupt or DMA overhead. In addition, a flow control capability is provided to disable a remote transmitter when the FIFO of the local receiving device is full. – Event counter – Count received or transmitted characters – Delay generator – Automatic bit length measurement • Modem controls – RTS, CTS, DCD, and up to four general purpose pins per channel Two modem control inputs (DCD and CTS) and three modem control outputs (RTS and two general purpose) are provided. Because the modem control inputs and outputs are general purpose in nature, they can be optionally programmed for other functions. – CTS and DCD programmable auto-enables for Tx and Rx – Programmable interrupt on change of CTS or DCD This document contains the electrical specifications for the SCN26562. See SCN26562/SCN68562 User’s Guide for complete functional description. • On-chip oscillator for crystal • TTL compatible • Single +5V power supply FEATURES Asynchronous Mode Features • Character length: 5 to 8 bits • Odd or even parity, no parity, or force parity • Up to two stop bits programmable in 1/16-bit increments • 1X or 16X and Tx clock factors • Parity, overrun, and framing error detection • False start bit detection • Start bit search 1/2-bit time after framing error detection • Break generation with handshake for counting break characters • Detection of start and end of received break • Character compare with optional interrupt on match • Transmits up to 4Mbit/sec data rate Receives up to 2Mbit/sec data General Features • Dual full-duplex synchronous/asynchronous receiver and transmitter • Multiprotocol operation – BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level, etc. – COP: BISYNC, DDCMP – ASYNC: 5–8 bits plus optional parity • Four character receiver and transmitter FIFOs • 0 to 4Mbit/sec data rate • Programmable bit rate for each receiver and transmitter selectable from: – 16 fixed rates: 50 to 38.4k baud rate – One user-defined rate derived from programmable counter/timer – External 1X or 16X clock – Digital phase-locked loop 1995 May 1 1 853-0307 15179 Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) Character-Oriented Protocol Features SCN26562 Bit-Oriented Protocol Features • Character length: 5 to 8 bits • Odd or even parity, no parity, or force parity • LRC or CRC generation and checking • Optional opening PAD transmission • One or two SYN characters • External sync capability • SYN detection and optional stripping • SYN or MARK line-fill on underrun • Idle in MARK or SYNs • Parity, FCS, overrun, and underrun error detection • Character length: 5 to 8 bits • Detection and transmission of residual character: 0–7 bits • Automatic switch to programmed character length for I field • Zero insertion and detection • Optional opening PAD transmission • Detection and generation of FLAG, ABORT, and IDLE bit patterns • Detection and generation of shared (single) FLAG between frames • Detection of overlapping (shared zero) FLAGs • ABORT, ABORT-FLAGs, or FCS FLAGs line-fill on underrun • Idle in MARK or FLAGs • Secondary address recognition including group and global BISYNC Features • EBCDIC or ASCII header, text and control messages • SYN, DLE stripping • EOM (end of message) detection and transmission • Auto transparent mode switching • Auto hunt after receipt of EOM sequence (with closing PAD check address • Single- or dual-octet secondary address • Extended address and control fields • Short frame rejection for receiver • Detection and notification of received end of message • CRC generation and checking • SDLC loop mode capability after EOT or NAK) • Control character sequence detection for both transparent and normal text ORDERING INFORMATION VCC = +5V +5%, TA = 0°C to +70°C DESCRIPTION Serial Data Rate = 4Mbps Maximum DWG # 48-Pin Plastic Dual In-Line Package (DIP) SCN26562C4N48 SOT240-1 52-Pin Plastic Leaded Chip Carrier (PLCC) Package SCN26562C4A52 SOT238-3 ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER RATING UNIT 0 to +70 °C Storage temperature -65 to +150 °C Voltage from VCC to GND3 –0.5 to +7.0 V TA Operating ambient temperature2 TSTG VCC VS Voltage from any pin to ground3 –0.5 to VCC +0.5 V NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature and thermal resistance of 36°C/W junction to ambient for ceramic DIP, 40°C/W for plastic DIP, and 42°C/W for PLCC. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 1995 May 1 2 Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 PIN CONFIGURATIONS N PACKAGE IACKN 1 48 VCC A3 2 47 A4 A2 3 46 A5 A1 4 45 A6 RTxDAKBN/ GPI1BN 5 44 RTxDAKAN/ GPI1AN IRQN 6 43 X1/CLK 42 X2 8 41 RTSAN/ SYNOUTAN TRxCB 9 40 TRxCA RTxCB 10 39 RTxCA 38 34 20 DCDAN/ SYNIAN 33 TOP VIEW PIN FUNCTION 1 2 3 4 5 37 RxDA 36 TxDA 14 35 15 34 16 33 TxDAKAN/ GPI2AN RTxDRQAN/ GPO1AN TxDRQAN/ GPO2AN/RTSAN 17 32 CTSAN/LCAN D7 18 31 D0 D6 19 30 D1 D5 20 29 D2 D4 21 28 D3 18 RDN 22 27 EOPN RESETN 23 26 WRN GND 24 25 CEN 19 20 21 22 23 24 25 26 TxDAKBN/ GPI2BN RTxDRQBN/ GPO1BN TxDRQBN/ GPO2BN/RTSBN CTSBN/LCBN 46 21 7 TxDB 13 47 PLCC RDYN DIP 1 7 8 RTSBN/ SYNOUTBN DCDBN/ 11 SYNIBN RxDB 12 A PACKAGE INDEX CORNER 6 7 8 9 10 11 12 13 14 15 16 17 IACKN A3 A2 A1 RTxDAKBN/ GPI1BN IRQN NC RDYN RTSBN/ SYNOUTBN TRxCB RTxCB DCDBN/ SYNIBN NC RxDB TxDB TxDAKBN/ GPI2BN RTxDRQBN/ GPO1BN TxDRQBN/ GPO2BN/RTSBN CTSBN/LCBN D7 D6 D5 D4 RDN RESETN GND PIN FUNCTION 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 CEN WRN EOPN D3 D2 D1 D0 NC CTSAN/LCAN TxDRQAN/ GPO2AN/RTSAN RTxDRQAN/ GPO1AN TxDAKAN/ GPI2AN TxDA RxDA NC DCDAN/ SYNIAN RTxCA TRxCA RTSAN/ SYNOUTAN X2 X1/CLK RTxDAKAN/ GPI1AN A6 A5 A4 VCC SD00203 Figure 1. Pin Configurations 1995 May 1 3 Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 BLOCK DIAGRAM CHANNEL MODE AND TIMING A/B DPLL CLK MUX A/B D0–D7 BUS BUFFER DPLLA/B BRG INTERFACE/ OPERATION CONTROL COUNTER TIMER A/B ADDRESS DECODE C/T CLK MUX A/B CTCRA/B R/W DECODE RDYN CTPRLA/B WRN RDN A1–A6 CTPRHA/B CTHA/B DMA CONTROL MPU INTERFACE CTLA/B CCRA/B CEN PCRA/B RESETN INTERNAL BUS RSRA/B TRSRA/B ICTSRA/B GSR RTxDRQAN/GPO1AN CMR1A/B RTxDRQBN/GPO1BN CMR2A/B TxDRQAN/GPO2AN TxDRQBN/GPO2BN RTxDAKAN/GPI1AN TRANSMIT A/B TRANS CLK MUX TPRA/B TTRA/B TX SHIFT REG OMRA/B DMA INTERFACE TxD A/B TRANSMIT 4 DEEP FIFO RTxDAKBN/GPI1BN TxDAKAN/GPI2AN TxDAKBN/GPI2BN EOPN CONTROL CRC GENERATOR TRxCA/B SPEC CHAR GEN LOGIC RTxCA/B CTSAN/LCAN CTSBN/LCBN DCDBN/SYNIBN RECEIVER A/B SPECIAL FUNCTION PINS RCVR CLK MUX DCDAN/SYNIAN RTSBN/SYNOUTBN RPRA/B RTSAN/SYNOUTAN RTRA/B S1RA/B INTERRUPT CONTROL S2RA/B RxD A/B ICRA/B IRQN IACKN RCVR SHIFT REG IERA/B IVR RECEIVER 4 DEEP FIFO IVRM DUSCC LOGIC CRC ACCUM BISYNC COMPARE LOGIC X1/CLK X2 OSCILLATOR SD00204 Figure 2. Block Diagram 1995 May 1 4 Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 PIN DESCRIPTION MNEMONIC PIN NO. TYPE NAME AND FUNCTION DIP PLCC A1–A6 4–2, 47–45 4–2, 51–49 I D0–D7 31–28, 21–18 33–30, 23–20 I/O RDN 22 24 I Read strobe. WRN 26 28 I Write strobe. CEN 25 27 I Chip select. RDYN 7 8 O Ready. IRQN 6 6 O Interrupt request. Address lines. Bidirectional data bus. IACKN 1 1 I Interrupt acknowledge. X1/CLK 43 47 I Crystal 1 or external clock. X2 42 46 I Crystal 2. RESETN 23 25 I Master reset. RxDA, RxDB 37, 12 40, 14 I Channel A (B) receiver serial data. TxDA, TxDB 36, 13 39, 15 O Channel A (B) transmitter serial data. RTxCA, RTxCB 39, 10 43, 11 I/O Channel A (B) receiver/transmitter clock. TRxCA, TRxCB 40, 9 44, 10 I/O Channel A (B) transmitter/receiver clock. CTSA/BN, LCA/BN 32, 17 35, 19 I/O Channel A (B) clear-to-send input or loop control output. DCDA/BN, SYNIA/BN 38, 11 42, 12 I Channel A (B) data carrier detected or external sync. RTxDRQA/BN, GPO1A/BN 34, 15 37, 17 O Channel A (B) receiver/transmitter DMA service request or general purpose output. TxDRQA/BN, GPO2A/BN, RTSA/BN 33, 16 36, 18 O Channel A (B) transmitter DMA service request, general purpose output or request-to-send. RTxDAKA/BN, GPI1A/BN 44, 5 48, 5 I Channel A (B) receiver/transmitter DMA acknowledge or general purpose input 1. TxDAKA/BN, GPI2A/BN 35, 14 38, 16 I Channel A (B) transmitter DMA acknowledge or general purpose input 2. EOPN 27 29 I/O DMA transfer complete. 41, 8 45, 9 O Channel A (B) request-to-send or Sync detect. VCC 48 52 I Power input. GND 24 26 I Signal and power ground. RTSA/BN, SYNOUTA/BN 1995 May 1 5 Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 DC ELECTRICAL CHARACTERISTICS1, 3 TA = 0°C to +70°C, VCC = 5.0V +5% SYMBOL VIL VIH VOL VOH PARAMETER Min Input low voltage: All except X1/CLK X1/CLK Input high voltage: All except X1/CLK X1/CLK Typ 2.0 2.4 Output low voltage: All except IRQN IRQN Output high voltage: (Except open drain outputs) IOL = 5.3mA IOL = 8.8mA low current3 high current3 IILX1 IIHX1 X1/CLK input X1/CLK input IILX2 IIHX2 X2 input low current3 X2 input high current3 IIL Input low current RESETN, TxDAKN, RxDAKN II Input leakage current IOZH IOZL Output off current high, 3-State data bus Output off current low, 3-State data bus IODL Open drain output low current in off state: EOPN IRQN, RDYN Open drain output high current in off state: EOPN, IRQN, RDYN IODH LIMITS TEST CONDITIONS ICC Power supply current CIN COUT CI/O Input capacitance2 Output capacitance2 Input/output capacitance2 Max UNIT 0.8 0.4 V V VCC V V V V 0.5 0.5 IOH = –400µA 2.4 VIN = 0, X2 = GND VIN = VCC, X2 = GND –5.5 VIN = 0, X1 = open VIN = VCC, X1 = open –100 VIN = 0 –40 VIN = 0 to VCC –5 VIN = VCC VIN = 0 –5 V 0.0 1.0 mA mA 100 µA µA µA VIN = 0 5 µA 5 µA µA –25 µA µA –120 –5 VIN = VCC 5 µA VO = 0 to VCC 275 mA VCC = GND = 0 VCC = GND = 0 VCC = GND = 0 10 15 20 pF pF pF NOTES: 1. Parameters are valid over specified temperature range. 2. These values were not explicitly tested; they are guaranteed by design and characterization data. 3. X1/CLK and X2 are not tested with a crystal installed. AC ELECTRICAL CHARACTERISTICS1, 2, 3, 4 TA = 0°C to +70°C, VCC = 5V +5% LIMITS SYMBOL PARAMETER SCN26562C4 Min tRELREH RESETN low to RESETN high 1.2 Max SCN26562C2 Min 1.2 UNIT Max µs NOTES: 1. Parameters are valid over specified temperature range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.8V and 2.0V with a transition time of 20ns maximum. For X1/CLK, this swing is between 0.4V and 2.4V. All time measurements are referenced at input voltages of 0.4V and 2.4V and output voltages of 1.2V and 2.0V, as appropriate. 3. See Figure 17 for test conditions for outputs. 4. Tests for open drain outputs are intended to guarantee switching of the output transistor. Measurement of this response is referenced from midpoint of the switching signal to a point 0.2V above the actual output signal level. This point represents noise margin that assures true switching has occurred. RESETN tRELREH SD00205 Figure 3. Reset Timing 1995 May 1 6 Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) A6–A1 tADVRDL tCEHCEL tRDHCEH CEN tCELRDL tRDLADI tRDLRDH tRDHRDL RDN tRDLDDV tRDHDDF D0–D7 tRDLRYL tRYZDDV tRDHDDI RDYN 1 NOTES: 1. Wait on Rx. Receiver FIFO empty. 2. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle. SD00206 Figure 4. Read Cycle LIMITS SYMBOL PARAMETER SCN26562C4 Min tADVRDL tCELRDL tRDLADI tRDLRYL tRDLDDV tRDLRDH tRYZDDV tRDHCEH tCEHCEL tRDHDDI tRDHRDL tRDHDDF 1995 May 1 Address valid to RDN low CEN low to RDN low RDN low to address invalid RDN low to RDYN low RDN low to read data valid RDN low to RDN high RDYN high impedance to read data valid RDN high to CEN high CEN high to CEN low RDN high to read data invalid RDN high to RDN low RDN high to data bus floating 10 0 150 300 0 160 10 160 7 Max 275 280 100 75 SCN26562C2 Min 10 0 150 310 0 170 10 170 UNIT Max 275 300 100 75 ns ns ns ns ns ns ns ns ns ns ns ns Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) A6–A1 tCEHCEL tADVWRL tWRHCEH CEN tCELWRL tWRLADI tWRLWRH tWRHWRL WRN tWDVWRH tWRHWDI D0–D7 tWRLRYL RDYN 1 NOTES: 1. Wait on Tx. Transmitter FIFO full. 2. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle. SD00207 Figure 5. Write Cycle LIMITS SYMBOL PARAMETER SCN26562C4 Min tADVWRL tCELWRL tWRLRYL tWRHCEH tWRLWRH tWDVWRH tCEHCEL tWRLADI tWRHWRL tWRHWDI 1995 May 1 Address valid to WRN low CEN low to WRN low WRN low to READY low WRN high to CEN high WRN low to WRN high Write data valid to WRN high CEN high to CEN low WRN low to address invalid WRN high to WRN low WRN high to write data invalid 8 Max SCN26562C2 Min 10 0 10 0 0 300 100 160 150 160 10 0 310 100 170 150 170 10 275 UNIT Max 275 ns ns ns ns ns ns ns ns ns ns Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) SERVICE ROUTINE A INTERRUPT REQUEST LOCKED IRQN Cleared through software VECTOR SETTLING IACKN A VECTOR LOCKED tIALDDV A C D7–D0 C B tIAHDDI tIAHDDF NOTES: A ICR[5:4] = 01 or 10 (mode 1 or mode 2) B Call instruction (mode 2) C ICR[5:4] = 11 (mode 3) SD00208 Figure 6. Interrupt Acknowledge Cycle LIMITS SYMBOL PARAMETER SCN26562C4 Min tIALDDV tIAHDDF tIAHDDI IACKN low to data bus valid IACKN high to data bus floating IACKN high to data bus invalid 10 SCN26562C2 Max Min 280 150 10 UNIT Max 280 150 ns ns ns CEN WRN tWRHGOV GPO1_N AND/OR GPO2_N OLD DATA NEW DATA SD00209 Figure 7. Output Port Timing LIMITS SYMBOL PARAMETER SCN26562C4 Min tWRHGOV 1995 May 1 WRN high to GPO output data valid Max 300 9 SCN26562C2 Min UNIT Max 300 ns Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) CEN RDN tGIVRDL tRDLGII GPI1N AND/OR GPI2N SD00210 Figure 8. Input Port Timing LIMITS SYMBOL PARAMETER SCN26562C4 Min tGIVRDL tRDLGII GPI input valid to RDN low RDN low to GPI input invalid UNIT SCN26562C2 Max Min 20 100 Max 20 100 ns ns tCLHCLL tCCHCCL tRCHRCL tTCHTCL X1/CLK CTCLK RxC TxC tCLLCLH tCCLCCH tRCLRCH tTCLTCH SD00211 Figure 9. Clock LIMITS SYMBOL PARAMETER SCN26562C4 Min tCLHCLL tCLLCLH tCCHCCL tCCLCCH tRCHRCL tRCLRCH tTCHTCL tTCLTCH fCL fCC fRC fTC 1995 May 1 X1/CLK high to low time X1/CLK low to high time C/T CLK high to low time C/T CLK low to high time RxC high to low time RxC low to high time TxC high to low time TxC low to high time X1/CLK frequency C/T CLK frequency RxC frequency (16X or 1X) TxC frequency (16X or 1X) Typ 25 25 100 100 110 110 110 110 2.0 0 0 0 14.7456 10 UNIT SCN26562C2 Max Min 16.0 4.0 4.0 4.0 25 25 100 100 150 150 150 150 2.0 0 0 0 Typ 14.7456 Max 16.0 4.0 2.5 2.5 ns ns ns ns ns ns ns ns MHz MHz MHz MHz Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) 1 BIT TIME (1 OR 16 CLOCKS) TxC (INPUT) tCILTXV TxD tCOLTXV TxC (1X OUTPUT) SD00212 Figure 10. Transmit Timing LIMITS SYMBOL PARAMETER SCN26562C4 Min tCILTXV tCOLTXV SCN26562C2 Max TxC input low (1X) to TxD output TxC input low (16X) to TxD output TxC output low to TxD output Min 240 435 50 UNIT Max 240 435 50 ns ns ns tRCHSOL SYNOUTN tSILRCH tRCHSIH SYNIN RXC (1X) INPUT tRXVRCH tRCHRXI RxD SD00213 Figure 11. Receive Timing LIMITS SYMBOL PARAMETER SCN26562C4 Min tRXVRCH tRCHRXI tSILRCH tRCHSIH tRCHSOL 1995 May 1 RxD data valid to RxC high: For NRZ data For NRZI, Manchester, FM0, FM1 data RxC high to RxD data invalid: For NRZ data For NRZI, Manchester, FM0, FM1 data SYNIN low to RxC high RxC high to SYNIN high RxC high to SYNOUT low 11 Max SCN26562C2 Min 50 120 50 130 50 10 100 50 50 10 100 50 300 UNIT Max ns ns 300 ns ns ns ns ns Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) tWRHEOZ EOPN (OUTPUT) tWRLEOL RTxDRQN OR TxDRQN CEN tWRLTRH A WRN D7–D0 tEILWRH tWRHEIH EOPN (INPUT) A The TxFIFO is addressed during this write cycle. SD00214 Figure 12. Transmit Dual Address DMA Timing LIMITS SYMBOL PARAMETER SCN26562C4 Min tWRLTRH tWRLEOL tWRHEOZ tEILWRH tWRHEIH 1995 May 1 WRN low to Tx DMA REQN high WRN low to EOPN output low WRN high to EOPN output high impedance EOPN input low to WRN high WRN high to EOPN input high 50 50 12 Max 320 225 225 SCN26562C2 Min 50 50 UNIT Max 320 225 225 ns ns ns ns ns Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) RTxDRQN tRDLRRH CEN A RDN D7–D0 tRDLEOL tRDHEOZ EOPN (OUTPUT) A The RxFIFO is addressed during this read cycle. SD00215 Figure 13. Receive Dual Address DMA Timing LIMITS SYMBOL PARAMETER SCN26562C4 Min tRDLRRH tRDLEOL tRDHEOZ 1995 May 1 RDN low to Rx DMA REQN high RDN low to EOPN output low RDN high to EOPN output high impedance Max 320 300 225 13 SCN26562C2 Min UNIT Max 320 300 225 ns ns ns Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) TxRQN tTAHTAL tTALTRH TxDAKN tTALTAH WRN A MEMRN B tTAHEIH tEILTAH EOPN (INPUT) tWDVTAH tTAHWDI D7–D0 tTAHEOF tTALEOL EOPN (OUTPUT) NOTES: A Ignored by the DUSCC since CEN is not asserted, but it can be used externally to qualify TxDAKN. B Memory read signal; not seen by DUSCC. SD00216 Figure 14. DMA-Transmit Single Address Mode LIMITS SYMBOL PARAMETER SCN26562C4 Min tTAHTAL tTALTAH tTALTRH tWDVTAH tTAHWDI tTALEOL tTAHEOF tEILTAH tTAHEIH 1995 May 1 Transmit DMA ACKN high to low time Transmit DMA ACKN low to high time Tx DMA ACKN low to Tx DMA REQN high Write data valid to Tx DMA ACKN high Tx DMA ACKN high to write data invalid Tx DMA ACKN low to EOPN output low Tx DMA ACKN high to EOPN output float EOPN input low to Tx DMA ACKN high Tx DMA ACKN high to EOPN input high Max 100 250 90 30 50 50 14 SCN26562C2 Min 100 250 250 170 200 90 30 50 50 UNIT Max 250 170 200 ns ns ns ns ns ns ns ns ns Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) RxDRQN tRAHRAL tRALRRH RxDAKN tRALRAH RDN A MEMWN B tRAHEOF tRALEOL EOPN (OUTPUT) tRALDDV tRAHDDI D7–D0 tRAHDDF NOTES: A Ignored by the DUSCC bit; it can be used to qualify RxDAKN. B Memory read signal; not seen by DUSCC. SD00217 Figure 15. DMA-Receive Single Address Mode LIMITS SYMBOL PARAMETER SCN26562C4 Min tRAHRAL tRALRAH tRALRRH tRALEOL tRAHEOF tRALDDV tRAHDDI tRAHDDF 1995 May 1 Receive DMA ACKN high to low time Receive DMA ACKN low to high time Rx DMA ACKN low to Rx DMA REQN high Rx DMA ACKN low to EOPN output low Rx DMA ACKN high to EOPN output float Rx DMA ACKN low to read data valid Rx DMA ACKN high to read data invalid Rx DMA ACKN high to data bus float 160 250 10 15 Max 320 200 225 225 125 SCN26562C2 Min 160 250 10 UNIT Max 320 200 225 225 125 ns ns ns ns ns ns ns ns Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 AC ELECTRICAL CHARACTERISTICS (Continued) VM RDN/WRN tRWHIRH VOL +0.2V IRQN VOL SD00218 Figure 16. Interrupt Timing LIMITS SYMBOL PARAMETER SCN26562C4 Min tRWHIRH SCN26562C2 Max RDN/WRN high to IRQN high for: Read RxFIFO (RxRDY interrupt) Write TxFIFO (TxRDY interrupt) Write RSR (Rx condition interrupt) Write TRSR (Rx/Tx interrupt) Write ICTSR (counter/timer interrupt) Min 450 450 400 400 400 UNIT Max 450 450 400 400 400 ns ns ns ns ns X1/CLK WRN COMMAND VALID SD00219 Figure 17. Command Timing RxC 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 RxD LCN a. Loop Control Output Assertion RxC 1 9 RxD LCN b. Loop Control Output Negation SD00220 Figure 18. Relationship Between Received Data and the Loop Control Output 1995 May 1 16 Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC) SCN26562 2.7K VDD IRQN 50pF 820Ω RDYN +5.0V 150pF 1K VDD EOPN 50pF 710 ALL OTHER OUTPUTS +5.0V 150pF NOTE: All CL includes 50pF stray capacitance, i.e., CL = 150pF = 100pF discrete +50pF stray. SD00221 Figure 19. Test Conditions for Outputs 1995 May 1 17