PHILIPS SC26C562_06

INTEGRATED CIRCUITS
SC26C562
CMOS dual universal serial
communications controller (CDUSCC)
Product data sheet
Supersedes data of 2004 Mar 29
2006 Aug 10
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
• Watchdog timer
• 0 to 10 Mbit/s data rate
• Programmable bit rate for each receiver and transmitter selectable
DESCRIPTION
The Philips Semiconductors SC26C562 Dual Universal Serial
Communications Controller (CDUSCC) is a single-chip CMOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SC26C562 interfaces to synchronous
bus MPUs and is capable of program-polled, interrupt driven,
block-move or DMA data transfers.
from:
– 19 fixed rates: 50 to 64 kbaud
– One user-defined rate derived from programmable
counter/timer
– External 1X or 16X clock
– Digital phase-locked loop
The SC26C562 (CDUSCC) is (PIN) hardware and (REGISTER)
software compatible with the existing SCN26562 (DUSCC).
CDUSCC will automatically configure to the NMOS DUSCC register
map (default mode) on power-up.
• Parity and FCS (frame check sequence LRC or CRC) generation
and checking
• Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multifunction counter/timer, a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides sixteen common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
counter/timer, or from an external 1X or 16X clock, making the
CDUSCC well-suited for dual-speed channel applications. Data
rates up to 10 Mbit/s are supported.
Manchester
• Programmable channel mode: full- or half-duplex, auto-echo, or
local loopback
• Programmable data transfer mode: polled, interrupt, DMA, wait
• DMA interface
– Compatible with Synchronous and Asynchronous bus DMA
controllers
– Half- or full-duplex operation
– Single or dual address data transfers
– Automatic frame termination on counter/ timer terminal count or
DMA DONE (EOPN)
The transmitter and receiver each contain a sixteen-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to sixteen characters
at a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.
• Transmit path clear status
• High speed data bus interface: 160 ns bus cycle
• DPLL operation up to 312.5 kHz with internal clock
• Interrupt capabilities
Two modem control inputs (DCD and CTS) and three modem
control outputs (RTS and two general purpose) are provided.
Because the modem control inputs and outputs are general purpose
in nature, they can be optionally programmed for other functions.
– Vector output (fixed or modified by status)
– Individual interrupt enable bits
– Programmable internal priorities
– Maskable interrupt conditions
The SC26C562 CDUSCC is optimized to interface with processors
using a synchronous bus interface, such as the 8086, and iAPX86
family. For systems using an asynchronous bus, such as the 68000
and 68010, refer to the SC68C562 documentation.
– 80XX/X compatible
• Multi-function programmable 16-bit counter/timer
– Bit rate generator
– Event counter
Refer to the CMOS Dual Universal Serial Communication Controller
(CDUSCC) User’s Manual for a complete operational description.
– Count received or transmitted characters
– Delay generator
– Automatic bit length measurement
FEATURES
General Features
• Modem controls
– RTS, CTS, DCD, and up to four general purpose I/O pins per
channel
• Dual full-duplex synchronous/ asynchronous receiver and
transmitter
– CTS and DCD programmable auto-enables for Tx and Rx
• Multi-protocol operation
– Programmable interrupt on change of CTS or DCD
• On-chip oscillator for crystal
• TTL compatible
• Single +5 V power supply
– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
etc.
– COP: Single SYNC, dual SYNC, BiSYNC, DDCMP
– ASYNC: 5-8 bits plus optional parity
• Sixteen character receive and transmit FIFOs with interrupt
threshold control
• FIFO’ed status bits
2006 Aug 10
2
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
• Extended address and control fields
• Short frame rejection for receiver
• Detection and notification of received end of message
• CRC generation and checking
• SDLC loop mode capability
Asynchronous Mode Features
• Character length: 5 to 8 bits
• Odd or even parity, no parity, or force parity
• Up to two stop bits programmable in 1/16-bit increments
• 1X or 16X Rx and Tx clock factors
• Parity, overrun and framing error detection
• False start bit detection
• Break generation with handshake for counting break characters
• Detection of start and end of received break
• Character compare with optional interrupt on match
• Transmit and receive up to 10 Mbit/s at 1× or 1 Mbit/s at 16× data
Character-Oriented Protocols
• Character length: 5 to 8 bits
• Odd or even parity, no parity, or force parity
• LRC or CRC generation and checking
• Optional opening PAD transmission
• One or two SYN characters
• External sync capability
• SYN detection and optional stripping
• SYN or MARK line-fill or underrun
• Idle in MARK or SYNs
• Parity, FCS, overrun and underrun error detection
• Optional SYNC exclusion from FCS
• BISYNC features
rates
Bit-Oriented Protocol
• Character length: 5 to 8 bits
• Detection and transmission of residual character: 0–7 bits
• Automatic switch to programmed character length for I field
• Zero insertion and deletion
• Optional opening PAD transmission
• Detection and generation of FLAG, ABORT, and IDLE bit patterns
• Transmit 7 or 8 bit ABORT
• Detection and generation of shared (single) FLAG between
– EBCDIC or ASCII header, text and control messages
– SYN, DLE stripping
– EOM (end of message) detection and transmission
– Auto transparency mode switching
frames
• Detection of overlapping (shared zero) FLAGs
• Idle in MARK or FLAGs
• Secondary address recognition including group and global
– Auto hunt after receipt of EOM sequence (with closing PAD
check after EOT or NAK)
– Control character sequence detection for both transparent and
normal text
– Parity generation for data and LRC characters
address
• Single- or dual-octet secondary address
ORDERING INFORMATION
Tamb = 0 °C to +70 °C. Serial data rate = 10 Mbit/s maximum
Type number
SC26C562C1A
Package
Name
Description
Version
PLCC52
plastic leaded chip carrier; 52 leads
SOT238-2
ABSOLUTE MAXIMUM RATINGS1
PARAMETER
RATING
UNIT
0 to +70
°C
Storage temperature
–65 to +150
°C
Voltage from VCC to GND3
–0.5 to +7.0
V
–0.5 to VCC +0.5
V
SYMBOL
Tamb
Operating ambient temperature2
Tstg
VCC
VS
Voltage from any pin to ground3
2006 Aug 10
3
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
BLOCK DIAGRAM
CHANNEL
MODE AND
TIMING A/B
DPLL CLK
MUX A/B
D0–D7
BUS
BUFFER
DPLLA/B
BRG
A7 CONTROL
LOGIC
A7
INTERFACE/
OPERATION
CONTROL
COUNTER
TIMER A/B
ADDRESS
DECODE
C/T CLK
MUX A/B
CTCRA/B
R/W
DECODE
RDYN
CTPRLA/B
WRN
RDN
A1–A6
CTPRHA/B
CTHA/B
DMA
CONTROL
MPU
INTERFACE
CEN
CCRA/B
RESETN
PCRA/B
CTLA/B
TRANSMIT
A/B
INTERNAL BUS
RSRA/B
TRSRA/B
ICTSRA/B
GSR
RTxDRQAN/GPO1AN
CMR1A/B
RTxDRQBN/GPO1BN
CMR2A/B
TxDRQAN/GPO2AN
TxDRQBN/GPO2BN
RTxDAKAN/GPI1AN
OMRA/B
DMA
INTERFACE
TRCR A/B
TRMR A/B
TxDAKAN/GPI2AN
CONTROL
RTxCA/B
DCDBN/SYNIBN
TxD A/B
CRC
GENERATOR
SPEC CHAR
GEN LOGIC
RECEIVER
A/B
CTSAN/LCAN
CTSBN/LCBN
TX SHIFT
REG
TELR
A/B
CID
TxDAKBN/GPI2BN
EOPN
TRxCA/B
TPRA/B
TTRA/B
TRANSMIT
16 DEEP
FIFO
FTLR A/B
RTxDAKBN/GPI1BN
TRANS CLK
MUX
SPECIAL
FUNCTION
PINS
RCVR CLK
MUX
DCDAN/SYNIAN
RPRA/B
RTSBN/SYNOUTBN
RTRA/B
RTSAN/SYNOUTAN
S1RA/B
S2RA/B
INTERRUPT
CONTROL
RCVR
SHIFT REG
ICRA/B
IRQN
IACKN
IVRM
IER1 A/B
RFLR
A/B
IER2 A/B
IER3 A/B
CDUSCC
LOGIC
CRC
ACCUM
BISYNC
COMPARE
LOGIC
X1/CLK
X2
RxD A/B
RECEIVER
16 DEEP
FIFO
IERA/B
OSCILLATOR
SD00239
Figure 1. Block diagram
2006 Aug 10
4
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
PIN CONFIGURATION
INDEX
CORNER
7
1
47
8
46
PLCC
34
20
21
33
TOP VIEW
Pin Function
Pin Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
IACKN
A3
A2
A1
RTxDAKBN/GPI1BN
IRQN
NC
RDYN
RTSBN/SYNOUTBN
TRxCB
RTxCB
DCDBN/SYNIBN
NC
RxDB
TxDB
TxDAKBN/GPI2BN
RTxDRQBN/GPO1BN
TxDRQBN/GPO2BN/RTSBN
CTSBN/LCBN
D7
D6
D5
D4
RDN
RESETN
GND
CSN
WRN
EOPN
D3
D2
D1
D0
NC
CTSAN/LCAN
TxDRQAN/GPO2AN/RTSAN
RTxDRQAN/GPO1AN
TxDAKAN/GPI2AN
TxDA
RxDA
NC
DCDAN/SYNIAN
RTxCA
TRxCA
RTSAN/SYNOUTAN
X2
X1/CLK
RTxDAKAN/GPI1AN
A6
A5
A4
VCC
SD00740
Figure 2. Pin configuration
PIN DESCRIPTION
PIN
TYPE
A1–A6
MNEMONIC
4-2,
51-49
I
D0–D7
33-30,
23-20
I/O
Bidirectional Data Bus: Active-HIGH, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All data,
command and status transfers between the CPU and the CDUSCC take place over this bus. The
data bus is enabled when CSN and RDN, or CSN and WRRN are LOW during interrupt
acknowledge cycles and single address DMA acknowledge cycles.
RDN
24
I
Read Strobe: Active-LOW input. When active and CSN is also active, causes the content of the
addressed register to be present on the data bus. RDN is ignored unless CSN is active.
WRN
28
I
Write Strobe: Active-LOW input. When active and CSN is also active, the content of the data bus is
loaded into the addressed register. The transfer occurs on the rising edge of WRN. WRN is ignored
unless CEN is active.
CSN
27
I
Chip Select: Active-LOW input. When active, data transfers between the CPU and the CDUSCC are
enabled on D0–D7 as controlled by RDN or WRN and A1–A6 inputs. When CSN is HIGH, the data
lines are placed in the 3-State condition (except during interrupt acknowledge cycles and single
address DMA transfers).
RDYN
8
O
Ready: Active-LOW, open drain. Used to synchronize data transfers between the CPU and the
CDUSCC. It is valid only during read and write cycles where the CDUSCC is configured in ‘wait on
Rx’, ‘wait on Tx’ or ‘wait on Tx or Rx’ modes, otherwise it is always inactive. RDYN becomes active
on the leading edge of RDN and WRN if the requested operation cannot be performed (viz, no data
in RxFIFO in the case of a read or no room in the TxFIFO in the case of a write).
2006 Aug 10
NAME AND FUNCTION
Address Lines: Active-HIGH. Address inputs which specify which of the internal registers is
accessed for read/write operation.
5
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
MNEMONIC
SC26C562
PIN
TYPE
IRQN
6
O
Interrupt Request: Active-LOW, open-drain. This output is asserted upon occurrence of any
enabled interrupting condition. The CPU can read the general status register to determine the
interrupting condition(s), or can respond with an interrupt acknowledge cycle to cause the CDUSCC
to output an interrupt vector on the data bus.
IACKN
1
I
Interrupt Acknowledge: Active-LOW. When IACKN is asserted, the CDUSCC responds by either
forcing the bus into high-impedance, placing a vector number, call instruction or zero on the data
bus. The vector number can be modified or unmodified by the status. If no interrupt is pending,
IACKN is ignored and the data bus placed in high-impedance.
X1/CLK
47
I
Crystal or External Clock: When using the crystal oscillator, the crystal is connected between pins
X1 and X2. If a crystal is not used, an external clock is supplied at this input. This clock is used to
drive the internal bit rate generator, as an optional input to the counter/timer or DPLL, and to provide
other required clocking signals. When a crystal is used, a capacitor must be connected from this pin
to ground.
X2
46
O
Crystal 2: Connection for other side of crystal. When a crystal is used, a capacitor must be
connected from this pin to ground. If an external clock is used on X1, this pin should be left floating.
RESETN
25
I
Master Reset: Active-LOW. A LOW on this pin resets the transmitters and receivers and resets the
registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is asynchronous, i.e., no clock is
required.
RxDA, RxDB
40, 14
I
Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If external
receiver clock is specified for the channel, the input is sampled on the rising edge of the clock.
TxDA, TxDB
39, 15
O
Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted first. This
output is in the marking (HIGH) condition when the transmitter is disabled or when the channel is
operating in local loopback mode. If external transmitter clock is specified for the channel, the data is
shifted on the falling edge of the clock.
RTxCA, RTxCB
43, 11
I/O
Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to supply the
receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the transmitter shift clock (1X), or the receiver sampling clock (1X).
TRxCA, TRxCB
44, 10
I/O
Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver, transmitter,
counter/timer, or DPLL clock. As an output, it can supply the counter/timer output, the DPLL output,
the transmitter shift clock (1X), the receiver sampling clock (1X), the transmitter BRG clock (16X),
The receiver BRG clock (16X), or the internal system clock (X1 ÷ 2).
CTSA/BN,
LCA/BN
35, 19
I/O
Channel A (B) Clear-to-Send Input or Loop Control Output: Active-LOW. The signal can be programmed to act as an enable for the transmitter when not in loop mode. The CDUSCC detects logic
level transitions on this input and can be programmed to generate an interrupt when a transition occurs. When operating in the BOP loop mode, this pin becomes a loop control output which is asserted and negated by CDUSCC commands. This output provides the means of controlling external
loop interface hardware to go on-line and off-line without disturbing operation of the loop.
DCDA/BN,
SYNIA/BN
42, 12
I
Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-LOW input, it acts as an enable for the receiver or can be used as a
general purpose input. For the DCD function, the CDUSCC detects logic level transitions on this pin
and can be programmed to generate an interrupt when a transition occurs. As an active-LOW
external sync input, it is used in COP mode to obtain character synchronization for the receiver
without receipt of a SYN character. This mode can be used in disc or tape controller applications or
for the optional byte timing lead in X.21.
RTxDRQA/BN,
GPO1A/BN
37, 17
O
Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose Output:
Active-LOW. For half-duplex DMA operation, this output indicates to the DMA controller that one or
more characters are available in the receiver FIFO (when the receiver is enabled) or that the transmit
FIFO is not full (when the transmitter is enabled). For full-duplex DMA operation, this output indicates
to the DMA controller that data is available in the receiver FIFO. In non-DMA mode, this pin is a
general purpose output that can be asserted and negated under program control.
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
36, 18
O
Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-LOW. For full-duplex DMA operation, this output indicates to the DMA
controller that the transmit FIFO is not full and can accept more data. When not in full-duplex DMA
mode, this pin can be programmed as a general purpose or a Request-to-Send output, which can be
asserted and negated under program control.
RTxDAKA/BN,
GPI1A/BN
48, 5
I
Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input: Active-LOW.
For half-duplex single address operation, this input indicates to the CDUSCC that the DMA controller
has acquired the bus and that the requested bus cycle (read receiver FIFO when the receiver is
enabled or load transmitter FIFO when the transmitter is enabled) is beginning. For full-duplex single
address DMA operation, this input indicates to the CDUSCC that the DMA controller has acquired
the bus and that the requested read receiver FIFO bus cycle is beginning. Because the state of this
input can be read under program control, it can be used as a general purpose input when not in
single address DMA mode.
2006 Aug 10
NAME AND FUNCTION
6
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
MNEMONIC
SC26C562
PIN
TYPE
NAME AND FUNCTION
38, 16
I
Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-LOW. When the
channel is programmed for full-duplex single address DMA operation, this input is asserted to
indicate to the CDUSCC that the DMA controller has acquired the bus and that the requested load
transmitter FIFO bus cycle is beginning. Because the state of this input can be read under program
control, it can be used as a general purpose input when not in full-duplex single address DMA mode.
29
I/O
Done (EOP): Active-LOW, open-drain. EOPN can be used and is active in both DMA and non-DMA
modes. As an input, EOPN indicates the last DMA transfer cycle to the TxFIFO. As an output, EOPN
indicates either the last DMA transfer from the RxFIFO or that the transmitted character count has
reached terminal count.
RTSA/BN,
SYNOUTA/BN
45, 9
O
Channel A (B) Sync Detect or Request-to-Send: Active-LOW. If programmed as a sync output, it
is asserted one bit time after the specified sync character (COP or BISYNC modes) or a FLAG (BOP
modes) is detected by the receiver. As a Request-to-Send modem control signal, it functions as
described previously for the TxDRQN/RTSN pin.
VCC
34, 52
I
+5 V Power Input
GND
26, 13,
41, 7
I
Signal and Power Ground Input
TxDAKA/BN,
GPI2A/BN
EOPN
2006 Aug 10
7
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
DC ELECTRICAL CHARACTERISTICS4,5
Tamb = 0 °C to +70 °C, VCC = 5.0 V ± 10 %4,5
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
Min
Typ
Max
–
–
–
–
0.8
0.8
V
V
2.0
0.8 × VCC
–
–
–
VCC
V
V
IOL = 5.3 mA
IOL = 8.8 mA
–
–
–
–
–
0.5
V
V
IOH = –400 µA
VCC – 0.5
–
0.5
V
VIL
Input LOW voltage:
All except X1/CLK
X1/CLK
VIH
Input HIGH voltage except X1/CLK
All except X1/CLK
X1/CLK
VOL
Output LOW voltage:
All except IRQN7
IRQN
VOH
Output HIGH voltage
(Except open drain outputs)
IILX1
X1/CLK input LOW current10
VIN = 0, X2 = open
–150
–
0.0
µA
IIHX1
X1/CLK input HIGH current10
VIN = VCC, X2 = GND
–
–
150
µA
ISCX2
SC
X2 short circuit current
IIL
Input LOW current
RESETN, TxDAKN, RxDAKN
II
Input leakage current
IOZH
Output off current HIGH, 3-State data bus
IOZL
IODL
X1 = open, VIN = 0 V
–
–
–15
mA
X1 = open, VIN = VCC
–
–
+15
mA
VIN = 0 V
–15
–
–0.5
µA
VIN = 0 V to VCC
–1
–
+1
µA
VIN = VCC
–
–
+1
µA
Output off current LOW, 3-State data bus
VIN = 0 V
–1
–
–
µA
Open drain output LOW current in off state:
EOPN, RDYN
IRQN
VIN = 0 V
VIN = 0 V
–15
–1
–
–
–0.5
–
µA
µA
IODH
Open drain output HIGH current in off state:
EOPN, IRQN, RDYN
VIN = VCC
–1
–
1
µA
ICC13
Power supply current
(see Figure 19 for graphs)
–
25
80
mA
CIN
Input capacitance9
VCC = GND = 0 V
–
–
10
pF
COUT
Output capacitance9
VCC = GND = 0 V
–
–
15
pF
CI/O
Input/output capacitance9
VCC = GND = 0 V
–
–
20
pF
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. Clock may be stopped (DC) for testing purposes, or when CDUSCC is in non-operational modes.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range.
5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2 V and 3.0 V with a
transition time of 20 ns maximum. For X1/CLK, this swing is between 0.2 V and 4.4 V. All time measurements are referenced at input
voltages of 0.2 V and 3.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
6. See Figure 20 for test conditions for outputs.
7. Tests for open drain outputs are intended to guarantee switching of the output transistor. Measurement of this response is referenced from
midpoint of the switching signal to a point 0.2 V above the actual output signal level. This point represents noise margin that assures true
switching has occurred.
8. Execution of the valid command (after it is latched) requires 3 rising edges of X1 (see Figure 15).
9. These values were not explicitly tested; they are guaranteed by design and characterization data.
10. X1/CLK and X2 are not tested with a crystal installed.
11. X1/CLK frequency must be at least the faster of the receiver or transmitter serial data rate.
12. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CSN as the ‘strobing’ input. CSN
and RDN (also CSN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
13. VO = 0 V to VCC, Rx and Tx clocks at 10 MHz, X1 clock at 10 MHz.
2006 Aug 10
8
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS4,5,6,7
Tamb = 0 °C to +70 °C; VCC = 5 V ± 10 %
RESETN
tRELREH
SD00205
Figure 3. Reset Timing
SYMBOL
tRELREH
LIMITS
PARAMETER
RESETN LOW to RESETN HIGH
Min
Max
200
–
UNIT
ns
A6–A1
tADVRDL
tCEHCEL
tRDHCEH
CSN (CEN)
tCELRDL
tRDLADI
tRDLRDH
tRDHRDL
RDN
tRDLDDV
tRDLDLZ
tRDHDDF
D0–D7
tRDLRYL
tRYZDDV
tRDHDDI
RDYN
A
NOTE:
A Wait on Rx. Receiver FIFO empty.
SD00240
Figure 4. Read Cycle12
SYMBOL
LIMITS
PARAMETER
UNIT
Min
Max
5
–
ns
tADVRDL
Address valid to RDN LOW
tCELRDL
CEN LOW to RDN LOW
0
–
ns
tRDLADI
RDN LOW to address invalid
50
–
ns
tRDLRYL
RDN LOW to RDYN LOW
–
150
ns
tRDLDDV
RDN LOW to read data valid
tRDLRDH
RDN LOW to RDN HIGH
valid9
–
130
ns
130
–
ns
tRYZDDV
RDYN high-impedance to read data
–
90
ns
tRDHCEH
RDN HIGH to CEN HIGH
0
–
ns
tCEHCEL
CEN HIGH to CEN LOW
30
–
ns
tRDHDDI
RDN HIGH to read data invalid
5
–
ns
tRDHRDL
RDN HIGH to RDN LOW
30
–
ns
tRDHDDF
RDN HIGH to data bus floating
–
40
ns
tRDLDLZ
RDN LOW to data bus low-impedance9
10
–
ns
2006 Aug 10
9
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
A6–A1
tADVWRL
tCEHCEL
tWRHCEH
CSN (CEN)
tCELWRL
tWRLADI
tWRLWRH
tWRHWRL
WRN
tWDVWRH
tWRHWDI
D0–D7
tWRLRYL
RDYN
A
tRYHZWRH
NOTE:
A Wait on Tx. Transmitter FIFO full.
SD00241
Figure 5. Write
SYMBOL
Cycle12
LIMITS
PARAMETER
Min
Max
UNIT
tADVWRL
Address valid to WRN LOW
5
–
ns
tCELWRL
CSN LOW to WRN LOW
0
–
ns
tWRLRYL
WRN LOW to RDYN LOW
–
–
ns
tWRHCEH
WRN HIGH to CSN HIGH
0
–
ns
tWRLWRH
WRN LOW to WRN HIGH
100
–
ns
tWDVWRH
Write data valid to WRN HIGH
60
–
ns
tCEHCEL
CEN HIGH to CEN LOW
30
150
ns
tWRLADI
WRN LOW to address invalid
50
–
ns
tWRHWRL
WRN HIGH to WRN LOW
30
–
ns
tWRHWDI
WRN HIGH to write data invalid
5
–
ns
tRYHZWRH
RDYN high-impedance to WRN HIGH9
0
–
ns
2006 Aug 10
10
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
SERVICE
ROUTINE
A
INTERRUPT REQUEST LOCKED
IRQN
Cleared
through
software
VECTOR SETTLING
IACKN
A
VECTOR
LOCKED
tIALDDV
A
C
D7–D0
C
B
tIAHDDI
tIAHDDF
NOTES:
A ICR[5:4] = 01 or 10 (mode 1 or mode 2)
B Call instruction (mode 2)
C ICR[5:4] = 11 (mode 3)
SD00208
Figure 6. Interrupt Acknowledge Cycle
SYMBOL
tIALDDV
tIAHDDF
tIAHDDI
tIALDLZ
tIAHIAL
LIMITS
PARAMETER
Min
IACKN LOW to data bus valid
IACKN HIGH to data bus floating
IACKN HIGH to data bus invalid
IACKN LOW to data bus LOW impedance9
IACKN HIGH to LOW
Max
130
60
5
10
30
UNIT
ns
ns
ns
ns
ns
CEN
WRN
tWRHGOV
GPO1_N
AND/OR
GPO2_N
OLD DATA
NEW DATA
SD00209
Figure 7. Output Port Timing
SYMBOL
tWRHGOV
2006 Aug 10
LIMITS
PARAMETER
WRN HIGH to GPO output data valid
11
Min
Max
–
100
UNIT
ns
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
CSN (CEN)
RDN
tGIVRDL
tRDLGII
GPI1N
AND/OR
GPI2N
SD00242
Figure 8. Input Port Timing
SYMBOL
tGIVRDL
tRDLGII
LIMITS
PARAMETER
Min
Max
20
40
–
–
GPI input valid to RDN LOW
RDN LOW to GPI input invalid
*Pull-up resistor is not required when using CMOS levels
TTL
UNIT
ns
ns
DRIVING
FROM EXTERNAL
SOURCE
VCC
470Ω
*
X1
X2 OPEN WHEN
X1 IS DRIVEN
X2
÷2
CL1
tCLHCLL
tCCHCCL
tRCHRCL
tTCHTCL
X1/CLK
CTCLK
RxC
TxC
X1
CP1
TO
CDUSCC
CIRCUITS
50-150kΩ
CL2
X2
CP2
CP1 = 7-12pF
SC26C562
CP2 = 12-17pF
tCLLCLH
tCCLCCH
tRCLRCH
tTCLTCH
NOTE: CL1 AND CL2 VALUES DEPEND ON
CRYSTAL
MANUFACTURER’S REQUIREMENTS, AND SHOULD
INCLUDE CP1 AND CP2
SD00243
Figure 9. Clock Timing
SYMBOL
tCLHCLL
tCLLCLH
tCCHCCL
tCCLCCH
tRCHRCL
tRCLRCH
tTCHTCL
tTCLTCH
fCL
fCC
fRC
fTC
fRTC
2006 Aug 10
LIMITS
PARAMETER
X1/CLK HIGH to LOW time
X1/CLK LOW to HIGH time
C/T CLK HIGH to LOW time
C/T CLK LOW to HIGH time
RxC HIGH to LOW time
RxC LOW to HIGH time
TxC HIGH to LOW time
TxC LOW to HIGH time
X1/CLK frequency11
C/T CLK frequency
RxC frequency (16X or 1X @ 50% duty cycle)
TxC frequency (16X or 1X @ 50% duty cycle)
Tx/Rx frequency for FM/Manchester encoding
12
Min
Typ
Max
25
25
45
45
50
50
50
50
0
0
0
0
–
–
–
–
–
–
–
–
–
14.7456
–
–
–
–
–
–
–
–
–
–
–
–
16.0
10
10
10
5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
1 BIT TIME
(1 OR 16 CLOCKS)
TxC
(INPUT)
TxC
(INPUT)
tCILTXV
tCILTXV
tCILTXV
TxD
TxD
tCOLTXV
tCOLTXV
TxC
(1X OUTPUT)
TxC
(1X OUTPUT)
a. Transmit Timing NRZ
tCOLTXV
b. Transmit Timing FM0/1, Manchester Encoding
SD00244
Figure 10.
SYMBOL
LIMITS
PARAMETER
Min
Max
UNIT
tCILTXV
TxC input LOW (1X) to TxD output
TxC input LOW (16X) to TxD output
–
–
120
120
ns
ns
tCOLTXV*
TxC output LOW to TxD output9 (NRZ, NRZI)
FM, MAN
–
–
20
30
ns
ns
*Characterized with no loads on TxD and TxC outputs. Tester load is approximately 50 pF.
tRCHSOL
RXC
(INPUT)
SYNOUTN
tSILRCH
tRCHRXI
tRXVRCH
tRXVRCH
tRCHSIH
SYNIN
RxD
RXC (1X)
INPUT
tRXVRCH
tRCHRXI
tRCHRXI
RxD
a. Receive Timing NRZ
b. Receive Timing FM0/1, Manchester Encoding
SD00245
Figure 11.
SYMBOL
LIMITS
PARAMETER
UNIT
Min
Max
RxD data valid to RxC HIGH:
For NRZ data
For NRZI, Manchester, FM0, FM1 data
20
30
–
–
ns
ns
RxC HIGH to RxD data invalid:
For NRZ data
For NRZI, Manchester, FM0, FM1 data
20
30
–
–
ns
ns
tSILRCH
SYNIN LOW to RxC HIGH
50
–
ns
tRCHSIH
RxC HIGH to SYNIN HIGH
20
–
ns
tRCHSOL
RxC HIGH to SYNOUT LOW
–
100
ns
tRXVRCH
tRCHRXI
2006 Aug 10
13
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
tWRHEOZ
EOPN
(OUTPUT)
tWRLEOL
RTxDRQN OR
TxDRQN
CSN (CEN)
tWRLTRH
A
WRN
D7–D0
tEILWRH
tWRHEIH
EOPN
(INPUT)
A
The TxFIFO is addressed during this write cycle.
SD00246
Figure 12. Transmit Dual Address DMA Timing
SYMBOL
tWRLTRH
tWRLEOL
tWRHEOZ
tEILWRH
tWRHEIH
2006 Aug 10
LIMITS
PARAMETER
WRN LOW to Tx DMA REQN HIGH
WRN LOW to EOPN output LOW
WRN HIGH to EOPN output high-impedance
EOPN input LOW to WRN HIGH
WRN HIGH to EOPN input HIGH
14
Min
Max
–
–
–
30
25
100
100
60
–
–
UNIT
ns
ns
ns
ns
ns
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
RTxDRQN
tRDLRRH
CEN
A
RDN
D7–D0
tRDLEOL
tRDHEOZ
EOPN
(OUTPUT)
A
The RxFIFO is addressed during this read cycle.
SD00247
Figure 13. Receive Dual Address DMA Timing
SYMBOL
tRDLRRH
tRDLEOL
tRDHEOZ
2006 Aug 10
LIMITS
PARAMETER
RDN LOW to Rx DMA REQN HIGH
RDN LOW to EOPN output LOW
RDN HIGH to EOPN output high-impedance
15
Min
Max
–
–
–
100
100
60
UNIT
ns
ns
ns
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
TxRQN
tTAHTAL
tTALTRH
TxDAKN
tTALTAH
WRN
A
A
B
B
MEMRN
tTAHEIH
tEILTAH
EOPN
(INPUT)
tWDVTAH
tTAHWDI
D7–D0
tTAHEOF
tTALEOL
EOPN
(OUTPUT)
NOTES:
A Ignored by the CDUSCC since CEN is not asserted, but it can be used externally to qualify TxDAKN.
B Memory read signal; not seen by CDUSCC.
SD00248
Figure 14. DMA-Transmit Single Address Mode
SYMBOL
tTAHTAL
tTALTAH
tTALTRH
tWDVTAH
tTAHWDI
tTALEOL
tTAHEOF
tEILTAH
tTAHEIH
2006 Aug 10
LIMITS
PARAMETER
Transmit DMA ACKN HIGH to LOW time
Transmit DMA ACKN LOW to HIGH time
Tx DMA ACKN LOW to Tx DMA REQN HIGH
Write data valid to Tx DMA ACKN HIGH
Tx DMA ACKN HIGH to write data invalid
Tx DMA ACKN LOW to EOPN output LOW
Tx DMA ACKN HIGH to EOPN output float
EOPN input LOW to Tx DMA ACKN HIGH
Tx DMA ACKN HIGH to EOPN input HIGH
16
Min
Max
30
100
–
40
10
–
–
30
25
–
–
100
–
–
80
60
–
–
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
RxDRQN
tRAHRAL
tRALRRH
RxDAKN
tRALRAH
RDN
A
A
MEMWN
B
B
tRAHEOF
tRALEOL
EOPN
(OUTPUT)
tRALDDV
tRAHDDI
D7–D0
tRAHDDF
NOTES:
A Ignored by the CDUSCC bit; it can be used to qualify RxDAKN.
B Memory read signal; not seen by CDUSCC.
SD00249
Figure 15. DMA-Receive Single Address Mode
LIMITS
SYMBOL
tRAHRAL
tRALRAH
tRALRRH
tRALEOL
tRAHEOF
tRALDDV
tRAHDDI
tRAHDDF
2006 Aug 10
Receive DMA ACKN HIGH to LOW time
Receive DMA ACKN LOW to HIGH time
Rx DMA ACKN LOW to Rx DMA REQN HIGH
Rx DMA ACKN LOW to EOPN output LOW
Rx DMA ACKN HIGH to EOPN output float
Rx DMA ACKN LOW to read data valid
Rx DMA ACKN HIGH to read data invalid
Rx DMA ACKN HIGH to data bus float
17
Min
Max
30
130
–
–
–
–
5
–
–
–
100
100
60
130
–
60
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
VM
RDN/WRN
tRWHIRH
VOL +0.2V
IRQN
VOL
SD00218
Figure 16. Interrupt Timing
SYMBOL
tRWHIRH
LIMITS
PARAMETER
RDN/WRN HIGH to IRQN HIGH for:
Read RxFIFO (RxRDY interrupt)
Write TxFIFO (TxRDY interrupt)
Write RSR (Rx condition interrupt)
Write TRSR (Rx/Tx interrupt)
Write ICTSR (counter/timer interrupt)
Write TRMSR (Tx Path, Patt. Det.)
Min
Max
–
–
–
–
–
–
90
90
90
90
90
90
UNIT
ns
ns
ns
ns
ns
ns
X1/CLK
WRN
COMMAND
VALID
SD00219
Figure 17. Command Timing
RxC
1
2
3
4
5
6
7
8
3
4
5
6
7
8
RxD
LCN
a. Loop Control Output Assertion
RxC
1
2
9
RxD
LCN
b. Loop Control Output Negation
SD00220
Figure 18. Relationship Between Received Data and the Loop Control Output
2006 Aug 10
18
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
50
SC26C562
50
0 °C
40
40
25 °C
30
30
ICC
ICC
70 °C
20
20
10
10
0
0
4
4.5
5
5.5
6
4
VCC
6
8
10
Tx/Rx Clk and X1 Frequency
Test Condition: VCC = 5 V at 25 °C
Test Condition: Tx/Rx and X1 Frequency @ 10 MHz
SD00250
Figure 19.
2.7 kΩ
TRxC
IRQN
VDD
RTxC
50 pF
50 pF
820 Ω
RDYN
+5.0 V
150 pF
1 kΩ
EOPN
VDD
50 pF
710 Ω
ALL OTHER
OUTPUTS
+5.0 V
150 pF
NOTE:
All CL includes 50 pF stray capacitance,
i.e., CL = 150 pF = 100 pF discrete +50 pF stray.
SD00251
Figure 20. Test Conditions for Outputs
2006 Aug 10
19
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
PLCC52: plastic leaded chip carrier; 52 leads
2006 Aug 10
SC26C562
SOT238-2
20
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
REVISION HISTORY
Rev
Date
Description
_4
20060810
Product data sheet (9397 750 14948). Supersedes data of 2004 Mar 29 (9397 750 13072).
Modifications:
• Ordering information: changed Version for PLCC52 from SOT238–3 to SOT238–2
• Changed package outline drawing from SOT238–3 to SOT238–2.
_3
20040329
Product data (9397 750 13072). Supersedes Product specification of 1998 Sep 04 (9397 750 04355).
_2
19980904
Product specification (9397 750 04355). ECN 853-1663 19973 of 04 September 1998.
Supersedes data of 1995 May 01.
_1
19950501
2006 Aug 10
21
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
Legal Information
Data sheet status
Document status [1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this data sheet was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.semiconductors.philips.com.
environmental damage. Philips Semiconductors accepts no liability for
inclusion and/or use of Philips Semiconductors products in such equipment
or applications and therefore such inclusion and/or use is at the customer’s
own risk.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Philips Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Philips Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local Philips
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause
permanent damage to the device. Limiting values are stress ratings only and
operation of the device at these or any other conditions above those given in
the Characteristics sections of this document is not implied. Exposure to
limiting values for extended periods may affect device reliability.
Terms and conditions of sale — Philips Semiconductors products are
sold subject to the general terms and conditions of commercial sale, as
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Right to make changes — Philips Semiconductors reserves the right to
make changes to information published in this document, including without
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malfunction of a Philips Semiconductors product can reasonably be
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Please be aware that important notices concerning this document and the product(s)
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 Koninklijke Philips Electronics N.V. 2006.
All rights reserved.
For more information, please visit http://www.semiconductors.philips.com.
For sales office addresses, email to: [email protected].
Date of release: 20060810
Document identifier: SC26C562_4
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