INTEGRATED CIRCUITS 74ALVCHS16830 18-bit to 36-bit address driver with bus hold (3-State) Product data Supersedes data of 2001 Sep 07 2002 Mar 15 Philips Semiconductors Product data 18-bit to 36-bit address driver with bus hold (3-State) FEATURES 74ALVCHS16830 PIN CONFIGURATION • Diodes on inputs clamp overshoot • ESD classification testing is done to JEDEC Standard JESD22. TOP VIEW Protection exceeds 2000 V HBM per method A114. • Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA. • Bus hold on data inputs eliminates the need for external pullup/pulldown resistors • Packaged in thin very small-outline package (TVSOP) — 0.4 mm pitch • Optimized for use with PCK953 in SDRAM module applications • Low noise, low skew 2Y2 1 80 1Y3 1Y2 2 79 2Y3 GND 3 78 GND 2Y1 4 77 1Y4 1Y1 5 76 2Y4 VCC 6 75 VCC A1 7 74 1Y5 A2 8 73 2Y5 GND 9 72 GND A3 10 71 1Y6 A4 11 70 2Y6 GND 12 DESCRIPTION The ALVCHS16830 address driver is designed for 2.3 V to 3.6 V VCC operation. Diodes to VCC have been added on the inputs to clamp overshoot. The bus hold feature retains the inputs’ last state whenever the input bus goes to high impedance. This prevents floating inputs and eliminates the need for pull up or pull down resistors. The 74ALVCHS16830 is characterized for operation from –40 to +85 °C. FUNCTION TABLE Inputs 68 1Y7 A6 14 67 2Y7 VCC 15 66 VCC A7 16 65 1Y8 A8 17 64 2Y8 GND 18 To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Outputs 69 GND A5 13 63 GND A9 19 62 1Y9 OE1 20 61 2Y9 OE2 21 60 1Y10 A10 22 59 2Y10 GND 23 58 GND A11 24 57 1Y11 A12 25 56 2Y11 VCC 26 55 VCC A13 27 54 1Y12 OE1 OE2 A 1Yn 2Yn L H H H Z A14 28 53 2Y12 L H L L Z GND 29 52 GND A15 30 51 1Y13 H L H Z H H L L Z L A16 31 50 2Y13 49 GND L L H H H GND 32 L L L L L A17 33 48 1Y14 Z A18 34 47 2Y14 H H X Z VCC 35 46 VCC 2Y18 36 45 1Y15 1Y18 37 44 2Y15 GND 38 43 GND 2Y17 39 42 1Y16 1Y17 40 41 2Y16 SW00723 ORDERING INFORMATION PACKAGES 80-pin plastic thin very small outline (TVSOP) 2002 Mar 15 TEMPERATURE RANGE ORDER CODE DWG NUMBER –40 to +85 °C 74ALVCHS16830DGB SOT647-1 2 853-2280 27859 Philips Semiconductors Product data 18-bit to 36-bit address driver with bus hold (3-State) LOGIC DIAGRAM (POSITIVE LOGIC) PIN DESCRIPTION PIN(S) VCC OE2 21 VCC OE1 20 VCC 5 1Y1 A1 74ALVCHS16830 7 4 2Y1 SYMBOL FUNCTION 6, 15, 26, 35, 46, 55, 66, 75 VCC Supply voltage 7, 8, 10, 11, 13, 14, 16, 17, 19, 22, 24, 25, 27, 28, 30, 31, 33, 34 An Inputs 1, 2, 4, 5, 36, 37, 39, 40, 41, 42, 44, 45, 47, 48, 50, 51, 53, 54, 56, 57, 59, 60, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80 1Yn, 2Yn Outputs 20, 21 OE1, OE2 Output enable 3, 9, 12, 18, 23, 29, 32, 38, 43, 49, 52, 58, 63, 69, 72, 78 GND Ground to 17 other channels SW00724 ABSOLUTE MAXIMUM RATINGS Over recommended operating free-air temperature range (unless otherwise noted).1 SYMBOL VCC PARAMETER CONDITIONS Supply voltage range RATING UNIT –0.5 to +4.6 V VI Input voltage range See Note 2 VO Output voltage range See Notes 2 and 3 IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 IO Continuous output current Continuous current through each VCC or GND "100 mA 106 °C/W –65 to +150 °C ICC, IGND ΘJA Package thermal impedance Tstg Storage temperature range See Note 4 –0.5 to +4.6 V –0.5 to VCC +0.5 V –50 mA –50 mA "50 mA NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 3. This value is limited to 4.6 V maximum. 4. The package thermal impedance is calculated in accordance with JESD 51. 2002 Mar 15 3 Philips Semiconductors Product data 18-bit to 36-bit address driver with bus hold (3-State) 74ALVCHS16830 RECOMMENDED OPERATING CONDITIONS All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. LIMITS SYMBOL VCC PARAMETER Supply voltage VIH High level input voltage High-level VIL Low level input voltage Low-level VI Input voltage VO Output voltage IOH IOL CONDITIONS UNIT MIN MAX 2.3 3.6 VCC = 2.3 V to 2.7 V 1.7 — VCC = 2.7 V to 3.6 V 2 — VCC = 2.3 V to 2.7 V — 0.7 VCC = 2.7 V to 3.6 V — 0.8 0 VCC V V High-level output current Low-level output current V V V 0 VCC VCC = 2.3 V — –12 VCC = 2.7 V — –12 VCC = 3 V — –24 VCC = 2.3 V — 12 VCC = 2.7 V — 12 VCC = 3 V mA mA — 24 ∆t/∆v Input transition rise or fall rate — 10 ns/V Tamb Operating free-air temperature –40 +85 °C 2002 Mar 15 4 Philips Semiconductors Product data 18-bit to 36-bit address driver with bus hold (3-State) 74ALVCHS16830 ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range (unless otherwise noted). LIMITS SYMBOL VCC MIN TYP1 MAX II = –18 mA 2.3 V — — –1.2 II = 18 mA 2.3 V — — VCC+1.2 2.3 V to 3.6 V VCC–0.2 — — IOH = –4 mA, VIH = 1.7 V 2.3 V 1.9 — — IOH = –6 mA, VIH = 1.7 V 2.3 V 1.7 — — IOH = –8 mA, VIH = 2 V 2.7 V 2.4 — — IOH = –12 mA, VIH = 2 V 3V 2 — — IOH = –24 mA, VIH = 2 V 3V 2 — — 2.3 V to 3.6 V — — 0.2 IOL = 4 mA, VIL = 0.7 V 2.3 V — — 0.4 IOL = 6 mA, VIL = 0.7 V 2.3 V — — 0.55 IOL = 8 mA, VIL = 0.8 V 2.7 V — — 0.55 IOL = 12 mA, VIL = 0.8 V 3V — — 0.6 IOL = 24 mA, VIL = 0.8 V 3V — — 0.8 PARAMETER VIK TEST CONDITIONS V IOH = –100 µA VOH II II(hold) V V V V VI = VCC or GND 3.6 V — — ±5 VI = 0.7 V 2.3 V 45 — — VI = 1.7 V 2.3 V –45 — — VI = 0.8 V 3V 75 — — 3V –75 — — 3.6 V — — ±500 VI = 2 V VI = 0 to 3.8 V V IOL = 100 µA VOL UNIT V2 µA µA IOZ VO = VCC or GND 3.6 V — — ±10 µA ICC VI = VCC or GND, IO = 0 3.6 V — — 40 µA One input at VCC – 0.8 V, Other inputs at VCC or GND 3 V to 3.6 V — — 750 µA — 3.62 — VI = VCC or GND 33V 3.3 — 8.21 — VO = VCC or GND 3.3 V — 3.53 — ∆ICC Control inputs Ci Co Data inputs Outputs pF pF NOTES: 1. All typical values are at VCC = 3.3 V, Tamb = 25 °C. 2. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. 2002 Mar 15 5 Philips Semiconductors Product data 18-bit to 36-bit address driver with bus hold (3-State) 74ALVCHS16830 SWITCHING CHARACTERISTICS Over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 and 2). PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 2.5 V ± 0.2 V VCC = 2.7 V VCC = 3.3 V ± 0.3 V UNIT MIN MAX MIN MAX MIN MAX 1.7 3.5 ns tpd A Y 1.2 3.8 — 4 ten OE Y 1 5.7 — 5.7 1 4.8 ns tdis OE Y 1 4.9 — 5.4 1.7 5.2 ns Output skew — — — — — — 500 ps tsk(o)1 NOTE: 1. Output skew between any 2 outputs of same part switching in the same direction. OPERATING CHARACTERISTICS, Tamb = 25 °C SYMBOL Cpd 2002 Mar 15 PARAMETER Power dissipation capacitance per driver TEST CONDITIONS All outputs enabled All outputs disabled CL = 0, 0 f = 10 MHz 6 VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V TYP TYP 49 53 6 7.5 UNIT pF Philips Semiconductors Product data 18-bit to 36-bit address driver with bus hold (3-State) 74ALVCHS16830 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V S1 500 Ω From Output Under Test 2 × VCC TEST Open S1 GND CL = 30 pF (see Note A) tpd Open tPLZ/tPZL 2 × VCC 500 Ω tPHZ/tPZH GND Load Circuit VCC Timing Input tw VCC/2 VCC 0V Input tsu VCC/2 0V th Voltage Waveforms Pulse Duration VCC Data Input VCC/2 VCC/2 VCC/2 0V Voltage Waveforms Setup and Hold Times Output Control (low-level enabling) VCC/2 VCC/2 tPLZ Output Waveform 1 S1 at 2 x VCC (see Note B) 0V tPLH 0V tPZL VCC Input VCC VCC/2 VCC/2 tPHL VCC VCC/2 tPZH VOL + 0.15 V VOL tPHZ VOH Output VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 VOH VOH – 0.15 V 0V Voltage Waveforms Enable and Disable Times SV01849 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load circuit and voltage waveforms 2002 Mar 15 7 Philips Semiconductors Product data 18-bit to 36-bit address driver with bus hold (3-State) 74ALVCHS16830 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V and 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open TEST S1 tpd tPLZ/tPZL Open 6V tPHZ/tPZH GND GND CL = 50 pF (see Note A) 500 Ω Load Circuit 2.7 V Timing Input tw 1.5 V 2.7 V 0V Input tsu 1.5 V 0V th Voltage Waveforms Pulse Duration 2.7 V Data Input 1.5 V 1.5 V 1.5 V 0V Voltage Waveforms Setup and Hold Times Output Control (low-level enabling) 1.5 V 1.5 V tPLZ Output Waveform 1 S1 at 6 V (see Note B) 0V tPLH 0V tPZL 2.7 V Input 2.7 V 1.5 V 1.5 V tPHL 3V 1.5 V tPZH VOL + 0.3 V tPHZ VOL VOH Output 1.5 V Output Waveform 2 S1 at GND (see Note B) 1.5 V VOL Voltage Waveforms Propagation Delay Times 1.5 V VOH VOH – 0.3 V 0V Voltage Waveforms Enable and Disable Times SV01850 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load circuit and voltage waveforms 2002 Mar 15 8 Philips Semiconductors Product data 18-bit to 36-bit address driver with bus hold (3-State) 74ALVCHS16830 TSSOP80: plastic thin shrink small outline package; 80 leads; body width 6.1 mm 2002 Mar 15 9 SOT647-1 Philips Semiconductors Product data 18-bit to 36-bit address driver with bus hold (3-State) 74ALVCHS16830 Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 03-02 For sales offices addresses send e-mail to: [email protected]. Document order number: 2002 Mar 15 10 9397 750 09605