July 7, 2009 IRS2552D CCFL/EEFL BALLAST CONTROLLER IC Features • • • • • • • • • • • • • • • • Product Summary Drives up to two IGBT/MOSFET power devices Integrated programmable oscillator Soft start function 15.6 V voltage clamp on VCC Micro-power startup 0 V to 5 V input analog dimming Programmable ignition frequency Programmable ignition time Lamp current control Programmable deadtime Supports multi-lamp operation Burst dimming with soft start at every burst Latched open circuit protection Integrated bootstrap functionality Excellent latch immunity on all inputs & outputs Integrated ESD protection on all pins Topology Half-Bridge VOFFSET 600 V VOUT VCC IO+ & IO- (typical) 300 mA & 450 mA Deadtime (programmable) 500ns ~ 2µs Package Options Typical Application • CCFL/EEFL inverter 16-Lead PDIP 16-Lead SOIC (Narrow Body) Typical Application Diagram www.irf.com © 2009 International Rectifier 23 IRS2552D Table of Contents Page Typical Application Diagram 1 Qualification Information 4 Absolute Maximum Ratings 5 Recommended Operating Conditions 6 Electrical Characteristics 7 Functional Block Diagram 10 Lead Definitions 12 Lead Assignments 13 State Diagram 14 Application Information and Additional Details 15 Package Details 29 Part Marking Information 30 Ordering Information 32 www.irf.com © 2009 International Rectifier 2 IRS2552D Description The IRS2552D incorporates a high voltage half-bridge gate driver with a front end that incorporates full control functionality for CCFL/EEFL ballasts. Includes a programmable ignition and supports dimming via analog or PWM control voltage. HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. Noise immunity is achieved with low di/dt peak of the gate drivers, and with an undervoltage lockout hysteresis of approximately 1 V. The IRS2552D also includes protection features for over-current and over-voltage of the lamps. www.irf.com © 2009 International Rectifier 3 IRS2552D Qualification Information† Qualification Level Moisture Sensitivity Level Machine Model ESD Human Body Model IC Latch-Up Test RoHS Compliant Industrial†† (per JEDEC JESD 47E) Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. MSL3††† SOIC16 (per IPC/JEDEC J-STD-020C) Not applicable PDIP16 (non-surface mount package style) Class C (per JEDEC standard EIA/JESD22-A115-A) Class 3A (per EIA/JEDEC standard JESD22-A114-B) Class I, Level A (per JESD78A) Yes † †† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. www.irf.com © 2009 International Rectifier 4 IRS2552D Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VH VL VCO VCT VDT MIN DIM CR CD SD CS ICC dVS/dt PD RΘJA TJ TS TL † Definition High-side floating supply voltage High-side floating supply offset voltage High-side floating output voltage Low-side output voltage VCO pin voltage CT pin voltage DT pin voltage MIN pin voltage DIM pin voltage CR pin voltage CD pin voltage SD pin voltage CS pin voltage † Supply current Allowable offset voltage slew rate Package power dissipation @ TA ≤ +25 ºC 16L-PDIP 16L-SOIC 16L-PDIP 16L-SOIC Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) Min. -0.3 VB - 25 VS – 0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 ---50 ---------55 -55 --- Max. 625 VB + 0.3 VB + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 25 50 1.3 1.4 70 82 150 150 300 Units V mA V/ns W ºC/W ºC This IC contains a voltage clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6 V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section. www.irf.com © 2009 International Rectifier 5 IRS2552D Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Symbol VBS VS VCC ICC TJ † †† Definition High-side floating supply voltage Steady-state high-side floating supply offset voltage Supply voltage Supply current Junction temperature Min. VCC – 0.7 † -3.0 VCCUV+ +0.1V †† -40 Max. VCLAMP 600 VCLAMP 10 125 Units V mA ºC Care should be taken to avoid output switching conditions where the VS node flies inductively below ground by more than 5 V. Enough current should be supplied to the VCC pin of the IC to keep the internal 15.6 V zener diode clamping the voltage at this pin. Recommended Component Values Symbol RMIN RMAX RDT CT CDT CR CD Component MIN pin resistor value MAX pin resistor value DT pin resistor value CT pin capacitor value DT pin capacitor value CR pin capacitor value CD pin capacitor value Min. 5 5 22 330 47 1 1 www.irf.com Max. Units --- kΩ --- pF --- nF © 2009 International Rectifier 6 IRS2552D Electrical Characteristics VBIAS (VCC, VBS) = 14 V, CT = 1 nF and TA = 25 °C unless otherwise specified. The input parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol Definition Low Voltage Supply Characteristics Min Typ Max VCCUV+ Rising VCC undervoltage lockout threshold 9.5 10.5 11.5 VCCUV- Falling VCC undervoltage lockout threshold 8.5 9.5 10.5 VCC undervoltage lockout hysteresis 0.5 1 1.5 Micropower startup VCC supply current --- 300 350 Quiescent VCC supply current --- 4.0 4.5 IQCCFLT VCC supply current --- 0.9 1.3 ICC,FMIN VCC current @ fosc = fMIN --- 4.7 5.3 VCLAMP VCC clamp voltage 14.6 15.6 16.6 Micropower startup VBS supply current --- 6 20 VBS supply current --- 1000 1200 VBSUV+ VBS supply undervoltage positive going threshold 6.5 7.5 8.5 VBSUV- VBS supply undervoltage negative going threshold 6.0 7.0 8.0 Offset supply leakage current --- --- 50 VCCUVHYS IQCCUV IQCC Units Test Conditions V N/A µA VCC = VCCUV+ -100 mV rising RMIN = 12 kΩ, RUN MODE CT = 0 V mA Fault mode RMIN = 12 kΩ, RUN MODE V ICC = 19 mA Floating Supply Characteristics IQBSUV IBS ILK VCC ≤ VCCUV-, µA VCC = VBS HO oscillating V N/A μA VB = VS = 600 V Oscillator I/O Characteristics fMIN Minimum oscillator frequency 36.5 39 42.5 fMAX Maximum oscillator frequency 67 69 71 VCT+ Upper CT ramp voltage threshold 4.8 5.0 5.2 VCT- Lower CT ramp voltage threshold --- 0 --- CT pin source current 350 410 470 VMIN VMIN pin voltage 4.8 5.0 5.2 VMAX VMAX pin voltage 4.8 5.0 5.2 VMIN,FLT VMIN voltage in fault mode --- 0 --- VMAX,FLT VMAX voltage in fault mode --- 0 --- kHz ICT www.irf.com RMIN = 12 kΩ, RUN MODE RMAX = 6.8 kΩ, IGNITION MODE V N/A μA RMIN =12 kΩ, RUN MODE V N/A © 2009 International Rectifier 7 IRS2552D Electrical Characteristics VBIAS (VCC, VBS) = 14 V, CT = 1 nF and TA = 25 °C unless otherwise specified. The input parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol Ignition Definition Min Typ Max Units Test Conditions ICR,IGN Source current at CR pin in IGN mode 3.7 4.5 5.3 μA RMIN = 12 kΩ, IGNITION MODE VCS,IGN Ignition detection threshold 0.57 0.6 0.63 V N/A V Gate Driver Output Characteristics VOH High-level output voltage, VBIAS – VO --- VCC --- VOL Low-level output voltage, VO --- COM --- VOL,UV UV-mode output voltage, VO --- COM --- tR Output rise time --- 80 150 tF Output fall time --- 45 100 tD Output deadtime (HO or LO) 1.0 1.1 1.2 IO+ Output source current --- 300 --- IO- Output sink current --- 450 --- 13.2 13.5 mV IO = 0 A IO = 0 A, VCC ≤ VCCUV- ns μs N/A RDT = 2.2 kΩ, CDT = 1 nF mA N/A --- V N/A Bootstrap FET Characteristics VB,ON VB when the bootstrap FET is on IB,CAP VB source current when FET is on 40 55 --- mA CBS = 0.1 μF IB,10V VB source current when FET is on 9 12 --- mA VB = 10 V Shutdown threshold at SD pin 1.9 2.0 2.1 V N/A CD pin source current 3.7 4.5 5.3 μA Threshold at which CD triggers shutdown 4.8 5.0 5.2 V Shutdown VSD,TH ICD,source VCD,TH www.irf.com VSD>VSD,TH, RMIN = 12 kΩ VCC = 14 V © 2009 International Rectifier 8 IRS2552D Electrical Characteristics VBIAS (VCC, VBS) = 14 V, CT = 1 nF and TA = 25 °C unless otherwise specified. The input parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol Definition Min Typ Max Units Test Conditions Over-Current Compensation VCS,TH Current compensation threshold at CS pin 1.15 1.21 1.27 V ICD,OC Source current at CD pin when the IC is in current compensation mode 3.7 4.5 5.3 μA VCD,oc Voltage on CD where duty cycle reaches minimum 4.8 5.0 5.2 V DCMIN Minimum HO duty cycle --- 10% --- --- VCR+ CR pin upper threshold voltage 4.8 5.0 5.2 VCR- CR pin lower threshold voltage --- 0.2 --- 125 150 175 N/A VCS>VCS,TH, RMIN = 12 kΩ N/A VCD = 4.7 V, RUN MODE Dimming ICR,RUN Source current at CR pin in RUN mode V N/A μA RMIN = 12 kΩ CR = 100 nF, fCR Frequency at CR pin 240 310 370 Hz RUN MODE, RMIN = 12 kΩ Soft Start DCMIN Minimum HO duty cycle --- 10% --- --- VCR,SS End of soft start voltage 0.88 0.96 1.04 VDIM,SS Soft start disable threshold --- 4.8 --- VENATH Enable threshold 1.9 2.2 2.5 V VENAHYS Enable hysteresis --- 200 --- mV V VCR = 0 V, VDIM < VDIM,SS VDIM < VDIM,SS N/A Enable www.irf.com N/A © 2009 International Rectifier 9 IRS2552D Functional Block Diagram IMIN ICD ICR_IGN 12 ICR_RUN CS 0.6V 5V 1.21V MIN 5 IGNITION LOGIC IMAX 5V MAX 6 OVER CURRENT CONTROL BAND GAP REF 5V SOFT START CONTROL CT 3 VBG S 5V 0V Q R1 DEAD TIME CONTROL EN R2 Q DUTY CYCLE CONTROL DT 4 CD 10 LEVEL SHIFT 5V SD 11 2V CR 9 DIM 7 Q S Q R PULSE FILTER & LATCH 16 VB 15 HO 14 VS BOOT STRAP DRIVE UV 1 5V UVLO UV OUTPUT LOGIC EN 13 VCC LO 15.6V 2 0.2V 8 COM ENA 2.2V www.irf.com © 2009 International Rectifier 10 IRS2552D Input/Output Pin Equivalent Circuit Diagrams: IRS2552D VB ESD Diode 25V HO VCC ESD Diode ESD Diode VS CT 600V ESD Diode VCC RESD RESD ESD Diode COM LO 25V ESD Diode COM VCC ESD Diode MIN, MAX RESD ESD Diode COM www.irf.com © 2009 International Rectifier 11 IRS2552D Lead Definitions Symbol VCC COM Description Logic and internal gate drive supply voltage IC power and signal ground CT Oscillator timing capacitor DT Independent dead time R and C MIN RFMIN sets running frequency MAX RFMAX sets ignition mode frequency DIM 0 to 5 V DC burst mode dimming control input ENA Chip Enable (2 V logic threshold) CR Burst dimming ramp CD Shutdown delay timing SD Open load detection CS Ignition detection (0.6 V threshold), over-current (1.2 V threshold) LO Low side output VS Half bridge HO High side output VB High side floating supply www.irf.com © 2009 International Rectifier 12 IRS2552D Lead Assignments VB 16 2 COM HO 15 3 CT 4 DT 5 MIN 6 MAX IRS2552D 1 VCC VS 14 LO 13 CS 12 SD 11 7 DIM CD 10 8 ENA CR www.irf.com 9 © 2009 International Rectifier 13 IRS2552D State Diagram† † All values are typical. Applies to application circuit on page 1. www.irf.com © 2009 International Rectifier 14 IRS2552D Application Information and Additional Details Information regarding the following topics is included as subsections within this section of the datasheet. • • • • • • • • • • • • IGBT/MOSFET Gate Drive Undervoltage Lockout Protection Oscillator Deadtime Ignition Run Mode Lamp Current Control Frequency, Current and Deadtime Calculation Dimming Function Soft Start PCB Layout Tips Additional Documentation IGBT/MOSFET Gate Drive The IRS2552D HVICs are designed to drive up to two MOSFET or IGBT power devices. Figures 1 and 2 illustrate several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the high-side power switch and VLO for the low-side power switch; this parameter is sometimes generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage. VB (or VCC) IO+ HO (or LO) + VHO (or VLO) VS (or COM) - Figure 1: HVIC sourcing current Figure 2: HVIC sinking current Undervoltage Lock-Out The IRS2552D includes an under voltage lockout circuit such that it remains in micro-power mode until the voltage at VCC pin exceeds the VCCUV+ threshold. When VCC exceeds the VCCUV+ threshold the IRS2552D oscillator starts up and gate drive signals appear at the LO and HO outputs, provided the ENABLE pin is connected to a voltage source above VENATH. The LO output will always go high first in order to pre-charge the bootstrap capacitor before the IRS2552D begins normal operation. www.irf.com © 2009 International Rectifier 15 IRS2552D Oscillator During UVLO and shutdown and the voltage at the MIN and MAX pins remain at 0 V. When VCC is raised above VCCUV+ the oscillator will start and LO and HO will produce output drive waveforms at frequency FMAX. The MAX pin sources 5 V and the resistance connected from this point to COM determines the CT charging current and consequently the frequency. RMIN is always connected from the MIN pin to COM, which sets the RUN mode frequency. In IGNITION mode the MAX pin supplies 5 V to RMAX, which is connected to COM setting a higher CT charging current and consequently a higher ignition frequency, as RMAX is smaller than RMIN. In RUN mode the MAX pin is no longer active and the voltage will drop to 0V. CT charges until the voltage reaches the 5 V threshold and then it is discharged rapidly to VCT-. It then begins to charge again, repeating this sequence and producing a saw tooth waveform. The MIN pin sources 5 V during IGNITION and RUN modes. The current flowing through FMIN to COM determines the charging current of CT during RUN mode and also serves as a current reference for the currents supplied from the CD and CR pins. VCC VCCUV+ CT VCT+ VCT- DT 1/3*VCC LO HO Figure 3: Oscillator waveforms Deadtime In the IRS2552D the dead time is determined by an independent external timing circuit comprising of RDT and CDT and is not affected by the values of CT, RMIN or RMAX. The DT pin voltage is held at COM when LO or HO is high. CDT is charged through RDT, which is connected to VCC, when DT is internally disconnected from COM at the start of the dead time. The dead time ends when CDT has charged to 1/3 VCC. This allows the dead time to remain consistent over the working range of VCC, i.e. from UVLO+ to the clamp voltage of 15.6 V. Ignition During the IGNITION phase the CR capacitor is charged through an internal current source ICR_IGN. When CR reaches VCR+ then if the voltage at CS is greater than VCSIGN, the IRS2552D will enter RUN mode. If the voltage at the CS pin is less than VCSIGN the IRS2552D will enter FAULT mode whereby LO and HO will both go low and the IRS2552D will shut down until VCC is reduced below VCCUV- and then increased above VCCU+. The ignition function is achieved by applying a frequency somewhat above resonance to the output step up transformer and resonant load. This should develop sufficient voltage across the lamps to allow partial ignition and some arc current to flow. The combined lamp current is fed back to the CS pin through a suitable isolating network to determine whether the lamps have ignited successfully. If a successful ignition is detected after the voltage at CR has reached VCR+ then RMAX is disconnected inside the IRS2552D and the frequency will switch immediately to www.irf.com © 2009 International Rectifier 16 IRS2552D to FMIN, therefore applying maximum power to the lamps. At this point the burst mode dimming function will be enabled. Run Mode In RUN mode an additional current source ICR_RUN is also switched into the circuit. This causes CR to ramp up to VCR+ much more rapidly than before. The CR pin is used to provide ignition timing as well as the burst mode dimming low frequency ramp. If the output is open circuit a very large voltage develops at the output. This is fed back to the SD pin through some suitable isolated sensing network such that the voltage at the SD pin will exceed VSDTH during an overvoltage condition. At this stage the capacitor CD begins to charge through a current source. When VSD > VSDTH the burst mode dimming function is disabled and the output will be continuous. If the voltage at SD drops below VSDTH the capacitor CD will be discharged to 0V again. If SD remains above VSDTH long enough for the CD capacitor voltage to reach VCDMAX or about 5 V then the IRS2552D will shut down and go into fault mode. Lamp Current Control Additionally the half bridge current is monitored at the CS pin so that during running if too much power is supplied to the lamps the IRS2552D is able to compensate by reducing the oscillator duty cycle while maintaining the same run frequency. This prevents the lamps from being over driven preventing premature end of life. When VCS > VCSTH the CD capacitor will begin to charge and the CD pin voltage will rise. As this occurs the duty cycle will begin to adjust, i.e. the HO on time will become gradually shorter and the LO on time will become gradually longer. The dead time will remain constant at all times. In this way the power to the output will be reduced while the frequency remains at fMIN. As the CD voltage rises, the duty cycle will be further reduced. If VCS then drops below VCSTH then the duty cycle will be regulated at that point and thus the current will be maintained at this limit. If VCS remains above VCSTH then the voltage will continue to rise on CD until it reaches VCDMAX, at which point the duty cycle reaches its minimum limit DCMIN and the IRS2552D will enter FAULT mode, requiring VCC to fall below UVLO- and then rise above UVLO+ in order to re-start. Frequency, Current, and Dead Time Calculation The running frequency of the IRS2552D is given by the following formula: f MIN = 1 2.09 ⋅ CT ⋅ RMIN where VMIN = 5 V, i.e. When the ignition ramp is complete and RMAX has no further effect on the oscillator. The ignition frequency given by: f MAX = 1 2.09 ⋅ CT ⋅ RMAX and the dead time is calculated by: t DT = RDT ⋅ C DT ⋅ ln(1.5) t DT = 0.405 ⋅ RDT ⋅ C DT www.irf.com © 2009 International Rectifier 17 IRS2552D Maximum duty cycle DCMAX = 0.5 − (t DT * f ) The ICR charging current during ignition mode and the ICD charging current are given by: ICRIGN = ICD = 0.06 RMIN 0.06 RMIN The ICR charging current and frequency during run mode are given by: ICRRUN = f CR = 1.8 RMIN 0.36 RMIN ⋅ CCR Dimming Function The IRS2552D supports burst mode dimming, meaning that the output drive to the lamps is pulsed on and off at a low frequency and the burst duty cycle is adjusted to control the average current and therefore the light output of the lamps. The IRS2552D contains a low frequency oscillator that generates a ramp waveform at the CR pin from 0 V to 5 V. The ramp frequency is dependent on the value of the external CR capacitor. A DC dimming control voltage is fed into the DIM pin which is compared with the dimming ramp by means of an internal comparator, which generates the PWM signal that is used internally to switch the outputs on and off. Thus when the DIM voltage is at 5 V the outputs will be on all of the time and when it is at 0 V the outputs will be off all of the time. Alternatively a PWM dimming control signal from 0 V to 5 V can be fed directly into the DIM pin to allow external PWM control independent of the dimming ramp. During the off period the LO and HO outputs are both low. www.irf.com © 2009 International Rectifier 18 IRS2552D 5V CR DIM 1V 0.2V Soft Start Soft Start Soft Start LO HO Duty cycle increases from 10% to 50% Figure 4: Dimming waveform RUN MODE ICCRUN charges CR up to VCR+. CR oscillates at fCR (sawtooth) Half-bridge oscillates at FMIN. VDC reset to 0V SOFT START ON OFF DC increases from DC min to DC max DC=DCmax DC=0 VDIM <VCRSS VCR<VCRSS VCRSS <VDIM<VDIMSS VCR<VCRSS VCR>VDIM VDIM>VDIMSS VCR<VDIM VCR>VDIM VCR<VDIM VCR>VDIM Soft start In addition the IRS2552D includes a soft start function that operates at the start of each burst, during dimming operation when VDIM < VDIMSS. The soft start will operate during the portion of the dimming ramp CR at the start of each burst from CR = 0 V to CR = VCRSS. When VCR = 0 the duty cycle will be at minimum (DCMIN) and will linearly increase to 50% (minus the dead time) when VCR reaches VCRSS. This function is enabled only in RUN mode and allows inrush currents to be eliminated during burst mode dimming, while always maintaining the frequency at FMIN. www.irf.com © 2009 International Rectifier 19 IRS2552D PCB Layout Tips Distance between high and low voltage components: It’s strongly recommended to place the components tied to the floating voltage pins (VB and VS) near the respective high voltage portions of the device. Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating side. Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 5). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collectorto-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect. Figure 5: Antenna Loops Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and VSS pins. A ceramic 1 μF ceramic capacitor is suitable for most applications. This component should be placed as close as possible to the pins in order to reduce parasitic elements. Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients as the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the VS pin and the switch node (see Figure 6), and in some cases using a clamping diode between VSS and VS (see Figure 7). See DT04-4 at www.irf.com for more detailed information. www.irf.com © 2009 International Rectifier 20 IRS2552D Figure 6: VS resistor Figure 7: VS clamping diode Additional Documentation Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function and the document number to quickly locate them. Below is a short list of some of these documents. DT97-3: Managing Transients in Control IC Driven Power Stages AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality DT04-4: Using Monolithic High Voltage Gate Drivers AN-978: HV Floating MOS-Gate Driver ICs www.irf.com © 2009 International Rectifier 21 IRS2552D Programmable parameter characteristics 100 100 90 90 80 80 70 70 60 60 FMIN(kHz FMIN, FMAX(kHz Figure 7 to 12 provide the characteristics of the programmable parameters as a function of the value of the programming components. 50 40 50 40 30 30 20 20 10 10 0 0 0 300 600 900 1200 0 1500 5 10 15 20 25 30 35 40 45 50 RMIN(kΩ) CT(pF) RMIN, RMAX=12.1K Figure 7: FMIN, FMAX vs. CT Figure 8: FMIN vs. RMIN 2000 100 90 1600 80 60 DT(nS) FMAX(kHz) 70 50 40 1200 800 30 20 400 10 0 0 0 5 10 15 20 25 30 35 40 45 50 0 RMAX(kΩ) 400 800 1200 1600 2000 CDT(pF) RDT=2.21K Figure 9: FMAX vs. RMAX Figure 10: DT vs. CDT 100 3000 90 2500 80 70 FCR(kHz) DT(nS) 2000 1500 1000 60 50 40 30 20 500 10 0 0 0 1 2 3 4 5 6 7 0 RDT(KΩ) 500 1000 1500 2000 2500 3000 3500 CR(pF) Figure 11: DT vs. RDT Figure 12: FCR vs. CR www.irf.com © 2009 International Rectifier 22 Parameter characteristics Figure 13 to 18 provide the characteristics of the main parameters as a function of VCC or the oscillator frequency 6 20 5 16 IQCC(mA) IQCC(mA) 4 12 8 3 2 4 1 0 0 0 2 4 6 8 10 12 14 16 9 9.2 9.4 9.6 VCC(V) Figure 13: ICC vs. VCC 2 70 1.75 FMAX TDEAD(uS) Frequency(kHz) 10.2 1.5 50 40 FMIN 30 10 Figure 14: IQCC vs. VCC (VCC raising and falling 80 60 9.8 VCC(V) 1.25 1 0.75 20 0.5 10 0.25 0 0 10 11 12 13 14 15 16 10 11 12 13 VCC(V) 14 15 16 VCC(V) RMIN=12.1K, RNAX=6.81K Figure 16: td vs. VCC 10 10 9 9 8 8 7 7 ICC_FMAX(mA) ICC_RUN(mA Figure15: FMIN, FMAX vs. VCC 6 5 4 3 6 5 4 3 2 2 1 1 0 0 30 34 38 42 46 50 30 FMIN(kHz) 34 38 42 46 50 FMAX(kHz) Figure 17: ICC RUN vs. FMIN Figure 18: ICC FMAX vs. FMAX www.irf.com © 2009 International Rectifier 23 IRS2552D Parameter Temperature Trends Figures 38-58 provide the characteristics of the main parameters over temperature based on three temperatures (40 ºC, 25 ºC, and 125 ºC) average testing. 350 11.5 300 11 250 IQCCUV (uA) VCCUV ( V) 10.5 VCCUV+ 10 9.5 200 150 100 VCCUV9 50 8.5 0 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (C) 25 50 75 100 125 Temperature (C) Figure 19: VCCUV vs. temperature Figure 20: IQCCUV vs. temperature 5.5 4 3.9 5 3.8 ICC,FMIN (mA) IQCC (mA) 3.7 3.6 3.5 3.4 4.5 4 3.3 3.2 3.5 3.1 3 3 -50 -25 0 25 50 75 100 125 -50 Temperature (C) -25 0 25 50 75 100 125 Temperature (C) Figure 21: IQCC vs. temperature Figure 22: ICC,FMIN vs. temperature www.irf.com © 2009 International Rectifier 24 IRS2552D 8.5 16.6 8 VBSUV ( V) VCLAMP ( V) 16.1 15.6 VBSUV+ 7.5 7 VBSUV- 15.1 6.5 14.6 6 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (C) 25 50 75 100 125 Temperature (C) Figure 23: VCLAMP vs. temperature Figure 24: VBSUV vs. temperature 71 42.5 70.5 41.5 70 FMAX (kHz) FMIN (kHz) 40.5 39.5 38.5 69.5 69 68.5 68 37.5 67.5 36.5 67 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (C) Figure 25: fMIN vs. temperature 50 75 100 125 100 125 Figure 26: fMAX vs. temperature 5.2 5.2 5.15 5.15 5.1 5.1 5.05 5.05 VMAX ( V) VMIN ( V) 25 Temperature (C) 5 4.95 5 4.95 4.9 4.9 4.85 4.85 4.8 4.8 -50 -25 0 25 50 75 100 125 -50 Temperature (C) -25 0 25 50 75 Temperature (C) Figure 27: VMINvs. temperature Figure 28: VMAX vs. temperature www.irf.com © 2009 International Rectifier 25 IRS2552D 630 5.3 5.1 620 VCS,IGN (mV) ICR_IGN (uA) 4.9 4.7 4.5 4.3 610 600 590 4.1 580 3.9 3.7 570 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (C) 50 75 100 125 100 125 100 125 Figure 30: Vcs,ign vs. temperature 1.2 14 1.18 13.9 1.16 13.8 1.14 13.7 VB,ON ( V) DT (uS) Figure 29: ICR,IGN vs. temperature 1.12 1.1 1.08 13.6 13.5 13.4 1.06 13.3 1.04 13.2 1.02 13.1 1 13 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (C) 25 50 75 Temperature (C) Figure 31: tD vs. temperature Figure 32: VB,ON vs. temperature 90 20 80 18 16 70 14 60 IB,10V (mA) IB,CAP (mA) 25 Temperature (C) 50 40 30 12 10 8 6 20 4 10 2 0 0 -50 -25 0 25 50 75 100 125 -50 Temperature (C) -25 0 25 50 75 Temperature (C) Figure 33: IB,CAP vs. temperature Figure 34: IB,10V vs. temperature www.irf.com © 2009 International Rectifier 26 IRS2552D 5.3 2.1 5.1 4.9 ICD,SOURCE (uA) VSDTH ( V) 2.05 2 4.7 4.5 4.3 4.1 1.95 3.9 1.9 3.7 -50 -25 0 25 50 75 100 -50 125 -25 0 Temperature (C) 25 50 75 100 125 Temperature (C) Figure 35: VSD,TH vs. temperature Figure 36: VCD,SOURCEvs. temperature 1.27 5.2 5.15 1.25 1.23 5.05 VCSTH ( V) VCDTH ( V) 5.1 5 4.95 1.21 1.19 4.9 1.17 4.85 4.8 1.15 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (C) Figure 37: VCD,TH vs. temperature 50 75 100 125 100 125 Figure 38: VCDSTH vs. temperature 5.3 5.2 5.1 5.15 4.9 5.1 4.7 5.05 VCD,OC ( V) ICD,OC (uA) 25 Temperature (C) 4.5 4.3 5 4.95 4.1 4.9 3.9 4.85 3.7 4.8 -50 -25 0 25 50 75 100 125 -50 Temperature (C) -25 0 25 50 75 Temperature (C) Figure 39: ICD,OC vs. temperature Figure 40: VCD,OC vs. temperature www.irf.com © 2009 International Rectifier 27 IRS2552D 14 360 12 340 320 8 fCR ( z) DCMIN ( %) 10 6 300 4 280 2 260 0 240 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (C) 25 50 75 100 125 100 125 100 125 Temperature (C) Figure 41: DCMIN vs. temperature Figure 42: fCR vs. temperature 5 1040 4.95 1020 4.9 4.85 VDIM_SS ( V) VCR_SS (mV) 1000 980 960 940 4.8 4.75 4.7 4.65 920 4.6 900 4.55 880 4.5 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (C) Figure 43: VCR,SS vs. temperature 50 75 Figure 44: VDIM,SS vs. temperature 2.5 1.2 2.4 1.1 2.3 1 ENATH+ 2.2 IQBS (mA) ENATH ( V) 25 Temperature (C) 2.1 ENATH2 0.9 0.8 0.7 1.9 0.6 1.8 1.7 0.5 -50 -25 0 25 50 75 100 125 -50 Temperature (C) -25 0 25 50 75 Temperature (C) Figure 45: VENA vs. temperature Figure 46: IBS vs. temperature www.irf.com © 2009 International Rectifier 28 IRS2552D Package Details: PDIP16 and S016N www.irf.com © 2009 International Rectifier 29 IRS2552D Package Details: SOIC16N, Tape and Reel LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 15.70 16.30 D 7.40 7.60 E 6.40 6.60 F 10.20 10.40 G 1.50 n/a H 1.50 1.60 16SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.618 0.641 0.291 0.299 0.252 0.260 0.402 0.409 0.059 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 16SOICN Metric Imperial Code Min Max Min Max A 329.60 330.25 12.976 13.001 B 20.95 21.45 0.824 0.844 C 12.80 13.20 0.503 0.519 D 1.95 2.45 0.767 0.096 E 98.00 102.00 3.858 4.015 F n/a 22.40 n/a 0.881 G 18.50 21.10 0.728 0.830 H 16.40 18.40 0.645 0.724 www.irf.com © 2009 International Rectifier 30 IRS2552D Part Marking Information www.irf.com © 2009 International Rectifier 31 IRS2552D Ordering Information Standard Pack Base Part Number Package Type PDIP16 IRS2552D SOIC16N Complete Part Number Form Quantity Tube/Bulk 25 IRS2552DPBF Tube/Bulk 45 IRS2552DSPBF Tape and Reel 2500 IRS2552DSTRPBF The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied. For technical support, please contact IR’s Technical Assistance Center http://www.irf.com/technical-info/ WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 www.irf.com © 2009 International Rectifier 32