PHILIPS UDA1331H

INTEGRATED CIRCUITS
DATA SHEET
UDA1331H
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
Preliminary specification
Supersedes data of 1998 Apr 16
File under Integrated Circuits, IC01
1998 Oct 06
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
FEATURES
Document references
General
• “USB Specification”
• Universal Serial Bus (USB) stereo Audio Playback
Peripheral (APP) system with adaptive (5 to 55 kHz)
20-bits digital-to-analog conversion and filtering
• “USB Common Class Specification”
• “USB Device Class Definition for Audio Devices”
• “Device Class Definition for Human Interface Devices
(HID)”
• USB-compliant audio and Human Interface Device
(HID)
• “USB HID Usage Table”.
• Supports 12 Mbits/s full-speed serial data transmission
• Supports multiple audio data formats (8, 16 and 24 bits)
APPLICATIONS
• Supports headphone and line output
• USB monitors
• Fully automatic ‘Plug-and-Play’ operation
• USB speakers
• High linearity
• USB headsets
• Wide dynamic range
• USB telephone/answering machines
• Superior signal-to-noise ratio (typical 95 dB)
• USB links in consumer audio devices.
• Low total harmonic distortion (typical 90 dB)
• 3.3 V power supply
GENERAL DESCRIPTION
• Efficient power management
The UDA1331H is a stereo CMOS digital-to-analog
bitstream converter designed for USB-compliant audio
playback devices and multimedia audio applications.
The UDA1331H is an adaptive asynchronous sink USB
audio device with a continuous sampling frequency (fs)
range from 5 to 55 kHz. It contains a USB interface, an
embedded microcontroller and an Asynchronous
Digital-to-Analog Converter (ADAC).
• Low power consumption
• On-chip master clock oscillator, only an external crystal
is required
• Partly programmable USB descriptors and configuration
via I2C-bus.
Sound processing
The USB interface is the interface between the USB, the
ADAC and the microcontroller. The USB interface consists
of an analog front-end and a USB processor. The analog
front-end transforms the differential USB data to a digital
data stream. The USB processor buffers the input and
output data from the analog front-end and handles all
low-level USB protocols. The USB processor selects the
relevant data from the universal serial bus, performs an
extensive error detection and separates control
information (input and output) and audio information (input
only).
• Separate digital volume control for left and right channel
• Soft mute
• Digital bass and treble tone control
• External Digital Sound Processor (DSP) option possible
via standard I2S-bus or Japanese digital I/O format
• Selectable clipping prevention
• Selectable Dynamic Bass Boost (DBB)
• On-chip digital de-emphasis.
1998 Oct 06
2
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
feature processing DSP, the SFG, digital up-sampling
filters, a variable hold register, a Noise Shaper (NS) and a
Filter Stream DAC (FSDAC) with integrated filter and line
output drivers. The audio information is applied to the
ADAC via the USB processor or via the digital I/O input.
The control information becomes accessible at the
microcontroller. The audio information becomes available
at the digital I/O output or is fed directly to the ADAC.
The microcontroller handles the high-level USB protocols,
translates the incoming control requests and manages the
user interface via General Purpose (GP) pins and an
I2C-bus. The firmware for the microcontroller must be
located in an external (E)PROM.
An external DSP can be used for adding extra sound
processing features via the digital I/O-bus.
The UDA1331H supports the standard I2S-bus data input
format and the LSB-justified serial data input format with
word lengths of 16, 18 and 20 bits.
The ADAC enables the wide and continuous range of input
sampling frequencies. By means of a Sample Frequency
Generator (SFG), the ADAC is able to reconstruct the
average sample frequency from the incoming audio
samples. The ADAC also performs the sound processing.
The ADAC consists of FIFO registers, a unique audio
The wide dynamic range of the bitstream conversion
technique used in the UDA1331H guarantees a high audio
sound quality.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
IDD(tot)
IDD(ps)
supply voltage
total supply current
supply current in power-save
mode
note 1
3.0
−
−
3.3
50
18
3.6
−
−
V
mA
mA
−90(2)
0.0032
−30(2)
3.2
95
−80
0.01
−20
10
−
dB
%
dB
%
dBA
−
0.66
−
V
5
0
−
25
55
70
kHz
°C
Dynamic performance DAC
THD + N
----------------------S
total harmonic
distortion-plus-noise to signal
ratio
S/Nbz
signal-to-noise ratio at bipolar
zero
full-scale output voltage
(RMS value)
Vo(FS)(rms)
fs = 44.1 kHz; RL = 5 kΩ
at input signal of 1 kHz (0 dB)
−
−
at input signal of 1 kHz (−60 dB) −
−
A-weighted at code 0000H
90
VDD = 3.3 V
General characteristics
fi(sample)
Tamb
audio sample input frequency
operating ambient temperature
Notes
1. VDD is the supply voltage on pins VDDA, VDDE, VDDI and VDDX. VSS is the ground on pins VSSA, VSSE, VSSI and VSSX.
All VDD and VSS pins must be connected to the same supply or ground respectively.
2. The audio information from the USB interface is fed directly to the ADAC.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
UDA1331H QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm
1998 Oct 06
3
VERSION
SOT319-2
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
BLOCK DIAGRAM
D+
handbook, full pagewidth
D−
20
17
TC 55
RTCB 61
SHTCB 15
TEST
CONTROL
BLOCK
3 SCL
ANALOG FRONT-END
4 SDA
6 EA
8 PSEN
USB-PROCESSOR
9 ALE
11 P2.0
GP4/BCKO 14
12 P2.1
GP3/WSO 13
18 P2.2
GP2/DO 10
19 P2.3
DIGITAL I/O
GP1/DI 7
21 P2.4
GP0/BCKI 64
MICROCONTROLLER
GP5/WSI 2
22 P2.5
23 P2.6
24 P2.7
56 P0.0
FIFO REGISTERS
57 P0.1
58 P0.2
fs
59 P0.3
SAMPLE
FREQUENCY
GENERATOR
60 P0.4
AUDIO FEATURE
PROCESSING DSP
62 P0.5
63 P0.6
fs
5 P0.7
UP-SAMPLE FILTERS
64fs
VSSX 36
32 VDDE
30 VSSE
VARIABLE HOLD REGISTER
XTAL1 37
XTAL2 38
OSC
VDDX 39
VOUTL 53
UDA1331H
128fs
TIMING
51 VDDO
49 VSSO
3rd-ORDER
NOISE SHAPER
LEFT
DAC
29 VSSI
25 VDDI
45 VDDA
44 VSSA
RIGHT
DAC
46 VOUTR
REFERENCE
VOLTAGE
42
Vref
Fig.1 Block diagram.
1998 Oct 06
4
MBK529
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
n.c.
1
−
GP5/WSI
2
I/O
general purpose pin 5 or word select input
SCL
3
I/O
serial clock input (I2C-bus)
SDA
4
I/O
serial data input/output (I2C-bus)
P0.7
5
I/O
Port 0.7 of the microcontroller
EA
6
I/O
external access (active LOW)
GP1/DI
7
I/O
general purpose pin 1 or data input
PSEN
8
I/O
program store enable (active LOW)
ALE
9
I/O
address latch enable (active HIGH)
GP2/DO
10
I/O
general purpose pin 2 or data output for extra DSP chip
P2.0
11
I/O
Port 2.0 of the microcontroller
P2.1
12
I/O
Port 2.1 of the microcontroller
GP3/WSO
13
I/O
general purpose pin 3 or master word select output for extra DSP chip
GP4/BCKO
14
I/O
SHTCB
15
I
shift clock TCB input (active HIGH)
n.c.
16
−
not connected
not connected
general purpose pin 4 or master bit clock output for extra DSP chip
D−
17
I/O
negative data line of the differential data bus conform to the USB-standard
P2.2
18
I/O
Port 2.2 of the microcontroller
P2.3
19
I/O
Port 2.3 of the microcontroller
D+
20
I/O
positive data line of the differential data bus conform to the USB-standard
P2.4
21
I/O
Port 2.4 of the microcontroller
P2.5
22
I/O
Port 2.5 of the microcontroller
P2.6
23
I/O
Port 2.6 of the microcontroller
P2.7
24
I/O
VDDI
25
−
digital supply voltage core
n.c.
26
−
not connected
n.c.
27
−
not connected
n.c.
28
−
not connected
VSSI
29
−
digital ground core
VSSE
30
−
digital ground I/O pins
n.c.
31
−
not connected
VDDE
32
−
digital supply voltage I/O pins
n.c.
33
−
not connected
n.c.
34
−
not connected
n.c.
35
−
not connected
Port 2.7 of the microcontroller
VSSX
36
−
crystal oscillator ground
XTAL1
37
I
crystal oscillator input 1
XTAL2
38
O
crystal oscillator output 2
VDDX
39
−
crystal oscillator supply voltage
n.c.
40
−
not connected
1998 Oct 06
5
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
SYMBOL
PIN
I/O
n.c.
41
−
not connected
UDA1331H
DESCRIPTION
Vref
42
O
reference output voltage
n.c.
43
−
not connected
VSSA
44
−
analog ground
VDDA
45
−
analog supply voltage
VOUTR
46
O
right channel output voltage
n.c.
47
−
not connected
n.c.
48
−
not connected
VSSO
49
−
operational amplifier ground
n.c.
50
−
not connected
VDDO
51
−
operational amplifier supply voltage
n.c.
52
−
not connected
VOUTL
53
O
left channel output voltage
n.c.
54
−
not connected
TC
55
I
test control input (active HIGH)
P0.0
56
I/O
Port 0.0 of the microcontroller
P0.1
57
I/O
Port 0.1 of the microcontroller
P0.2
58
I/O
Port 0.2 of the microcontroller
P0.3
59
I/O
Port 0.3 of the microcontroller
P0.4
60
I/O
Port 0.4 of the microcontroller
RTCB
61
I
P0.5
62
I/O
Port 0.5 of the microcontroller
P0.6
63
I/O
Port 0.6 of the microcontroller
GP0/BCKI
64
I/O
general purpose pin 0 or master bit clock input
1998 Oct 06
asynchronous reset input for test control box (active HIGH)
6
Philips Semiconductors
Preliminary specification
52 n.c.
53 VOUTL
54 n.c.
55 TC
56 P0.0
57 P0.1
58 P0.2
UDA1331H
59 P0.3
60 P0.4
61 RTCB
62 P0.5
handbook, full pagewidth
63 P0.6
64 GP0/BCKI
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
51 VDDO
n.c. 1
50 n.c.
GP5/WSI 2
SCL
3
49 VSSO
SDA
4
48 n.c.
P0.7 5
47 n.c.
46 VOUTR
EA 6
GP1/DI 7
45 VDDA
PSEN 8
44 VSSA
43 n.c.
ALE 9
42 VREF
UDA1331H
GP2/DO 10
P2.0 11
41 n.c.
P2.1 12
40 n.c.
GP3/WSO 13
39 VDDX
GP4/BCKO 14
38 XTAL2
SHTCB 15
37 XTAL1
36 VSSX
n.c. 16
Fig.2 Pin configuration.
1998 Oct 06
7
VDDE 32
n.c. 31
VSSE 30
VSSI 29
n.c. 28
n.c. 27
n.c. 26
VDDI 25
33 n.c.
P2.7 24
P2.3 19
P2.6 23
34 n.c.
P2.5 22
P2.2 18
P2.4 21
35 n.c.
D+ 20
D− 17
MBK528
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
The PSIE is the digital front-end of the USB processor.
This module recovers the 12 MHz USB clock, detects the
USB sync word and handles all low-level USB protocols
and error checking.
FUNCTIONAL DESCRIPTION
All bold-faced parameters given in this data sheet
such as ‘bAlternateSetting’ are part of the USB
specification as described in “USB Device Class
Definition for Audio Devices”.
The MMU is the digital back-end of the USB processor.
It handles the temporary data storage of all USB packets
that are received or sent over the bus. Three types of
packets are defined on the USB. These are:
The Universal Serial Bus (USB)
Data and power are transferred via the USB by a 4-wire
cable. The signalling occurs via two wires and
point-to-point segments. The signals on each segment are
differentially driven into a cable of 90 Ω intrinsic
impedance. The differential receiver features input
sensitivity of at least 200 mV and sufficient common mode
rejection.
• Token packets
• Data packets
• Handshake packets.
The token packet contains information about the
destination of the data packet. The audio data is
transferred via an isochronous data sink endpoint and
consequently no handshaking mechanism is used.
The MMU also generates a 1 kHz clock that is locked to
the USB Start-Of-Frame (SOF) token.
The analog front-end
The analog front-end is an on-chip generic USB
transceiver. It is designed to allow voltage levels up to VDD
from standard or programmable logic to interface with the
physical layer of the USB. It is capable of receiving and
transmitting serial data at full speed (12 Mbits/s).
THE AUDIO SAMPLE REDISTRIBUTION (ASR) MODULE
The ASR module reads the audio samples from the MMU
and distributes these samples equidistant over a 1 ms
frame period. The distributed audio samples are translated
by the digital I/O module to standard I2S-bus format or
Japanese digital I/O format. The ASR module generates
the bit clock and the word select signal of the digital I/O.
The digital I/O formats the received audio samples to one
of the four specified serial digital audio formats
(standard I2S-bus, 16, 18 or 20 bits LSB-justified).
The USB processor
The USB processor forms the interface between the
analog front-end, the ADAC and the microcontroller.
The USB processor consists of:
• The Philips Serial Interface Engine (PSIE)
• The Memory Management Unit (MMU)
• The Audio Sample Redistribution (ASR) module.
The microcontroller
The microcontroller receives the control information
selected from the USB by the USB processor. It handles
the high-level USB protocols and the user interfaces.
THE PHILIPS SERIAL INTERFACE ENGINE AND MEMORY
MANAGEMENT UNIT (PSIE AND MMU)
The PSIE and MMU translate the electrical USB signals
into bytes and signals. Depending upon the USB device
address and the USB endpoint address, the USB data is
directed to the correct endpoint buffer on the PSIE and
MMU interface. The data transfer could be of the bulk,
isochronous, control or interrupt type. The USB device
address is configured during the enumeration process.
The UDA1331H has three endpoints. These are:
The major task of the software process, that is mapped
upon the microcontroller, is to control the different modules
of the UDA1331H in such a way that it behaves as a USB
device. Therefore the microcontroller:
• Interprets the USB requests and maps them upon the
UDA1331H application
• Controls the internal operation of the UDA1331H and
the digital I/O pins
• Control endpoint 0
• Status interrupt endpoint
• Isochronous data sink endpoint.
• Communicates with the external world (EEPROM) using
the I2C-bus facility and the general purpose I/O pins.
The amount of bytes per packet on the control endpoint is
limited by the PSIE and MMU hardware to 8 bytes per
packet.
The firmware must be located in an external (E)PROM.
The UDA1331H will be delivered with standard USB
compliant firmware.
1998 Oct 06
8
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
The Asynchronous Digital-to-Analog Converter
(ADAC)
Table 1
The ADAC receives USB audio information from the USB
processor or from the digital I/O-bus. The ADAC is able to
reconstruct the sample clock from the rate at which the
audio samples arrive and handles the audio sound
processing. After processing, the audio signal is
up-sampled, noise-shaped and converted to analog output
voltages capable of driving a line output. The ADAC
consists of:
Frequency domains for audio processing
DOMAIN
SAMPLE FREQUENCY (kHz)
1
5 to 12
2
12 to 25
3
25 to 40
4
40 to 55
THE NOISE SHAPER
A 3rd-order noise shaper converts the oversampled data
to a noise-shaped bitstream for the FSDAC. The in-band
quantization noise is shifted to frequencies well above the
audio band.
• A Sample Frequency Generator (SFG)
• First-In First-Out (FIFO) registers
• An audio feature processing DSP
• Two digital up-sample filters
• A variable hold register
THE FILTER STREAM DAC (FSDAC)
• A digital Noise Shaper (NS)
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post filter is not needed
because of the inherent filter function of the DAC.
On-board amplifiers convert the FSDAC output current to
an output voltage signal capable of driving a line output.
• A Filter Stream DAC (FSDAC) with integrated filter and
line output drivers.
THE SAMPLE FREQUENCY GENERATOR (SFG)
The SFG controls the timing signals for the asynchronous
digital-to-analog conversion. By means of a digital PLL,
the SFG automatically recovers the applied sampling
frequency and generates the accurate timing signals for
the audio feature processing DSP and the up-sample
filters.
USB Audio Playback Peripheral (APP) descriptors
In a typical USB environment the USB host has to know
which kind of devices are connected. For this purpose
each device contains a number of USB descriptors. These
descriptors describe, from different points of view (USB
configuration, USB interface and USB endpoint), the
capabilities of a device. Each of them can be requested by
the host. The collection of descriptors is denoted as a
descriptor map. This descriptor map will be reported to the
USB host during enumeration and on request.
FIRST-IN FIRST-OUT (FIFO) REGISTERS
The FIFO registers are used to store the audio samples
temporarily coming from the USB processor or from the
digital I/O input. The use of a FIFO register (in conjunction
with the SFG) is necessary to remove all jitter present on
the incoming audio signal.
THE AUDIO FEATURE PROCESSING DSP
The full descriptor map is implemented in the firmware
exploiting the full functionality of the UDA1331H. The USB
descriptors and their most important fields, in relationship
to the characteristics of the UDA1331H are briefly
explained below.
A DSP processes the sound features. The control and
mapping of the sound features is explained in Section
“Controlling the USB Audio Playback Peripheral (APP)”.
Depending on the sampling rate (fs) the DSP has four
frequency domains in which the treble and bass are
regulated (see Table 1). The domain is chosen
automatically.
GENERAL DESCRIPTORS
The UDA1331H supports one configuration containing a
control interface, an audio interface and a HID interface.
The descriptor map that describes this configuration is
partly fixed and partly programmable.
THE UP-SAMPLE FILTERS AND VARIABLE HOLD REGISTER
After the audio feature processing DSP two up-sample
filters and a variable hold register increase the
oversampling rate to 128fs.
1998 Oct 06
9
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
handbook, full pagewidth
INPUT TERMINAL
UDA1331H
FEATURE UNIT
OUTPUT TERMINAL
FU
IT
OT
MBK530
Fig.3 Audio function topology.
The programmable part can be retrieved from one of four
configuration maps located in the (E)PROM or from an
I2C-bus EEPROM. At start-up one of four configuration
maps can be selected depending on the logical
combination of GP3 and GP0. It is possible to overwrite
this configuration map with a configuration map loaded
from an I2C-bus EEPROM.
Table 2
Audio bandwidth at each audio mode
AUDIO MODE
8-bit PCM; mono
8-bit PCM; stereo
16-bit PCM; mono
16-bit PCM; stereo
AUDIO DEVICE CLASS SPECIFIC DESCRIPTORS
24-bit PCM; mono
The audio device class is partly specified with standard
descriptors and partly with specific audio device class
descriptors. The standard descriptors specify the number
and the type of the interface or endpoint. The UDA1331H
supports 7 different audio modes:
24-bit PCM; stereo
The maximum number of audio data samples within a USB
packet arriving on the isochronous sink endpoint is
restricted by the buffer capacity of this isochronous
endpoint. The maximum buffer capacity is 336 bytes/ms.
• 8-bit Pulse Code Modulation (PCM) mono or stereo
audio data
For each alternate setting with audio, a maximum
bandwidth is claimed as indicated in the standard
isochronous audio data endpoint descriptor
wMaxPacketSize field. To allow a small overshoot in the
number of audio samples per packet, the top sample
frequency of 55 kHz is taken in the calculation of the
bandwidth for each alternate setting. For each alternate
setting, with its own isochronous audio data endpoint
descriptor, wMaxPacketSize field is then defined as
described in Table 2.
• 16-bit PCM mono or stereo audio data
• 24-bit PCM mono or stereo audio data
• Zero bandwidth mode.
Each mode is defined as an alternate setting of the audio
interface, selectable with the standard audio streaming
interface descriptor bAlternateSetting field.
The seven alternate settings are described in more detail
by the specific audio device class descriptors.
Although in a specific UDA1331H application no endpoint
control properties can be used upon the isochronous
adaptive sink endpoint, the descriptors are still necessary
to inform the host about the definition of this endpoint:
isochronous, adaptive, sink, continuous sampling
frequency (at input side of this endpoint) with lower bound
of 5 kHz and upper bound of 55 kHz.
The UDA1331H supports the Input Terminal (IT), Output
Terminal (OT) and the Feature Unit (FU) descriptors.
The input and output terminals are not controllable via the
USB. The feature unit provides the basic manipulation of
the incoming logical channels.
The supported sound features are:
The audio class specific descriptors can be requested with
the ‘Get descriptor: configuration request’, which returns
all the descriptors, except the device descriptor.
• Volume control
• Mute control
• Treble control
• Bass control
• Bass boost control.
1998 Oct 06
wMaxPacketSize
56 (8⁄8 × 1 × 56)
112 (8⁄8 × 2 × 56)
112 (16⁄8 × 1 × 56)
224 (16⁄8 × 2 × 56)
168 (24⁄8 × 1 × 56)
336 (24⁄8 × 2 × 56)
10
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
HUMAN INTERFACE DEVICE SPECIFIC DESCRIPTORS
Controlling the USB Audio Playback Peripheral (APP)
The inputs defined on the UDA1331H are transmitted via
the USB to the host according to the HID class. The host
responds with the appropriate settings via the audio device
class for the audio related parts or via the HID class for the
HID related inputs and outputs of the UDA1331H.
This section describes the functionality of the feature unit
of the UDA1331H. The mapping of this functionality onto
USB descriptors is as implemented in the firmware.
The sound features as defined in the “USB Device Class
Definition for Audio Devices” are mapped on the
UDA1331H specific feature registers by the
microcontroller. These specific sound features are:
A HID descriptor is necessary to inform the host about the
conception of the user interface. The host communicates
via the HID device driver using either the control pipe or
the interrupt pipe. The UDA1331H uses USB endpoint 0
(control pipe) to respond to the HID specific ‘Get/set report
request’ to receive or transmit data from or to the
UDA1331H. The UDA1331H uses the status interrupt
endpoint as interrupt pipe for polling asynchronous data.
• Volume control (separate for left and right stereo
channels, no master channel)
• Mute control (only master channel)
• Treble control (only master channel)
• Bass control (only master channel)
• Dynamic bass boost control (only master channel).
The UDA1331H is a high-speed device. The maximum
transaction size is 64 bytes per USB frame and the polling
rate is defined at a maximum of every 1 ms.
These specific features can be activated via the host
(audio device class requests) or via the GP pins (HID plus
audio device class requests). Via the I2C-bus the user is
able to download the necessary configuration data for
different applications (definition of the function of the GP
pins, with or without digital I/O functionality, etc.).
The mapping and control of the standard USB audio
features and UDA1331H specific features is described
below.
The host requests the configuration descriptor which
includes the standard interface descriptor, the HID
endpoint descriptor and the HID descriptor. The HID
device driver of the host then requests the report
descriptor.
Report descriptors are composed of pieces of information
about the device. Each piece of information is called an
item. All items have a 1-byte prefix that contains the item
tag, type and size. In the UDA1331H only the short item
basic type is used.
VOLUME CONTROL
Volume control is possible via the host or via predefined
GP pins. The setting of 0 dB is always referenced to the
maximum available volume setting. Table 3 gives the
mapping of wVolume value (as defined in the “USB
Device Class Definition for Audio Devices”) upon the
actual volume setting of the USB APP. When using the
UDA1331H, the range is 0 down to −60 dB (in steps of
1 dB) and −∞ dB. Independant control of ‘left’/’right’
volume is possible. It should be noted that wVolume
bits B7 to B0 are not used. Values above 0 dB are
returned as 0 dB. The volume value at start-up of the
device is defined in the selected configuration map.
The hosts HID device driver will parse the report descriptor
and the defined items. By examining all of these items, the
HID class driver is able to determine the size and
composition of data reports from the device.
The main items of the UDA1331H are input and output
reports. Input reports are sent via the interrupt pipe
(UDA1331H USB address 3). Input and output reports can
be requested by the host via the control endpoint (USB
address 0).
The UDA1331H supports a maximum of three
pushbuttons, which represents a certain feature of the
UDA1331H. If pressed by the user the pushbutton will go
to its ‘ON’ state, if not pressed the pushbutton will go back
to its ‘OFF’ state. The UDA1331H supports a maximum of
two outputs for e.g. user LEDs.
Balance control is possible via the separate volume control
option of both channels. Therefore the characteristics of
the balance control are equal to the volume control
characteristics.
For more information about the input and output functions
of the UDA1331H see the application documentation of
the device.
1998 Oct 06
11
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
Table 3
UDA1331H
Volume control characteristics
wVOLUME
B15
B14
B13
B12
B11
B10
B9
B8
VOLUME USB SIDE
(dB)
VOLUME USB APP
(dB)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
−1
−1
1
1
1
1
1
1
1
0
−2
−2
1
1
1
1
1
1
0
1
−3
−3
1
1
1
1
1
1
0
0
−4
−4
1
1
1
1
1
0
1
1
−5
−5
1
1
1
1
1
0
1
0
−6
−6
1
1
1
1
1
0
0
1
−7
−7
1
1
1
1
1
0
0
0
−8
−8
1
1
1
1
0
1
1
1
−9
−9
1
1
1
1
0
1
1
0
−10
−10
...
...
...
...
...
...
...
...
...
...
1
1
0
0
0
1
0
1
−59
−59
1
1
0
0
0
1
0
0
−60
−60
1
1
0
0
0
0
1
1
−61
−∞
1
1
0
0
0
0
1
0
−62
−∞
...
...
...
...
...
...
...
...
...
...
1
0
0
0
0
0
0
0
−∞
−∞
This amounts to a mute transition of 23 ms at
fs = 44.1 kHz. When the mute is released, the samples are
returned to the full level again following a raised cosine
curve with the same coefficients being used in reversed
order. The mute, on the master channel is synchronized to
the sample clock, so that operation always takes place on
complete samples.
MUTE CONTROL
Mute is one of the sound features as defined in the “USB
Device Class Definition for Audio Devices”. The mute
control request data bMute controls the position of the
mute switch. The position can be either on or off. When
bMute is true the feature unit is muted. When bMute is
false the feature unit is not muted.
A mute can be given via the host or by pressing a
predefined GP pin.
When the mute is active for the master channel, the value
of the sample is decreased smoothly to zero following a
raised cosine curve. There are 32 coefficients used to step
down the value of the data, each one being used 32 times
before stepping to the next.
1998 Oct 06
12
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
TREBLE CONTROL
The treble control is available for the master channel of the UDA1331H. Treble can be regulated in three modes:
minimum, flat and maximum mode. The preferred mode is selected at start-up of the device (configuration map).
The corner frequency is 3000 Hz for the minimum mode and 1500 Hz for the maximum mode. The treble range is from
0 to 6 dB in steps of 2 dB. It should be noted that the negative treble values as defined in the “USB Device Class
Definition for Audio Devices” are not supported by the UDA1331H; the 0 dB value is returned as 0 dB. Table 4 gives the
mapping of the bTreble value upon the actual treble setting of the USB APP.
Table 4
Treble control characteristics
bTREBLE
B7
B6
B5
B4
B3
B2
B1
B0
TREBLE USB
SIDE (dB)
0
0
0
0
0
0
0
0
0.00
0
0
0
0
0
0
0
1
0.25
0
0
0
0
0
0
1
0
0.50
0
0
0
0
0
0
1
1
0.75
0
0
0
0
0
1
0
0
1.00
0
0
0
0
0
1
0
1
1.25
0
0
0
0
0
1
1
0
1.50
0
0
0
0
0
1
1
1
1.75
0
0
0
0
1
0
0
0
2.00
0
0
0
0
1
0
0
1
2.25
0
0
0
0
1
0
1
0
2.50
0
0
0
0
1
0
1
1
2.75
0
0
0
0
1
1
0
0
3.00
0
0
0
0
1
1
0
1
3.25
0
0
0
1
0
1
0
1
5.25
TREBLE USB APP (dB)
minimum
flat
maximum
0
0
0
2
0
2
4
0
4
6
0
6
6
0
6
6
0
6
6
0
6
...
...
0
0
0
1
1
1
0
1
7.25
0
0
1
0
0
1
0
1
9.25
...
...
0
1
1998 Oct 06
1
1
1
1
1
1
13
31.75
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
BASS CONTROL
The bass control is available for the master channel of the UDA1331H. Bass can be regulated in three modes: minimum,
flat and maximum mode. The preferred mode is selected at start-up of the device (configuration map). The Bass range
is from 0 to about 14 dB (minimum mode) or about 24 dB (maximum mode) in steps of 2 dB. It should be noted that the
negative bass values as defined in the “USB Device Class Definition for Audio Devices” are not supported by the
UDA1331H; the 0 dB value is returned as 0 dB. The maximum Bass value which will be reported to the host is always
24 dB independent of the mode. The maximum mode is the most accurate mode when the Bass values are reported to
the host. The corner frequency is 100 Hz for the minimum mode and 75 Hz for the maximum mode. Table 5 gives the
mapping of the bBass value upon the actual bass setting of the USB APP.
Table 5
Bass control characteristics
bBASS
B7
B6
B5
B4
B3
B2
B1
B0
BASS USB
SIDE (dB)
0
0
0
0
0
0
0
0
0.00
0
0
0
0
0
0
0
1
0.25
0
0
0
0
0
0
1
0
0.50
0
0
0
0
0
0
1
1
0.75
0
0
0
0
0
1
0
0
1.00
0
0
0
0
0
1
0
1
1.25
0
0
0
0
0
1
1
0
1.50
0
0
0
0
0
1
1
1
1.75
0
0
0
0
1
0
0
0
2.00
0
0
0
0
1
0
0
1
2.25
0
0
0
0
1
0
1
0
2.50
0
0
0
0
1
0
1
1
2.75
0
0
0
0
1
1
0
0
3.00
0
0
0
0
1
1
0
1
3.25
0
0
0
1
0
1
0
1
5.25
BASS USB APP (dB)
minimum
flat
maximum
0
0
0
1.1
0
1.7
2.4
0
3.6
3.7
0
5.4
5.2
0
7.4
6.8
0
9.4
8.4
0
11.3
10.2
0
13.3
11.9
0
15.2
13.7
0
17.3
...
...
0
0
0
1
1
1
0
1
7.25
...
0
0
1
0
0
1
0
1
9.25
0
0
1
0
1
1
0
1
11.25
...
...
0
0
1
1
0
1
0
1
13.25
0
0
1
1
1
1
0
1
15.25
...
...
0
1
0
0
0
1
0
1
17.25
...
1998 Oct 06
14
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
bBASS
B7
B6
B5
B4
B3
B2
B1
B0
BASS USB
SIDE (dB)
0
1
0
0
1
1
0
1
19.25
BASS USB APP (dB)
minimum
flat
maximum
13.7
0
19.2
13.7
0
21.2
13.7
0
23.2
13.7
0
23.2
13.7
0
23.2
13.7
0
23.2
13.7
0
23.2
13.7
0
23.2
...
0
0
1
1
1
0
1
1
21.25
0
1
0
1
0
1
0
1
23.25
...
...
0
1
1
0
0
1
0
1
25.25
...
0
1
1
0
1
1
0
1
27.25
0
1
1
1
0
1
0
1
29.25
...
...
0
1
1
1
1
1
0
1
31.25
...
0
1
1
1
1
1
1
1
31.75
DYNAMIC BASS BOOST CONTROL
Clipping prevention
Bass boost is one of the sound features as defined in the
“USB Device Class Definition for Audio Devices”.
The bass boost control request data bBassBoost controls
the position of the bass boost switch. The position can be
either on or off. When bBassBoost is true the bass boost
is activated. When bBassBoost is false the bass boost is
off.
If the maximum of the bass plus volume gives clipping, the
Bass is reduced. Clipping prevention is selectable via the
configuration map.
De-emphasis
De-emphasis is one of the properties which is not
supported by the USB. De-emphasis for 44.1 kHz can be
predefined in the configuration map selected at start-up of
the UDA1331H.
When clipping prevention is active, the bass is reduced to
avoid clipping with high volume settings. Bass boost is
selectable via the configuration map (see Table 6).
If byte 19H is loaded with 00H, bass boost is not reported
to the USB host by the device.
1998 Oct 06
15
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
3.3 V
handbook, full pagewidth
UDA1331H
3.3 V
3.3 V
22 kΩ
3.3 V
22 kΩ
22 kΩ
GP0
GP3
TR3
KEY 1
SW1
1.5 kΩ
KEY 2
SW2
22 kΩ
TR1
TR2
5
Vbus
D1
D2
22 kΩ
USB-B
connector
1
1
2
22 kΩ
2
GP5
22 kΩ
1
2
Vbus
22 Ω
3
D−
D+
22 Ω
4
MGM109
6
10 nF
22 pF
22 pF
10 nF
Fig.4 Diode matrix selection.
After selecting a configuration map the user cannot
change the chosen settings for the GP pins, internal
configuration, descriptors, etc.
Start-up and configuration of the UDA1331H
START-UP OF THE UDA1331H
After power-on, an internal power-on reset signal becomes
HIGH after a certain RC-time (R = 5 kΩ and C = Cref).
During 10 ms after power-on reset the UDA1331H has to
initiate the internal settings. After the power-on reset the
UDA1331H becomes master of the I2C-bus.
The UDA1331H tries to read the eventually connected
EEPROM and if an EEPROM is detected, the internal
descriptors are overwritten and the selected port
configuration is applied. If no EEPROM is detected, the
UDA1331H tries to read the logical levels of GP3 and GP0.
A choice can be made from four configuration maps via
these two pins.
For more information about the four (vendor specific)
configuration maps located in the (E)PROM and the diode
matrix see the application documentation.
CONFIGURATION OPTIONS OF THE UDA1331H VIA AN
I2C-BUS EEPROM
If an EEPROM is detected (reading byte 0 as AAH and
byte 1 as 55H), the UDA1331H will use the configuration
map in the EEPROM instead of one of four configuration
maps. The layout of the configuration map is fixed, the
values (except bytes 0 and 1) are user definable
(see Table 6). If the user wants to change these values
(the manufacturers name for instance), this can be
achieved via the EEPROM code.
CONFIGURATION SELECTION OF THE UDA1331H VIA A DIODE
MATRIX
The communication between the UDA1331H and the
external I2C-bus device is based on the standard I2C-bus
protocol given in the Philips specification “The I2C-bus and
how to use it (including specifications)”, which can be
ordered using the code 9398 393 40011. The I2C-bus has
two lines: a clock line SCL and a serial data line SDA
(see Fig.5).
The UDA1331H uses a configuration map to hold a
number of specific configurable data on hardware,
product, component and USB configuration level.
At start-up without EEPROM, the UDA1331H will scan the
logical levels of GP3 and GP0. With these two pins it is
possible to select one of the four possible (vendor specific)
configuration maps which are held in the external
(E)PROM. This selection can be achieved via a diode
matrix (see Fig.4).
1998 Oct 06
16
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t BUF
t LOW
tr
tf
t HD;STA
t SP
Philips Semiconductors
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
1998 Oct 06
SDA
t HD;STA
P
S
t HD;DAT
t HIGH
t SU;DAT
t SU;STA
MBC611
P
Preliminary specification
Fig.5 Definition of timing of the I2C-bus.
t SU;STO
Sr
UDA1331H
handbook, full pagewidth
17
SCL
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
Table 6
UDA1331H
Control options for the UDA1331H via the EEPROM configuration map; note 1
BYTE
(HEX)
REGISTER
NAME
COMMENTS
BIT
VALUE
0
−
recognition pattern; do not change it
AAH
1
−
recognition pattern; do not change it
55H
2
ASR control register
robust word clock
7
serial I2S-bus output format
phase inversion
4
bits per sample modi
3
ADAC mode register 0
3 and 2
00 = I2S-bus
01 = 16-bit LSB
10 = 18-bit LSB
11 = 20-bit LSB
0 = mono phase inversion off
1 = mono phase inversion on
00 = reserved
01 = 8-bit audio
10 = 16-bit audio
11 = 24-bit audio
audio mode
1
0 = mono
1 = stereo
ASR register start-up mode
0
0 = stop
1 = go
selection ADAC mode register
7
0
audio feature mode
1998 Oct 06
6 and 5
0 = off
1 = on
6 and 5
00 = flat
01 = minimum
10 = minimum
11 = maximum
de-emphasis
4
0 = de-emphasis off
1 = de-emphasis on
channel manipulation
3
0 = L ⇒ L, R ⇒ R
1 = L ⇒ R, R ⇒ L
synchronous/asynchronous control
2
0 = asynchronous
1 = synchronous
mute control
1
0 = no mute
1 = mute active
reset ADAC
0
0 = no reset ADAC
1 = reset ADAC
18
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
BYTE
(HEX)
REGISTER
NAME
4
ADAC mode register 1
5
I/O selection register
UDA1331H
COMMENTS
selection ADAC mode register
7
digital PLL lock speed
6 and 5
digital PLL lock mode
4
VALUE
1
00 = lock after 512 samples
01 = lock after 2048 samples
10 = lock after 4096 samples
11 = lock after 16384 samples
0 = adaptive
1 = fixed
digital PLL mode
3 and 2
00 = adaptive
01 = fixed state 1
10 = fixed state 2
11 = fixed state 3
serial I2S-bus input format
1 and 0
00 = I2S-bus
01 = 16-bit LSB
10 = 18-bit LSB
11 = 20-bit LSB
clipping
7
0 = clipping prevention off
1 = clipping prevention on
I2S-bus usage
6
0 = no I2S-bus used
1 = I2S-bus used
4/6 pins I2S-bus (see Section “The
general purpose pins (GP0 to GP5)”)
5
only if I2S-bus is used;
0 = 4 pins I2S-bus
1 = 6 pins I2S-bus
GP4
4
GP3
3
GP2
2
0 = function 1
1 = function 2
(see Tables 7, 8 and 9)
GP1
1
GP0
0
6
GP0 Usage Page if HID selected
7
GP0 Usage if HID selected
8
reserved
9
reserved
A
GP3 Usage Page if HID selected
B
GP3 Usage if HID selected
C
reserved
D
reserved
E
GP4 Usage Page if HID selected
F
GP4 Usage if HID selected
10
reserved
1998 Oct 06
BIT
19
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
BYTE
(HEX)
11
REGISTER
NAME
GP1 and GP2 outputs
definition register
UDA1331H
COMMENTS
BIT
VALUE
reserved
7
reserved
6
application GP2 function 2
5
0 = HID output 2
1 = LED output 2 (activated
when DBB is active)
application GP1 function 2
4
0 = HID output 1
1 = LED output 1 (activated
when mute is active)
polarity GP2 function 1
3
polarity GP1 function 1
2
polarity GP2 function 2
1
normal or inversed output
functionality:
0 = according Table 7
1 = inversed
polarity GP1 function 2
0
12
GP1 Usage Page if HID selected
13
GP1 Usage if HID selected
14
GP2 Usage Page if HID selected
15
GP2 Usage if HID selected
16
time between releasing standby and
enabling the audio output; steps of
20 ms
17
time between ‘no isochronous data
present’ and activating the mute
output; steps of 1 s; (only applicable
for function 1; no digital I/O
communication)
18
time between activating the mute
output and activating the standby
output; steps of 5 s; (only applicable
for function 1; no digital I/O
communication). When filled with zero
standby will not be activated.
19
default bass boost value on top of
Bass USB APP for Dynamic Bass
Boost (DBB); see Table 5
bass boost = register value; if
bass boost + Bass USB APP
is larger then the maximum
value of Table 5, the maximum
value is used (no bass boost
in flat mode)
1A
default volume value of USB APP
volume = −register value
1B
idVendor high byte
1C
idVendor low byte
1D
idProduct high byte
1E
idProduct low byte
1F
bmAttributes
20
maximum power steps of 2 mA with
maximum 500 mA
1998 Oct 06
20
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
BYTE
(HEX)
REGISTER
NAME
UDA1331H
COMMENTS
21
wTerminalType high byte
22
wTerminalType low byte
BIT
VALUE
23
24
25
pointer language string
32
26
pointer manufacturer string
36
27
pointer product string
46
28
pointer serial number
54
32 ⇒
language string
36 ⇒
−
manufacturer string
46 ⇒
−
product string
54 ⇒
−
serial number; note 2
Notes
1. An extensive description of the USB control options is available in the “USB Device Class Definition for Audio
Devices”.
2. The serial number is only supported in the external configuration map and not in the four internal configuration maps.
The general purpose pins (GP0 to GP5)
The UDA1331H has 6 General Purpose (GP) pins; these are pins GP0 to GP5. These can be used either for digital I/O
functions or for general purposes. The configurations presented are as implemented in the standard firmware.
There are basically three port configurations:
• No digital I/O communication
• 4-pins digital I/O communication
• 6-pins digital I/O communication.
These port configurations can be selected via the configuration map at start-up of the UDA1331H.
The user can make a selection between two functions for each of the pins GP0 to GP4 (see byte 5 in Table 6), except if
digital I/O communication is selected (see Tables 7, 8 and 9).
1998 Oct 06
21
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
Table 7
UDA1331H
No digital I/O communication
PIN
INPUT/OUTPUT
FUNCTION 1
FUNCTION 2
GP5
output; not programmable; note 2
connect/disconnect
connect/disconnect
GP4
inputs; programmable; note 1
alarm mute; note 3
HID input 3
HID input 2
HID input 2
HID input 1
HID input 1
standby; note 4
HID/LED output 2; note 6
mute; note 5
HID/LED output 1; note 6
GP3
GP0
GP2
outputs; programmable
GP1
Notes
1. The input pins must have a pull-up resistor.
2. Connect/disconnect: holds the USB ‘disconnected’ as long as the initialization is not finished.
3. Alarm mute: input to switch the sound off; specially used if the USB host program does not respond to the control.
This pin acts directly on the sound and passes the mute to the USB host.
4. Standby is switched on (output becomes LOW) after a programmable time if the mute is active (see Byte 18 in
Table 6).
5. Mute is switched on (output becomes LOW) after a programmable time if the isochronous data flow is interrupted
(see Byte 17 in Table 6).
6. For selection between HID/LED application see configuration map byte 11 (output is active HIGH).
Table 8
4-pins digital I/O communication
PIN
GP5
GP4
GP3
GP2
GP1
GP0
INPUT/OUTPUT
output; not programmable; note 1
digital I/O-bus
input; programmable
FUNCTION 1
connect/disconnect
BCKO
WSO
DO
DI
HID input 1
FUNCTION 2
connect/disconnect
BCKO
WSO
DO
DI
alarm mute; note 2
Notes
1. Connect/disconnect: holds the USB ‘disconnected’ as long as the initialization is not finished.
2. Alarm mute: input to switch the sound off; specially used if the USB host program does not respond to the control.
This pin acts directly on the sound and passes the mute to the USB host.
1998 Oct 06
22
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
Table 9
UDA1331H
6-pins digital I/O communication
PIN
GP5
GP4
GP3
GP2
GP1
GP0
INPUT/OUTPUT
digital I/O-bus
FUNCTION
WSI
BCKO
WSO
DO
DI
BCKI
Filter characteristics
The overall filter characteristic of the UDA1331H in flat mode is given in Fig.6. The overall filter characteristic of the
UDA1331H includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the FSDAC
(fs = 44.1 kHz).
DSP extension port
An external DSP can be used for adding extra sound processing features via the digital I/O-bus. The UDA1331H
supports the standard I2S-bus data protocol and the LSB-justified serial data input format with word lengths
of 16, 18 and 20 bits. Using the 4-pins digital I/O-bus the UDA1331H device acts as a master, controlling the BCK and
WS signals. The period of the WS signal is determined by the number of samples in the 1 ms frame of the USB. This
implies that the WS signal does not have a constant period time, but is jittery. Using the 6-pins digital I/O-bus GP2, GP3
and GP4 are the output pins (master) and GP0, GP1 and GP5 are the input pins (slave).
For characteristic timing of the I2S-bus input interface see Figs 7 and 8.
1998 Oct 06
23
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
MGM110
−0
handbook, full pagewidth
−20
volume
(dB)
−40
−60
−80
−100
−120
−140
−160
0
10
20
30
40
50
60
70
80
90
100
f (kHz)
Fig.6 Overall filter characteristics of the UDA1331H.
LEFT
handbook, full pagewidth
WS
RIGHT
tr
tBCK(H)
tf
ts;WS
th;WS
tBCK(L)
BCK
Tcy
ts;DAT
th;DAT
DATA
LSB
MSB
MGK003
Fig.7 Timing of digital I/O input signals.
1998 Oct 06
24
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2
RIGHT
>=8
3
1
2
>=8
3
BCK
DATA
MSB
B2
LSB MSB
B2
LSB MSB
INPUT FORMAT I2S-BUS
WS
RIGHT
LEFT
16
15
1
16
B15 LSB
MSB
2
15
2
1
BCK
MSB
DATA
B2
B2
B15 LSB
Philips Semiconductors
1
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
handbook, full pagewidth
1998 Oct 06
LEFT
WS
25
LSB-JUSTIFIED FORMAT 16 BITS
WS
RIGHT
LEFT
18
17
16
15
2
1
18
B17
LSB
MSB
17
16
15
2
1
B17
LSB
2
1
BCK
DATA
MSB
B2
B3
B4
B2
B3
B4
LSB-JUSTIFIED FORMAT 18 BITS
WS
LEFT
20
19
18
RIGHT
17
16
15
2
1
20
B19
LSB
MSB
19
18
17
16
15
BCK
B2
B3
B4
B5
B6
B2
B3
B4
B5
B6
B19
LSB
MGK002
LSB-JUSTIFIED FORMAT 20 BITS
Fig.8 Input formats.
Preliminary specification
MSB
UDA1331H
DATA
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
All digital I/Os
VI/O
DC input/output voltage range
−0.5
−
VDD
V
IO
output current
−
−
4
mA
Temperature
Tj
junction temperature
0
−
125
°C
Tstg
storage temperature
−55
−
+150
°C
Tamb
operating ambient temperature
0
25
70
°C
note 1
−3000
−
+3000
V
note 2
−300
−
+300
V
Electrostatic handling
Ves
electrostatic handling
Notes
1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
2. Equivalent to discharging a 200 pF capacitor through a 2.5 µH series inductor and a 25 Ω resistor.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
VALUE
UNIT
48
K/W
MAX.
UNIT
in free air
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
VDD
supply voltage
3.0
3.3
3.6
V
VI
DC input voltage for D+ and D−
0.0
−
VDD
V
VI/O
DC input voltage for the digital I/Os
0.0
−
VDD
V
1998 Oct 06
26
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
DC CHARACTERISTICS
VDD = 3.3 V; VSS = 0 V; Tamb = 25 °C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDE
digital supply voltage I/O pins
3.0
3.3
3.6
V
VDDI
digital supply voltage core
analog supply voltage
operational amplifier supply voltage
3.0
3.0
3.0
3.3
3.3
3.3
3.6
3.6
3.6
V
V
V
crystal oscillator supply voltage
digital supply current I/O pins
3.0
−
3.3
3
3.6
−
V
mA
digital supply current core
−
36
−
mA
analog supply current
operational amplifier supply current
−
−
4.2
4.0
−
−
mA
mA
crystal oscillator supply current
total power dissipation
total power dissipation in
power-save mode
−
−
−
2.1
165
60
15.0(2)
−
−
mA
mW
mW
−
−
−
−
VDDI
VDDI
0.3
10
V
V
V
µA
0.2
0.8
0.8
−
−
−
−
2.5
2.0
V
V
V
−
−
20
pF
−
−
−
0.3VDDI
VDDI
0.4
V
V
V
VDDA
VDDO
VDDX
IDDE
IDDI
IDDA
IDDO
IDDX
Ptot
Ptot(ps)
note 1
Inputs/outputs D+ and D−
VI
VOH
VOL
ILO
∆VI(dif)
VCM(dif)
VSE(RX)th
CI(TRX)
static DC input voltage
static DC output voltage HIGH
static DC output voltage LOW
high impedance state data line
output leakage current
differential input sensitivity
differential common mode voltage
single-ended receiver threshold
voltage
−0.5
RL = 15 kΩ to ground 2.8
RL = 1.5 kΩ to 3.6 V −
−
transceiver input capacitance
pin to ground
Digital inputs/outputs
VIL
VIH
VOL
LOW-level input voltage
HIGH-level input voltage
LOW-level output voltage
−
0.7VDDI
−
VOH
ILI
Ci
HIGH-level output voltage
input leakage current
VDDI − 0.4 −
−
−
−
1
V
µA
−
5
pF
1998 Oct 06
input capacitance
pin to ground
27
−
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
SYMBOL
PARAMETER
UDA1331H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Filter stream DAC
Vref
Vo(cm)
Ro
reference voltage
common mode output voltage
output resistance at pins VOUTL
and VOUTR
−
−
−
0.5VDDA −
0.5VDDA −
11
−
V
V
Ω
Ro(L)
Co(L)
output load resistance
output load capacitance
2.0
−
−
−
kΩ
pF
−
50
Notes
1. This value depends strongly on the application. The specified value is the typical value obtained using the application
as given in Fig.10.
2. At start-up of the oscillator.
1998 Oct 06
28
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
AC CHARACTERISTICS
VDD = 3.3 V; VSS = 0 V; Tamb = 25 °C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Driver characteristics D+ and D− (full-speed mode)
tr
rise time
CL = 50 pF
4
−
20
ns
tf
fall time
CL = 50 pF
4
−
20
ns
trf(m)
matching rise/fall time (tr/tf)
90
−
110
%
Vcr
output signal crossover voltage
1.3
−
2.0
V
R(o)driver
driver output resistance
28
−
43
Ω
steady-state drive
Data source timings D+ and D− (full-speed mode)
fi(sample)
audio sample input frequency
5
−
55
kHz
ffs(D)
full-speed data rate
11.97
12.00
12.03
Mbits/s
tfr
frame interval
0.9995
1.0000
1.0005
ms
tJ1(dif)
source differential jitter to next
transition
−3.5
0.0
+3.5
ns
tJ2(dif)
source differential jitter for paired
transitions
−4.0
0.0
+4.0
ns
tW(EOP)
source End Of Packet (EOP) width
160
−
175
ns
tEOP(dif)
differential to EOP transition skew
−2.0
−
+5.0
ns
tJR1
receiver data jitter tolerance to next
transition
−18.5
0.0
+18.5
ns
tJR2
receiver data jitter tolerance for
paired transitions
−9.0
0.0
+9.0
ns
tEOPR1
EOP width at receiver must reject as
EOP
40
−
−
ns
tEOPR2
EOP width at receiver must accept
as EOP
82
−
−
ns
Serial input/output data timing; see Fig.7
fclk(sys)
system clock frequency
−
12
−
MHz
fi(WS)
word select input frequency
5
−
55
kHz
tr
rise time
−
−
20
ns
tf
fall time
−
−
20
ns
tBCK(H)
bit clock HIGH time
55
−
−
ns
tBCK(L)
bit clock LOW time
55
−
−
ns
ts;DAT
data set-up time
10
−
−
ns
th;DAT
data hold time
20
−
−
ns
ts;WS
word select set-up time
20
−
−
ns
th;WS
word select hold time
10
−
−
ns
1998 Oct 06
29
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
SYMBOL
PARAMETER
UDA1331H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SDA and SCL lines (standard I2C-bus); see Fig.5
fSCL
SCL clock frequency
0
−
100
kHz
tBUF
bus free time between a STOP
and START condition
4.7
−
−
µs
tHD;STA
hold time (repeated) START
condition
4.0
−
−
µs
tLOW
SCL LOW time
4.7
−
−
µs
tHIGH
SCL HIGH time
4.0
−
−
µs
tSU;STA
set-up time for a repeated START
condition
4.7
−
−
µs
tSU;STO
set-up time for a STOP condition
4.0
−
−
µs
tHD;DAT
data hold time
5.0
−
0.9
µs
tSU;DAT
data set-up time
250
−
−
ns
tr
rise time of both SDA and SCL
signals
−
−
1000
ns
tf
fall time of both SDA and SCL
signals
−
−
300
ns
CL(bus)
load capacitance for each bus line
−
−
400
pF
Oscillator; note 1
fosc
oscillator frequency
−
48
−
MHz
δ
duty factor
−
50
−
%
gm
transconductance
13.5
23.0
30.5
mS
Ro
output resistance
450
700
1450
Ω
Ci(XTAL1)
parasitic input capacitance at XTAL1
10
11
12
pF
Ci(XTAL2)
parasitic input capacitance at XTAL2
4.5
5.0
5.5
pF
Istart
start current
4.3
8.8
15.0
mA
5Cref
−
−
ms
16
−
−
bits
Power-on reset
tsu(POR)
power-on reset set-up time
notes 2 and 3
Filter Stream DAC (FSDAC)
RES
resolution
Vo(FS)(rms)
full-scale output voltage
(RMS value)
VDD = 3.3 V
−
0.66
−
V
SVRR
supply voltage ripple rejection of
VDDA and VDDO
fripple = 1 kHz;
Vripple(p-p) = 0.1 V
−
60
−
dB
∆Vo
channel unbalance
maximum volume
−
0.03
−
dB
αct
crosstalk between channels
RL = 5 kΩ
−
95
−
dB
1998 Oct 06
30
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
SYMBOL
PARAMETER
(THD + N)/S total harmonic distortion-plus-noise
to signal ratio
UDA1331H
CONDITIONS
at input signal of
1 kHz (−60 dB)
signal-to-noise ratio at bipolar zero
TYP.
MAX.
UNIT
fs = 44.1 kHz;
RL = 5 kΩ
at input signal of
1 kHz (0 dB)
S/Nbz
MIN.
A-weighted at
code 0000H
−
−90(4)
−80
dB
−
0.0032
0.01
%
−
−30(4)
−20
dB
−
3.2
10
%
90
95
−
dBA
Notes
1. A 3rd overtone crystal of 48 MHz must be used in combination with a filter connected to the oscillator output (XTAL2),
(L = 1.5 µH ±10%; C = 10 nF ±10%). The series resistance of the crystal must be below 60 Ω. Cxtal1 = 4.7 pF ±10%;
Cxtal2 = 12 pF ±10%).
2. Strongly depends on the external decoupling capacitor connected to Vref.
3. Use for calculation of the power-on reset set-up time the Cref value in µF.
4. The audio information from the USB interface is fed directly to the ADAC.
APPLICATION INFORMATION
The UDA1331H can only be used in combination with an external (E)PROM. This (E)PROM can be connected to the
port pins (P0 and P2) of the UDA1331H and must contain the firmware for the microcontroller. The UDA1331H will be
delivered with standard USB compliant firmware.
The I2C-bus EEPROM is optional and can be used to configure client specific configurations and descriptors.
More information about the firmware, descriptors and configurations can be obtained from several application notes.
1998 Oct 06
31
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
APPLICATION DIAGRAM
+VA
handbook, full pagewidth
R15
1Ω
C8
47 µF
(16 V)
C14
100 nF
(63 V)
VSSA
44
GP0/BCKI
BCKI
digital
input
GP5/WSI
WSI
GP1/DI
DI
VDDA
45
64
2
7
+VC
L9
P5
1
2
3
4
1
2
3
4
R9
1.5 kΩ
8
R14
7
6
5
C26
10 nF
(50 V)
C27
D−
22 Ω
R13
C4
22 pF
(63 V)
C5
22 pF
(63 V)
D+
22 Ω
17
20
10 nF
(50 V)
C7
10 nF
(63 V)
L10
XTAL2
1.5 µH
38
UDA1331H
C6
12 pF
(63 V)
X1
48 MHz
C13
XTAL1
37
4.7 pF
(50 V)
VA(ext)(1)
VD(ext)(1)
L15
+VA
BLM32A07
L14
+VC
BLM32A07
L16
BLM32A07
C1
100 µF
(16 V)
C2
100 µF
(16 V)
+VD
C3
100 µF
(16 V)
GND
29
25
VSSI
C16
(1) BLM32A07.
(2) VD(ext) can be connected to 5 V (max) (5 V tolerant I/O).
MBK531
30
VDDI
100 nF
(63 V)
C15
L11
BLM32A07
100 nF
(63 V)
1Ω
R16
+VC
Fig.9 Application diagram (continued in Fig.10).
1998 Oct 06
32
32
VSSE
C18
100 nF
(63 V)
C17
100 nF
(63 V)
VDDE
L12
BLM32A07
1Ω
R17
+VD
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
handbook, full pagewidth
56
57
58
59
60
62
63
5
9
P0.0
D7
P0.1
D6
P0.2
D5
P0.3
D4
P0.4
D3
P0.5
D2
P0.6
D1
P0.7
D0
ALE
LE
18
19
17
16
14
15
13
12
8
9
D3
74HCT373D
7
4
OE
6
5
3
2
11
20
1
10
Q7
A0
Q6
A1
Q5
A2
Q4
A3
Q3
A4
Q2
A5
Q1
A6
Q0
A7
VCC
C24
GND
A8
12
18
19
21
22
8
6
11
9
12
8
13
7
15
6
16
5
17
4
18
3
19
D2
A9
24 EEPM27128
+VD
100 nF
(50 V)
A10
A11
11
10
A12
P2.0
A13
P2.1
OE
P2.2
CE
P2.3
PGM
P2.4
VPP
P2.5
PSEN
21
2
26
22
20
27
1
R8
1Ω
(external ROM)
A0
C23
100 nF
(63 V)
1
A1
2
A2
UDA1331H
3
VSS
8
D4
PCX8582X-2
4
7
6
5
VDD
PTC
4.7 kΩ
+VD
SCL
SDA
R6
10 kΩ
R7
10 kΩ
P8
4
3
42
SDA
1
SCL
Vref
2
C22
100 nF
(63 V)
SDA
SCL
(I2C-bus)
C12
47 µF
(16 V)
C10
46
53
47 µF
(16 V)
VOUTR
audio
output
VOUTL
C11
47 µF
(16 V)
14
13
10
61
55
15
49
51
VSSO
36
VDDO
VSSX
100 nF
(63 V)
100 nF
(63 V)
C9
C28
+VA
WSO
GP2/DO
digital
output
DO
RTCB
TC
SHTCB
VDDX
C21
1Ω
R18
BCKO
GP3/WSO
39
C19
47 µF
(16 V)
GP4/BCKO
100 nF
(63 V)
L13
BLM32A07
1Ω
R19
+VC
MBK532
(1) BLM32A07.
Fig.10 Application diagram (continued from Fig.9).
1998 Oct 06
33
O2
O3
O4
O5
O6
O7
28
VCC
C25
23
R20
+VD
O1
25
+VD
EA
O0
14
GND
+VD
100 nF
(50 V)
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
PACKAGE OUTLINE
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
c
y
X
51
A
33
52
32
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
L
20
64
detail X
19
1
ZD
w M
bp
e
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
3.20
0.25
0.05
2.90
2.65
0.25
0.50
0.35
0.25
0.14
20.1
19.9
14.1
13.9
1
24.2
23.6
18.2
17.6
1.95
1.0
0.6
0.2
0.2
0.1
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-02-04
97-08-01
SOT319-2
1998 Oct 06
EUROPEAN
PROJECTION
34
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Reflow soldering
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Oct 06
35
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Oct 06
36
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
NOTES
1998 Oct 06
37
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
NOTES
1998 Oct 06
38
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Peripheral (APP)
UDA1331H
NOTES
1998 Oct 06
39
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For all other countries apply to: Philips Semiconductors,
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545102/750/03/pp40
Date of release: 1998 Oct 06
Document order number:
9397 750 04263