INTEGRATED CIRCUITS DATA SHEET UDA1345TS Economy audio CODEC Preliminary specification Supersedes data of 1999 Dec 02 File under Integrated Circuits, IC01 2000 Apr 18 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS FEATURES General • Low power consumption • 2.4 V to 3.6 V power supply range with 3.0 V typical • 5 V tolerant TTL compatible digital inputs • 256, 384 and 512fs system clock • Supports sampling frequencies from 8 to 100 kHz • Non-inverting ADC plus integrated high-pass filter to cancel DC offset Advanced audio configuration • Stereo single-ended input configuration • The ADC supports 2 V (RMS) input signals • Overload detector for easy record level control • Stereo line output (under microcontroller volume control), no post filter required • Separate power control for ADC and DAC • High linearity, dynamic range and low distortion. • Integrated digital interpolation filter plus non-inverting DAC GENERAL DESCRIPTION • Functions controllable either by L3 microcontroller interface or via static pins The UDA1345TS is a single-chip stereo Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with signal processing features employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording and playback functions. • The UDA1345TS is pin and function compatible with the UDA1344TS • Small package size (SSOP28). Multiple format input interface • I2S-bus, MSB-justified up to 24 bits and LSB-justified 16, 18 and 20 bits format compatible The UDA1345TS supports the I2S-bus data format with word lengths of up to 24 bits, the MSB justified data format with word lengths of up to 20 bits and the LSB justified serial data format with word lengths of 16, 18 and 20 bits. The UDA1345TS also supports three combined data formats with MSB justified data output and LSB 16, 18 and 20 bits data input. • Three combined data formats with MSB data output and LSB 16, 18 and 20 bits data input • 1fs input and output format data rate. DAC digital sound processing The sound processing features of the UDA1345TS can only be used in L3 microcontroller mode: The UDA1345TS can be used either with static pin control or under L3 microcontroller interface. In L3 mode the UDA1345TS has basic sound features in playback mode such as de-emphasis, volume control and soft mute. • Digital dB-linear volume control (low microcontroller load) via L3 microcontroller with 1 dB steps • Digital de-emphasis for 32, 44.1 and 48 kHz • Soft mute via cosine roll-off (in 1024 samples). Note: in contrast to the UDA1344TS, the UDA1345TS does not have bass-boost and treble. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UDA1345TS 2000 Apr 18 SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm 2 VERSION SOT341-1 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA(ADC) VDDA(DAC) VDDD IDDA(ADC) ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current IDDA(DAC) DAC analog supply current IDDO(DAC) DAC operational amplifier supply current IDDD digital supply current Tamb ambient temperature 2.4 2.4 2.4 operating mode − ADC power-down − operating mode − DAC power-down − operating mode − DAC power-down − operating mode − ADC and DAC power-down − −40 3.0 3.0 3.0 10 100 4 50 2.5 200 5 300 − 3.6 3.6 3.6 − − − − − − − − +85 V V V mA µA mA µA mA µA mA µA °C − 1.0 − V − − −85 −80 −80 −75 dB dB − − −36 −34 −30 −30 dB dB 90 90 − 96 94 100 − − − dB dB dB − 900 − mV − − −85 −80 −80 −71 dB dB − − − −37 −35 100 −30 −30 − dB dB dB 90 90 100 98 − − dB dB Analog-to-digital converter Vi(rms) (THD + N)/S S/N αcs input voltage (RMS value) total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio notes 1 and 2 at 0 dB fs = 44.1 kHz fs = 96 kHz at −60 dB; A-weighted fs = 44.1 kHz fs = 96 kHz Vi = 0 V; A-weighted fs = 44.1 kHz fs = 96 kHz channel separation Digital-to-analog converter Vo(rms) (THD + N)/S αcs S/N 2000 Apr 18 output voltage (RMS value) total harmonic distortion plus noise-to-signal ratio channel separation signal-to-noise ratio note 3 at 0 dB fs = 44.1 kHz fs = 96 kHz at −60 dB; A-weighted fs = 44.1 kHz fs = 96 kHz code = 0; A-weighted fs = 44.1 kHz fs = 96 kHz 3 Philips Semiconductors Preliminary specification Economy audio CODEC SYMBOL UDA1345TS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Power performance PADDA PDA PAD PPD power consumption in record and playback mode power consumption in playback only mode power consumption in record only mode power consumption in power-down mode − 64 − mW − 36 − mW − 46 − mW − 2.0 − mW Notes 1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor. 2. The input voltage to the ADC scales proportionally with the power supply voltage. 3. The output voltage of the DAC scales proportionally with the power supply voltage. 2000 Apr 18 4 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS BLOCK DIAGRAM VDDA(ADC) VSSA(ADC) handbook, full pagewidth 2 VINL 3 VADCP 1 VADCN 7 Vref(A) 6 0 dB/6 dB SWITCH 4 5 0 dB/6 dB SWITCH ADC ADC 8 VDDD VSSD DATAO BCK WS DATAI 21 DECIMATION FILTER 10 20 11 MC1 MC2 MP5 DC-CANCELLATION FILTER 18 13 16 L3-BUS INTERFACE DIGITAL INTERFACE 17 14 15 19 12 MP1 VINR 9 MP2 MP3 MP4 SYSCLK INTERPOLATION FILTER UDA1345TS NOISE SHAPER DAC VOUTL DAC 26 24 25 27 VDDO VSSO 23 VDDA(DAC) 22 VSSA(DAC) Fig.1 Block diagram. 2000 Apr 18 5 28 Vref(D) VOUTR MGS875 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS PINNING SYMBOL PIN TYPE DESCRIPTION VSSA(ADC) 1 analog ground pad ADC analog ground VDDA(ADC) 2 analog supply pad ADC analog supply voltage VINL 3 analog input pad ADC input left Vref(A) 4 analog pad ADC reference voltage VINR 5 analog input pad ADC input right VADCN 6 analog pad ADC negative reference voltage VADCP 7 analog pad ADC positive reference voltage MC1 8 5 V tolerant digital input pad with internal pull-down pad mode control 1 (pull-down) MP1 9 5 V tolerant slew rate controlled digital output pad multi purpose pin 1 VDDD 10 digital supply pad digital supply voltage VSSD 11 digital ground pad digital ground SYSCLK 12 5 V tolerant digital Schmitt triggered input pad system clock 256, 384 or 512fs MP2 13 3-level input pad multi purpose pin 2 MP3 14 5 V tolerant digital Schmitt triggered input pad multi purpose pin 3 MP4 15 3-level input pad multi purpose pin 4 BCK 16 5 V tolerant digital Schmitt triggered input pad bit clock input WS 17 5 V tolerant digital Schmitt triggered input pad word select input DATAO 18 5 V tolerant slew rate controlled digital output pad data output DATAI 19 5 V tolerant digital Schmitt triggered input pad data input MP5 20 5 V tolerant digital Schmitt triggered input pad multi purpose pin 5 (pull down) MC2 21 5 V tolerant digital input pad with internal pull-down pad mode control 2 (pull-down) VSSA(DAC) 22 analog ground pad DAC analog ground VDDA(DAC) 23 analog supply pad DAC analog supply voltage VOUTR 24 analog output pad DAC output right VDDO 25 analog supply pad operational amplifier supply voltage VOUTL 26 analog output pad DAC output left VSSO 27 analog ground pad operational amplifier ground Vref(D) 28 analog pad DAC reference voltage 2000 Apr 18 6 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS Analog-to-Digital Converter (ADC) The stereo ADC of the UDA1345TS consists of two 5th-order Sigma-Delta modulators. They have a modified Ritchie-coder architecture in a differential switched capacitor implementation. The oversampling ratio is 64. handbook, halfpage VSSA(ADC) 1 28 Vref(D) VDDA(ADC) 2 27 VSSO 26 VOUTL VINL 3 Vref(A) 4 VINR 5 Analog front-end 24 VOUTR The analog front-end is equipped with a selectable 0 dB or 6 dB gain block (the pin to select this mode is given in Section “L3 microcontroller mode”). This block can be used in applications in which both 1 V (RMS) and 2 V (RMS) input signals can be input to the UDA1345TS. 23 VDDA(DAC) VADCN 6 VADCP 7 25 VDDO UDA1345TS 22 VSSA(DAC) MC1 8 21 MC2 MP1 9 20 MP5 VDDD 10 19 DATAI VSSD 11 18 DATAO In applications in which a 2 V (RMS) input signal is used, a 12 kΩ resistor must be used in series with the input of the ADC. This forms a voltage divider together with the internal ADC resistor and ensures that only 1 V (RMS) maximum is input to the IC. Using this application for a 2 V (RMS) input signal, the switch must be set to 0 dB. When a 1 V (RMS) input signal is input to the ADC in the same application, the gain switch must be set to 6 dB. 17 WS SYSCLK 12 16 BCK MP2 13 MP3 14 15 MP4 An overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in Table 1; the power supply voltage is assumed to be 3 V. MGS876 Fig.2 Pin configuration. Table 1 FUNCTIONAL DESCRIPTION INPUT GAIN SWITCH MAXIMUM INPUT VOLTAGE Present 0 dB 2 V (RMS) Present 6 dB 1 V (RMS) Absent 0 dB 1 V (RMS) Absent 6 dB 0.5 V (RMS) RESISTOR (12 kΩ) The UDA1345TS accommodates slave mode only, this means that in all applications the system devices must provide the system clocks (being the system clock itself and the digital audio interface signals). The system clock must be locked in frequency to the audio digital interface input signals. The BCK clock can be up to 128fs, or in other words the BCK frequency is 128 times the Word Select (WS) frequency or less: fBCK = < 128 × fWS. Decimation filter (ADC) The decimation from 64fs to 1fs is performed in two stages. Important: the WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital I/O data interface. sin x The first stage realizes a 4th-order ------------ characteristic. x This filter decreases the sample rate by 8. The second stage consists of 2 half-band filters and a recursive filter, each decimating by a factor of 2. Note: the sampling frequency range is from 5 to 100 kHz, however for the 512fs clock mode the sampling range is from 5 to 55 kHz. 2000 Apr 18 Application modes using input gain stage 7 Philips Semiconductors Preliminary specification Economy audio CODEC Table 2 UDA1345TS The Filter Stream DAC (FSDAC) Digital decimation filter characteristics ITEM CONDITIONS VALUE (dB) 0 − 0.45fs ±0.05 >0.55fs −60 Pass-band ripple Stop band Dynamic range Overall gain when a 0 dB signal is input to ADC to digital output 0 − 0.45fs 114 DC −1.16 The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. Note: it should be noted that the digital output level is inversely proportional to the ADC analog power supply. This means that with a constant analog input level and increasing power supply the digital output level will decrease proportionally. The output voltage of the FSDAC is scaled proportionally with the power supply voltage. Power control In the event that the DAC is powered-up or powered-down, a cosine roll-off mute will be performed (when powering down) or a cosine roll-up de-mute (when powering up) will be performed. This is in order to prevent clicks when powering up or down. This power-on/off mute takes 32 × 4 = 128 samples. Interpolation filter (DAC) The digital filter interpolates from 1 to 128fs by means of a cascade of a recursive filter and an FIR filter. Table 3 Digital interpolation filter characteristics ITEM Passband ripple Stopband Dynamic range Gain CONDITIONS VALUE (dB) 0 − 0.45fs ±0.03 >0.55fs −65 0 − 0.45fs 116.5 DC −3.5 L3MODE or static pin control The UDA1345TS can be used under L3 microcontroller interface mode or under static pin control. The mode can be set via the Mode Control (MC) pins MC1 (pin 8) and MC2 (pin 21). The function of these pins is given in Table 4. Double speed Table 4 Mode Control pins MC1 and MC2 SInce the device supports a sampling range of 8 to 100 kHz, the device can support double speed (e.g. for 44.1 kHz and 48 kHz sampling frequency) by just doubling the system speed. In double speed all features are available. L3MODE LOW LOW Test modes LOW HIGH HIGH LOW Noise shaper (DAC) Static pin mode HIGH HIGH MODE The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. 2000 Apr 18 MC2 MC1 Important: in L3MODE the UDA1345TS is completely pin and function compatible with the UDA1340M and the UDA1344TS. Note: the UDA1345TS does NOT support bass-boost and treble. 8 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS L3 microcontroller mode OVERLOAD DETECTION (ADC) The UDA1345TS is set to the L3 microcontroller mode by setting both MC1 (pin 8) and MC2 (pin 21) LOW. In practice the output is used to indicate whenever the output data, in either the left or right channel, is greater than −1 dB (the actual figure is −1.16 dB) of the maximum possible digital swing. When this condition is detected the OVERFL output is forced HIGH for at least 512fs cycles (11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement. The definition of the control registers is given in Section “L3 interface”. PINNING DEFINITION The pinning definition under L3 microcontroller interface is given in Table 5. Table 5 DC CANCELLATION FILTER (ADC) An optional IIR high-pass filter is provided to remove unwanted DC components. The operation is selected by the microcontroller via the L3-bus. The filter characteristics are given in Table 6. Pinning definition under L3 control SYMBOL PIN DESCRIPTION MP1 9 OVERFL output MP2 13 L3MODE input MP3 14 L3CLOCK input MP4 15 L3DATA input MP5 20 ADC 1 or 2 V (RMS) input control Table 6 DC cancellation filter characteristics ITEM CONDITIONS VALUE (dB) Pass-band ripple none Pass-band gain 0 SYSTEM CLOCK Droop at 0.00045fs Under L3 control the options are 256, 384 and 512fs. Attenuation at DC Dynamic range 0.031 at 0.00000036fs >40 0 − 0.45fs >110 MULTIPLE FORMAT INPUT/OUTPUT INTERFACE Static pin mode The UDA1345TS supports the following data input/output formats under L3 control: • I2S-bus The UDA1345TS is set to static pin control mode by setting both MC1 (pin 8) and MC2 (pin 21) HIGH. with data word length of up to 24 bits • MSB-justified serial format with data word length of up to 20 bits PINNING DEFINITION • LSB-justified serial format with data word lengths of 16, 18 or 20 bits The pinning definition under static pin control is given in Table 7. • Three combined data formats with MSB data output and LSB 16, 18 and 20 bits data input. Table 7 Pinning definition for static pin control SYMBOL The formats are illustrated in Fig.3. Left and right data channel words are time multiplexed. PIN DESCRIPTION MP1 9 data input/output setting MP2 13 3-level pin controlling de-emphasis and mute The UDA1345TS supports a 2 V (RMS) input using a series resistor of 12 kΩ as described in Section “Analog front-end”. In L3 microcontroller mode, the gain can be selected via pin MP5. MP3 14 256fs or 384fs system clock MP4 15 3-level pin to control ADC power mode and 1 V (RMS) or 2 V (RMS) input When MP5 is set LOW, 0 dB gain is selected. When MP5 is set HIGH, 6 dB gain is selected. MP5 20 data input/output setting ADC INPUT VOLTAGE CONTROL 2000 Apr 18 9 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS Table 10 Data format settings under static pin control SYSTEM CLOCK Under static pin control the options are 256fs and 384fs. With pin MP3 (pin 14) the mode can be set as is given in Table 8. Table 8 INPUT FORMAT System clock settings under static pin mode MODE MP3 256fs system clock LOW 384fs system clock HIGH MP1 MP5 MSB mode LOW LOW I2S-bus LOW HIGH MSB output LSB 20 input HIGH LOW MSB output LSB 16 input HIGH HIGH MUTE AND DE-EMPHASIS The formats are illustrated in Fig.3. Left and right data channel words are time multiplexed. Under static pin control via MP2 de-emphasis and mute can be selected for the playback path. The definition of the MP2 pin is given in Table 9. ADC INPUT VOLTAGE CONTROL Table 9 The UDA1345TS supports a 2 V (RMS) input using a series resistor as described in Section “Analog front-end”. Settings for pin MP2 MODE MP2 No de-emphasis and mute LOW De-emphasis 44.1 kHz Muted In static pin mode the 3-level pin MP4 (pin 15) is used to select 0 or 6 dB gain mode. When MP4 is set LOW the ADC is powered-down. When MP4 is set to half the power supply voltage, then 6 dB gain is selected, and when MP4 is set HIGH then 0 dB gain is selected. 0.5VDDD HIGH Table 11 MP4 mode settings (static mode) MULTIPLE FORMAT INPUT/OUTPUT INTERFACE MODE MP4 The data input/output formats supported under static pin control are as follows: ADC power-down mode LOW • with data word length of up to 24 bits 6 dB gain mode MID • MSB-justified serial format with data word length of up to 24 bits 0 dB gain mode HIGH I2S-bus • Two combined data formats with MSB data output and LSB 16 and 20 bits data input. The data formats can be selected using pins MP1 (pin 9) and MP5 (pin 20) as given in Table 10. 2000 Apr 18 10 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... RIGHT >=8 3 1 2 3 BCK DATA MSB B2 LSB MSB B2 LSB MSB INPUT FORMAT LEFT WS 1 2 >=8 I2S-BUS RIGHT >=8 3 1 2 LSB MSB B2 >=8 3 BCK DATA MSB B2 LSB MSB Philips Semiconductors 2 Economy audio CODEC 1 handbook, full pagewidth 2000 Apr 18 LEFT WS B2 MSB-JUSTIFIED FORMAT WS RIGHT LEFT 16 15 2 1 16 B15 LSB MSB 15 2 1 BCK 11 MSB DATA B2 B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS WS RIGHT LEFT 18 17 16 15 2 1 18 B17 LSB MSB 17 16 15 2 1 B17 LSB 2 1 BCK DATA MSB B2 B3 B4 B2 B3 B4 LSB-JUSTIFIED FORMAT 18 BITS LEFT 19 18 RIGHT 17 16 15 2 1 20 B19 LSB MSB 19 18 17 16 15 BCK DATA MSB B2 B3 B4 B5 B6 B2 B3 B4 B5 B6 B19 LSB MGG841 LSB-JUSTIFIED FORMAT 20 BITS Fig.3 Serial interface formats. UDA1345TS 20 Preliminary specification WS Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS Table 12 Selection of data transfer L3 interface The UDA1345TS has a microcontroller input mode. In the microcontroller mode, all of the digital sound processing features and the system controlling features can be controlled by the microcontroller. The controllable features are: • System clock frequency • Data input format • Power control • DC filtering BIT 0 TRANSFER 0 0 DATA (volume, de-emphasis, mute, and power control) 0 1 not used 1 0 STATUS (system clock frequency, data input format and DC filter) 1 1 not used Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the UDA1345TS is 000101 (bit 7 to bit 2). In the event that the UDA1345TS receives a different address, it will deselect its microcontroller interface logic. • De-emphasis • Volume • Mute. The exchange of data and control information between the microcontroller and the UDA1345TS is accomplished through a serial hardware interface comprising the following pins: DATA TRANSFER MODE The selection preformed in the address mode remains active during subsequent data transfers, until the UDA1345TS receives a new address command. The fundamental timing of data transfers is essentially the same as in the address mode, shown in Fig.4. The maximum input clock and data rate is 128fs. All transfers are byte wise, i.e. they are based on groups of 8 bits. Data will be stored in the UDA1345TS after the eighth bit of a byte has been received. A multibyte transfer is illustrated in Fig.6. • L3DATA: microcontroller interface data line • L3MODE: microcontroller interface mode line • L3CLOCK: microcontroller interface clock line. Information transfer via the microcontroller bus is LSB first, and is organized in accordance with the so called ‘L3’ format, in which two different modes of operation can be distinguished; address mode and data transfer mode (see Figs 4 and 5). Programming the sound processing and other features The address mode is required to select a device communicating via the L3-bus and to define the destination register set for the data transfer mode. Data transfer for the UDA1345TS can only be in one direction: for the UDA1345TS, data can only be written to the device. The feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred, being DATA or STATUS. This is performed in the address mode, bit 1 and bit 0 (see Table 12). The second selection is performed by the 2 MSBs of the data byte (bit 7 and bit 6). The other bits in the data byte (bit 5 to bit 0) are the values that are placed in the selected registers. Important: since the UDA1345TS does not have a Power-up reset circuit, after power up the L3 interface registers MUST be initialized. ADDRESS MODE When the data transfer of type DATA is selected, the features Volume, De-emphasis, Mute and Power control can be controlled. When the data transfer of type STATUS is selected, the features system clock frequency, data input format and DC filter can be controlled. The address mode is used to select a device for subsequent data transfer and to define the destination register set (DATA or STATUS). The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 data bits. The fundamental timing is shown in Fig.4. Data bits 0 and 1 indicate the type of subsequent data transfer as given in Table 12. 2000 Apr 18 BIT 1 12 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS handbook, full pagewidth L3MODE t s(MA) t h(MA) tLC tHC t s(MA) t h(MA) L3CLOCK Tcy t s(DAT) t h(DAT) BIT 7 BIT 0 L3DATA MGL883 Fig.4 Timing address mode. handbook, full pagewidth thalt thalt L3MODE tLC t s(MT) Tcy tHC t h(MT) L3CLOCK t h(DAT) L3DATA write t s(DAT) BIT 0 t h(DAT) BIT 7 MGL884 Fig.5 Timing for data transfer mode. 2000 Apr 18 13 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS thalt handbook, full pagewidth L3MODE L3CLOCK L3DATA address data byte #1 data byte #2 address MGD018 Fig.6 Multibyte transfer. Table 13 Data transfer of type status LAST IN TIME FIRST IN TIME REGISTER SELECTED BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 SC1 SC0 IF2 IF1 IF0 DC System Clock frequency (5 : 4); data Input Format (3 : 1); DC-filter Table 14 Data transfer of type data LAST IN TIME FIRST IN TIME REGISTER SELECTED BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 VC5 VC4 VC3 VC2 VC1 VC0 0 1 0 0 0 0 0 0 not used 1 0 0 DE1 DE0 MT 0 0 De-Emphasis (4 : 3); MuTe 1 1 0 0 0 0 PC1 PC0 Volume Control (5 : 0) Power Control (1 : 0) System clock frequency A 2-bit value (SC1 and SC0) to select the used external clock frequency (see Table 15). 2000 Apr 18 14 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS Table 18 Volume settings Table 15 System clock frequency settings SC1 SC0 FUNCTION VC5 VC4 VC3 VC2 VC1 VC0 0 0 512fs 0 0 0 0 0 0 0 0 1 384fs 0 0 0 0 0 1 0 1 0 256fs 0 0 0 0 1 0 −1 1 1 not used 0 0 0 0 1 1 −2 : : : : : : : Data input format VOLUME (dB) 1 1 0 0 1 1 −50 A 3-bit value (IF2 to IF0) to select the used data format (see Table 16). 1 1 0 1 0 0 −52 1 1 0 0 0 1 −54 Table 16 Data input format settings 1 1 0 0 1 0 −57 1 1 0 1 1 1 −60 1 1 1 0 0 0 −66 1 1 1 0 0 1 −∞ IF2 IF1 IF0 FUNCTION 0 0 0 I2S-bus 0 0 1 LSB-justified; 16 bits 0 1 0 LSB-justified; 18 bits 0 1 1 LSB-justified; 20 bits 1 0 0 MSB-justified De-emphasis 1 0 1 MSB-justified output/ LSB-justified 16 bits input A 2-bit value to enable the digital de-emphasis filter. 1 1 0 MSB-justified output/ LSB-justified 18 bits input Table 19 De-emphasis settings 1 1 1 MSB-justified output/ LSB-justified 20 bits input : : : : : : : 1 1 1 1 1 1 −∞ DE1 DE0 0 0 no de-emphasis 0 1 de-emphasis; 32 kHz DC filter 1 0 de-emphasis; 44.1 kHz A 1-bit value to enable the digital DC filter (see Table 17). 1 1 de-emphasis; 48 kHz Mute Table 17 DC filtering DC FUNCTION A 1-bit value to enable the digital DAC mute (playback). FUNCTION 0 no DC filtering 1 DC filtering Table 20 DAC mute MT FUNCTION Volume control 0 no muting A 6-bit value to program the left and right channel volume attenuation (VC5 to VC0). The range is 0 dB to −∞ dB in steps of 1 dB (see Table 18). 1 muting 2000 Apr 18 15 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS Power control A 2-bit value to disable the ADC and/or DAC to reduce power consumption. Table 21 Power control settings FUNCTION PC1 PC0 ADC DAC 0 0 off off 0 1 off on 1 0 on off 1 1 on on LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages referenced to ground; VDDD = VDDA = VDDO = 3 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER VDDD Txtal(max) Tstg Tamb Ves Ilu(prot) digital supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling latch-up protection current Isc(DAC) short-circuit current of DAC CONDITIONS MIN. MAX. − 5.0 − 150 −65 +125 −40 +85 according to JEDEC II specification Tamb = 125 °C; − 200 VDD = 3.6 V Tamb = 0 °C; VDD = 3 V; note 2 − 450 output short-circuited to VSSA(DAC) − 325 output short-circuited to VDDA(DAC) note 1 UNIT V °C °C °C mA mA mA Notes 1. All VDD and VSS connections must be made to the same power supply. 2. DAC operation after short-circuiting cannot be warranted. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2000 Apr 18 PARAMETER thermal resistance from junction to ambient CONDITIONS in free air 16 VALUE UNIT 90 K/W Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS DC CHARACTERISTICS VDDD = VDDA = VDDO = 3.0 V; fs = 44.1 kHz; Tamb = 25 °C; RL = 5 kΩ; note 1; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA(ADC) VDDA(DAC) VDDD IDDA(ADC) ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current IDDA(DAC) DAC analog supply current IDDO(DAC) DAC operational amplifier supply current IDDD digital supply current operating mode ADC power-down operating mode DAC power-down operating mode DAC power-down operating mode ADC and DAC power-down 2.4 2.4 2.4 − − − − − − − − 3.0 3.0 3.0 10 100 4 50 2.5 200 5.0 300 3.6 3.6 3.6 − − − − − − − − V V V mA µA mA µA mA µA mA µA 2.0 −0.5 1.3 − − − 5.0 0.8 1.9 V V V 0.9 0.4 − − − − − − 1.35 0.7 10 10 V V µA pF 0.9VDDD 0.4VDDD −0.5 − − − VDDD + 0.5 V 0.6VDDD V +0.5 V Digital input pins (5V tolerant TTL compatible) VIH VIL VIH(th) VIL(th) Vhys ILI Ci HIGH-level input voltage LOW-level input voltage HIGH-level threshold input voltage LOW-level threshold input voltage Schmitt trigger hysteresis voltage input leakage current input capacitance 3-level input pins (MP2; MP4) VIH VIM VIL HIGH-level input voltage MIDDLE-level input voltage LOW-level input voltage Digital output pins VOH VOL HIGH-level output voltage LOW-level output voltage IOH = −2 mA IOL = 2 mA 0.85VDDD − − − − 0.4 V V 0.45VDDA − − − 0.55VDDA − − − V kΩ kΩ pF Analog-to-digital converter Vref(A) Ro(ref) Ri Ci 2000 Apr 18 reference voltage with respect to VSSA Vref(A) reference output resistance input resistance fi = 1 kHz input capacitance 17 0.5VDDA 24 12 20 Philips Semiconductors Preliminary specification Economy audio CODEC SYMBOL PARAMETER UDA1345TS CONDITIONS MIN. TYP. MAX. UNIT 0.45VDDA − − − 0.5VDDA 12.5 0.13 tbf 0.55VDDA − 3.0 − V kΩ Ω mA 3 − − − − 200 kΩ pF Digital-to-analog converter Vref(D) Ro(ref) Ro Io(max) RL CL reference voltage with respect to VSSA Vref(D) reference output resistance DAC output resistance maximum output current (THD + N)/S < 0.1%; RL = 800 Ω load resistance load capacitance note 2 Notes 1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2. When higher capacitive loads must be driven then a 100 Ω resistor must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier. 2000 Apr 18 18 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS AC CHARACTERISTICS (ANALOG) VDDD = VDDA = VDDO = 3.0 V; fi = 1 kHz; fs = 44.1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Analog-to-digital converter input voltage (RMS value) Vi(rms) ∆Vi unbalance between channels (THD + N)/S total harmonic distortion plus noise-to-signal ratio S/N αcs PSRR signal-to-noise ratio channel separation power supply rejection ratio notes 1 and 2 − − 1.0 0.1 − − V dB − − −85 −80 −80 −75 dB dB − − −36 −34 −30 −30 dB dB 90 90 − − 96 94 100 30 − − − − dB dB dB dB − − 900 0.1 − − mV dB − − −85 −80 −80 −71 dB dB − −37 −30 dB − −35 −30 dB at 0 dB fs = 44.1 kHz fs = 96 kHz at −60 dB; A-weighted fs = 44.1 kHz fs = 96 kHz Vi = 0 V; A-weighted fs = 44.1 kHz fs = 96 kHz fripple = 1 kHz; Vripple(p-p) = 1% Digital-to-analog converter output voltage (RMS value) Vo(rms) unbalance between channels ∆Vo (THD + N)/S total harmonic distortion plus noise-to-signal ratio S/N αcs PSRR signal-to-noise ratio note 3 at 0 dB fs = 44.1 kHz fs = 96 kHz at −60 dB; A-weighted fs = 44.1 kHz fs = 96 kHz code = 0; A-weighted fs = 44.1 kHz 90 100 − dB fs = 96 kHz 90 − 98 100 − − dB dB fripple = 1 kHz; Vripple(p-p) = 1% − 60 − dB channel separation power supply rejection ratio Notes 1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor. 2. The input voltage to the ADC scales proportionally with the power supply voltage. 3. The output voltage of the DAC scales proportionally with the power supply voltage. 2000 Apr 18 19 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = VDDO = 2.7 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT System clock timing; see Fig.7 Tsys system clock cycle tCWL fsys LOW-level pulse width tCWH fsys HIGH-level pulse width fsys = 256fs; note 1 39 88 781 ns fsys = 384fs; note 1 26 59 520 ns fsys = 512fs; note 2 36 44 390 ns fsys < 19.2 MHz 0.30Tsys − 0.70Tsys ns fsys ≥ 19.2 MHz 0.40Tsys − 0.60Tsys ns fsys < 19.2 MHz 0.30Tsys − 0.70Tsys ns fsys ≥ 19.2 MHz 0.40Tsys − 0.60Tsys ns tr rise time − − 20 ns tf fall time − − 20 ns Serial input/output data timing; see Fig.8 tBCK bit clock period 1⁄ − − ns tBCKH bit clock HIGH time 34 − − ns tBCKL bit clock LOW time 34 − − ns tr rise time − − 20 ns tf fall time − − 20 ns ts(DATAI) data input set-up time 20 − − ns th(DATAI) data input hold time 0 − − ns td(DATAO−BCK) data output delay time (from BCK falling edge) − − 80 ns td(DATAO−WS) data output delay time (from WS edge) MSB-justified format − − 80 ns th(DATAO) data output hold time 0 − − ns ts(WS) word select set-up time 20 − − ns th(WS) word select hold time 10 − − ns 128fs Address and data transfer mode timing; see Figs 4 and 5 Tcy L3CLOCK cycle time 500 − − ns tHC L3CLOCK HIGH period 250 − − ns tLC L3CLOCK LOW period 250 − − ns ts(MA) L3MODE set-up time address mode 190 − − ns th(MA) L3MODE hold time address mode 190 − − ns ts(MT) L3MODE set-up time data transfer mode 190 − − ns th(MT) L3MODE hold time data transfer mode 190 − − ns 2000 Apr 18 20 Philips Semiconductors Preliminary specification Economy audio CODEC SYMBOL UDA1345TS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT ts(DAT) L3DATA set-up time data transfer mode and address mode 190 − − ns th(DAT) L3DATA hold time data transfer mode and address mode 30 − − ns thalt L3MODE halt time 190 − − ns Notes 1. Sampling range from 5 to 100 kHz is supported, with fs = 44.1 kHz typical. 2. Sampling range from 5 to 55 kHz is supported, with fs = 44.1 kHz typical. t CWH handbook, full pagewidth MGR984 t CWL Tsys Fig.7 System clock timing. handbook, full pagewidth WS tBCKH tr ts(WS) td(DATAO-BCK) th(WS) tf BCK tBCKL Tcy th(DATAO) td(DATAO-WS) DATAO ts(DATAI) th(DATAI) DATAI MGL885 Fig.8 Serial interface timing. 2000 Apr 18 21 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS APPLICATION INFORMATION The application information as given in Fig.9, is an optimum application environment. Simplification is possible at the cost of some performance degradation. The following notes apply: • The capacitors at the output of the DAC can be reduced. It should be noted that the cut-off frequency of the DC filter also changes. • The capacitors at the input of the ADC can also be reduced. It should be noted that the cut-off frequency of the capacitor with the 12 kΩ input resistance of the ADC will also change. VDDA 8LM32A07 R21 1Ω L2 VDDD 8LM32A07 C12 100 µF (16 V) ground C2 C11 100 µF (16 V) R24 R30 SYSCLK 47 Ω DATAO BCK WS DATAI MP1 overload flag left input VDDD R28 10 Ω 10 Ω 100 µF (16 V) C21 C25 100 nF (63 V) 100 nF (63 V) VSSA(ADC) VDDA(ADC) system clock handbook, full pagewidth VDDA L1 3V 2 1 VADCN VADCP 6 7 VSSD VDDD 10 11 12 18 4 C22 100 nF (63 V) 16 17 C1 VINL 9 UDA1345TS 3 47 µF (16 V) X5 C6 MP4 13 28 14 27 25 23 22 VDDO VSSA(DAC) C26 C27 100 nF (63 V) 100 nF (63 V) C7 C10 100 µF (16 V) R25 1Ω 100 µF (16 V) VDDO Fig.9 Application diagram. 22 X2 left output R22 10 kΩ R26 100 Ω X3 right output R27 10 kΩ Vref(D) C23 100 nF (63 V) 15 VSSO R23 100 Ω C8 47 µF (16 V) VINR 5 MP3 2000 Apr 18 VOUTR 47 µF (16 V) MP2 C5 VOUTL 47 µF (16 V) 24 right input C3 47 µF (16 V) 19 26 X4 Vref(A) C4 47 µF (16 V) MGS877 VDDA(DAC) R29 1Ω VDDA Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 2000 Apr 18 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-150 23 o Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS SOLDERING If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 2000 Apr 18 24 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Apr 18 25 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2000 Apr 18 26 Philips Semiconductors Preliminary specification Economy audio CODEC UDA1345TS NOTES 2000 Apr 18 27 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/25/02/pp28 Date of release: 2000 Apr 18 Document order number: 9397 750 07008