74HC4852 Dual 4-channel analog multiplexer/demultiplexer with injection-current effect control Rev. 02 — 30 May 2007 Product data sheet 1. General description The 74HC4852 is a high-speed Si-gate CMOS device and is specified in compliance with JEDEC standard no. 7A. The 74HC4852 is a dual 4-channel analog multiplexer or demultiplexer with common select inputs (S0 and S1). Both multiplexers have a common active LOW enable input (E), four independent inputs/outputs (pins nY0 to nY3) and a common input/output (pin nZ). The device features injection-current effect control, which has excellent value in automotive applications where voltages in excess of the supply voltage are common. With E LOW, two of the eight switches are selected (low impedance ON-state) by S0 and S1. With E HIGH, all switches are in the high-impedance OFF-state, independent of S0 and S1. The injection-current effect control allows signals at disabled analog input channels to exceed the supply voltage without affecting the signal of the enabled analog channel. This eliminates the need for external diode/resistor networks typically used to keep the analog channel signals within the supply-voltage range. 2. Features n Injection-current cross coupling < 1 mV/mA n Wide supply voltage range from 2.0 V to 6.0 V n ESD protection: u HBM JESD22-A114E Class 2 exceeds 2000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Latch-up performance exceeds 100 mA per JESD 78 Class II n Low ON-state resistance: u 400 Ω (typical) at VCC = 2.0 V u 215 Ω (typical) at VCC = 3.0 V u 120 Ω (typical) at VCC = 3.3 V u 76 Ω (typical) at VCC = 4.5 V u 59 Ω (typical) at VCC = 6.0 V 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control 3. Applications n n n n Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating Automotive application 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4852D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC4852PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HC4852BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT763-1 5. Functional diagram 10 9 13 1Z 10 S0 6 1Y0 12 1Y1 14 1Y2 15 0 4× 1 G4 MUX/DMUX 0 3 9 6 S1 E 2Z 1Y3 11 2Y0 1 2Y1 5 2Y2 2 2Y3 4 0 3 1 2 3 0 13 1 2 3 3 Fig 1. Logic symbol 001aag093 5 2 4 12 14 15 11 001aag094 Fig 2. IEC logic symbol 74HC4852_2 Product data sheet 1 © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 2 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control VCC 16 S0 10 1-OF-4 DECODER S1 E 9 6 INJECTION CURRENT CONTROL 13 INJECTION CURRENT CONTROL 12 INJECTION CURRENT CONTROL 14 INJECTION CURRENT CONTROL 15 INJECTION CURRENT CONTROL 11 INJECTION CURRENT CONTROL 1 INJECTION CURRENT CONTROL 5 INJECTION CURRENT CONTROL 2 INJECTION CURRENT CONTROL 4 INJECTION CURRENT CONTROL 3 1Z 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 2Z GND 8 001aag095 Fig 3. Functional diagram 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 3 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control 6. Pinning information 6.1 Pinning 1 terminal 1 index area 74HC4852 16 VCC 2Y0 74HC4852 2Y2 2 15 1Y2 3 14 1Y1 2Y0 1 16 VCC 2Z 2Y2 2 15 1Y2 2Y3 4 13 1Z 2Z 3 14 1Y1 2Y1 5 12 1Y0 2Y3 4 13 1Z E 6 2Y1 5 12 1Y0 n.c. 7 E 6 11 1Y3 n.c. 7 10 S0 GND 8 8 9 S1 S1 11 1Y3 10 S0 GND 9 GND(1) 001aag097 Transparent top view 001aag096 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO16 and TSSOP16 Fig 5. Pin configuration DHVQFN16 6.2 Pin description Table 2. Pin description Symbol Pin Description 2Y0 1 independent input/output 2Y2 2 independent input/output 2Z 3 common input/output 2Y3 4 independent input/output 2Y1 5 independent input/output E 6 enable input (active LOW) n.c. 7 not connected GND 8 ground (0 V) S1 9 select input S0 10 select input 1Y3 11 independent input/output 1Y0 12 independent input/output 1Z 13 common input/output 1Y1 14 independent input/output 1Y2 15 independent input/output VCC 16 positive supply voltage 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 4 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control 7. Functional description Table 3. Function table[1] Input Channel ON E S1 S0 L L L nY0 to nZ L L H nY1 to nZ L H L nY2 to nZ L H H nY3 to nZ H X X - [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Max Unit VCC supply voltage Conditions −0.5 +7.0 V VI input voltage −0.5 VCC + 0.5 V VSW switch voltage enable and disable mode −0.5 VCC + 0.5 V IIK input clamping current VI < 0 V or VI > VCC - ±20 mA ISK switch clamping current VI < 0 V or VI > VCC - ±20 mA ISW switch current VSW = 0 V to VCC - ±25 mA ICC supply current - 50 mA IGND ground current −50 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 500 mW [1] Tamb = −40 °C to +125 °C [1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN16 packages: Ptot derates linearly with 4.5 mW/K above 60 °C. 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 5 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Conditions Min Typ Max Unit supply voltage 2.0 - 6.0 V VI input voltage 0 - VCC V VSW switch voltage 0 - VCC V Tamb ambient temperature −40 - +125 °C ∆t/∆V input transition rise and fall rate VCC = 2.0 V - 6.0 1000 ns/V VCC = 3.0 V - 6.0 800 ns/V VCC = 3.3 V - 6.0 800 ns/V VCC = 4.5 V - 6.0 500 ns/V VCC = 6.0 V - 6.0 400 ns/V Min Typ Max Unit VCC = 2.0 V; ISW = 2 mA - 400 650 Ω VCC = 3.0 V; ISW ≤ 2 mA - 215 330 Ω VCC = 3.3 V; ISW ≤ 2 mA - 120 270 Ω VCC = 4.5 V; ISW ≤ 2 mA - 76 210 Ω VCC = 6.0 V; ISW ≤ 2 mA - 59 195 Ω 10. Static characteristics Table 6. RON resistance For test circuit see Figure 8. Symbol Parameter Conditions Tamb = 25 °C RON(peak) ∆RON ON resistance (peak) ON resistance mismatch between channels VI = VCC to GND; E = VIL VI = 0.5 × VCC; E = VIL VCC = 2.0 V; ISW = 2 mA - 4 10 Ω VCC = 3.0 V; ISW ≤ 2 mA - 2 8 Ω VCC = 3.3 V; ISW ≤ 2 mA - 2 8 Ω VCC = 4.5 V; ISW ≤ 2 mA - 2 8 Ω VCC = 6.0 V; ISW ≤ 2 mA - 3 9 Ω VCC = 2.0 V; ISW = 2 mA - - 670 Ω Tamb = −40 °C to +85 °C RON(peak) ON resistance (peak) VI = VCC to GND; E = VIL VCC = 3.0 V; ISW ≤ 2 mA - - 360 Ω VCC = 3.3 V; ISW ≤ 2 mA - - 305 Ω VCC = 4.5 V; ISW ≤ 2 mA - - 240 Ω VCC = 6.0 V; ISW ≤ 2 mA - - 220 Ω 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 6 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control Table 6. RON resistance …continued For test circuit see Figure 8. Symbol Parameter Conditions Min Typ Max Unit ∆RON ON resistance mismatch between channels VI = 0.5 × VCC; E = VIL VCC = 2.0 V; ISW = 2 mA - - 15 Ω VCC = 3.0 V; ISW ≤ 2 mA - - 12 Ω VCC = 3.3 V; ISW ≤ 2 mA - - 12 Ω VCC = 4.5 V; ISW ≤ 2 mA - - 12 Ω VCC = 6.0 V; ISW ≤ 2 mA - - 13 Ω VCC = 2.0 V; ISW = 2 mA - - 700 Ω VCC = 3.0 V; ISW ≤ 2 mA - - 380 Ω VCC = 3.3 V; ISW ≤ 2 mA - - 345 Ω VCC = 4.5 V; ISW ≤ 2 mA - - 270 Ω VCC = 6.0 V; ISW ≤ 2 mA - - 250 Ω Tamb = −40 °C to +125 °C RON(peak) ∆RON ON resistance (peak) VI = VCC to GND; E = VIL VI = 0.5 × VCC; E = VIL ON resistance mismatch between channels VCC = 2.0 V; ISW = 2 mA - - 20 Ω VCC = 3.0 V; ISW ≤ 2 mA - - 16 Ω VCC = 3.3 V; ISW ≤ 2 mA - - 16 Ω VCC = 4.5 V; ISW ≤ 2 mA - - 16 Ω VCC = 6.0 V; ISW ≤ 2 mA - - 18 Ω Min Typ[1] Max Unit VCC = 3.3 V - 0.05 1 mV VCC = 5.0 V - 0.03 1 mV VCC = 3.3 V - 0.55 5 mV VCC = 5.0 V - 0.27 5 mV VCC = 3.3 V - 0.04 2 mV VCC = 5.0 V - 0.03 2 mV VCC = 3.3 V - 0.56 20 mV VCC = 5.0 V - 0.48 20 mV Table 7. Injection current coupling For test circuit see Figure 9. Symbol Parameter Conditions Tamb = −40 °C to +125 °C ∆VO output voltage variation |ISW| ≤ 1 mA; RS ≤ 3.9 kΩ [2][3] |ISW| ≤ 10 mA; RS ≤ 3.9 kΩ |ISW| ≤ 1 mA; RS ≤ 20 kΩ |ISW| ≤ 10 mA; RS ≤ 20 kΩ [1] Typical values are measured at Tamb = 25 °C. [2] ∆VO here is the maximum variation of output voltage of an enabled analog channel when current is injected into any disabled channel. [3] ISW = total current injected into all disabled channels. 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 7 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control Table 8. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V 1.5 - - V VCC = 3.0 V 2.1 - - V VCC = 3.3 V 2.3 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V Tamb = 25 °C VIH VIL II HIGH-level input voltage LOW-level input voltage input leakage current control inputs control inputs VCC = 2.0 V - - 0.5 V VCC = 3.0 V - - 0.9 V VCC = 3.3 V - - 1.0 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V - - ±0.1 µA nYn; per channel - - ±0.1 µA nZ; all channels - - ±0.2 µA - - ±0.1 µA control inputs; VI = GND or VCC VCC = 6.0 V IS(OFF) OFF-state leakage current E = VIH; VI = GND or VCC; VO = VCC or GND; VCC = 6.0 V; see Figure 6 IS(ON) ON-state leakage current E = VIL; VI = GND or VCC; VO = VCC or GND; VCC = 6.0 V; see Figure 7 ICC supply current VI = GND or VCC - - 2.0 µA CI input capacitance S0, S1 and E - 2 10 pF Csw switch capacitance nZ; OFF-state - 9 40 pF nYn; OFF-state - 3 15 pF VCC = 2.0 V 1.5 - - V VCC = 3.0 V 2.1 - - V VCC = 3.3 V 2.3 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 6.0 V Tamb = −40 °C to +85 °C VIH VIL HIGH-level input voltage LOW-level input voltage control inputs control inputs VCC = 2.0 V - - 0.5 V VCC = 3.0 V - - 0.9 V VCC = 3.3 V - - 1.0 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 8 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control Table 8. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions II control inputs; VI = GND or VCC input leakage current VCC = 6.0 V IS(OFF) OFF-state leakage current Min Typ Max Unit - - ±0.1 µA - - ±0.5 µA E = VIH; VI = GND or VCC; VO = VCC or GND; VCC = 6.0 V; see Figure 6 nYn; per channel nZ; all channels IS(ON) ON-state leakage current E = VIL; VI = GND or VCC; VO = VCC or GND; VCC = 6.0 V; see Figure 7 ICC supply current VI = GND or VCC VCC = 6.0 V - - ±2.0 µA - - ±2.0 µA - - 5 µA CI input capacitance S0, S1 and E - - 10 pF Csw switch capacitance nZ; OFF-state - - 40 pF nYn; OFF-state - - 15 pF VCC = 2.0 V 1.5 - - V VCC = 3.0 V 2.1 - - V VCC = 3.3 V 2.3 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 3.0 V - - 0.9 V VCC = 3.3 V - - 1.0 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V - - ±1.0 µA - - ±2.0 µA Tamb = −40 °C to +125 °C VIH VIL II HIGH-level input voltage LOW-level input voltage input leakage current control inputs control inputs control inputs; VI = GND or VCC VCC = 6.0 V IS(OFF) OFF-state leakage current E = VIH; VI = GND or VCC; VO = VCC or GND; VCC = 6.0 V; see Figure 6 nYn; per channel nZ; all channels IS(ON) ON-state leakage current E = VIL; VI = GND or VCC; VO = VCC or GND; VCC = 6.0 V; see Figure 7 ICC supply current VI = GND or VCC VCC = 6.0 V 74HC4852_2 Product data sheet - - ±10.0 µA - - ±10.0 µA - - 20.0 µA © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 9 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control Table 8. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit CI input capacitance S0, S1 and E - - 10 pF Csw switch capacitance nZ; OFF-state - - 40 pF nYn; OFF-state - - 15 pF VCC IS A selected channel(1) nYn VI nZ n.c. VCC E VIH A E VIL IS IS nYn nZ nYn A any disabled channel GND VI VO VO GND 001aag098 001aag099 (1) Channel is selected by S0 and S1. Fig 6. Test circuit for measuring OFF-state leakage current Fig 7. Test circuit for measuring ON-state leakage current VCC nYn VI(1) any disabled channel ISW nZ VSW V VCC E VIL VIL E VI(2) nYn selected channel(1) nYn VI nZ RS GND ISW GND V VI 001aag101 001aag100 RON = VSW / ISW. VO (1) Channel is selected by S0 and S1. VI(1) < GND or VI(1) > VCC. GND < VI(2) < VCC. Fig 8. Test circuit for measuring ON resistance Fig 9. Test circuit for injection current coupling 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 10 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control 11. Dynamic characteristics Table 9. Dynamic characteristics GND = 0 V; CL = 50 pF; RL = 10 kΩ unless specified otherwise; for test circuit see Figure 12. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max 2.2 9.3 33 2.2 34 2.2 35 ns 7.7 16.8 38 6.3 40 6.3 42 ns 10.5 20.5 47.5 8.5 52.5 8.5 57.5 ns 39.5 75.4 100 39.3 105 39 115 ns 2.2 4.9 16.5 1.9 18 1.9 19.5 ns 4.9 8.8 20 3.9 21.5 3.9 23 ns 6.2 10.6 45 5.2 50 5.2 55 ns 35.2 69.5 90 35.5 100 35 110 ns 2.0 4.4 15.0 1.6 16.5 1.6 18.5 ns 4.4 7.9 17.5 3.4 19 3.4 22 ns 5.6 9.4 42.5 4.6 47.5 4.6 52.5 ns 34.6 68.1 85 34.6 95 34.5 105 ns 1.6 3.2 11.6 1.1 12.5 1.1 13.5 ns 3.2 5.8 14 2.3 15 2.3 17 ns 4.2 6.9 40 3 45 3 50 ns 28.5 63 80 28.2 90 28 100 ns VCC = 2.0 V tpd propagation delay see Figure 10 [1] nZ, nYn to nYn, nZ Sn to nZ, nYn ten enable time see Figure 11 [2] E to nZ, nYn tdis disable time see Figure 11 [3] E to nZ, nYn VCC = 3.0 V tpd propagation delay see Figure 10 [1] nZ, nYn to nYn, nZ Sn to nZ, nYn ten enable time see Figure 11 [2] E to nZ, nYn tdis disable time see Figure 11 [3] E to nZ, nYn VCC = 3.3 V tpd propagation delay see Figure 10 [1] nZ, nYn to nYn, nZ Sn to nZ, nYn ten enable time see Figure 11 [2] E to nZ, nYn tdis disable time see Figure 11 [3] E to nZ, nYn VCC = 4.5 V tpd propagation delay see Figure 10 [1] nZ, nYn to nYn, nZ Sn to nZ, nYn ten enable time see Figure 11 [2] E to nZ, nYn tdis disable time see Figure 11 E to nZ, nYn [3] 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 11 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control Table 9. Dynamic characteristics …continued GND = 0 V; CL = 50 pF; RL = 10 kΩ unless specified otherwise; for test circuit see Figure 12. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max 1.5 2.5 10.2 0.9 11 0.9 12 ns 2.4 4.8 12.6 1.6 14.5 1.6 16.5 ns 3.2 5.6 39 2.2 40 2.2 40 ns 14.4 57.9 78 13.5 80 13.0 80 ns VCC = 3.3 V - 42 - - - - - pF VCC = 5.0 V - 47 - - - - - pF VCC = 6.0 V [1] propagation delay see Figure 10 tpd nZ, nYn to nYn, nZ Sn to nZ, nYn ten enable time tdis disable time [2] see Figure 11 E to nZ, nYn [3] see Figure 11 E to nZ, nYn Power dissipation capacitance power dissipation capacitance CPD [4] per channel [1] tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑{(CL + Csw) × VCC2 × fo} where: fi = input frequency in MHz; fo = output frequency in MHz; ∑{(CL + Csw) × VCC2 × fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. 12. Waveforms VI nZ, nYn or Sn input VM VM GND tPLH tPHL VOH nYn or nZ input VM VM VOL 001aag102 Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. Input (nZ, nYn or Sn) to output (nYn, nZ) propagation delays 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 12 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control VI VM E input VM 0V tPLZ tPZL VCC nZ or nYn output VM VX VOL tPHZ VOH tPZH VY nZ or nYn output VM GND switch ON switch OFF switch ON 001aag103 Test data is given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 11. Enable and disable times Table 10. Measurement points Supply voltage Input Output VCC VM VI VM VX VY 2.0 V to 6.0 V 0.5 × VCC GND to VCC 0.5 × VCC VOL + 0.1 × (VCC − VOL) 0.9 × VOH 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 13 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control VI tW 90 % 90 % negative pulse VM 0V VI tTHL(tf) tTLH(tr) tTLH(tr) tTHL(tf) 90 % positive pulse 0V VM 10 % VM VM 10 % 10 % tW 001aac221 a. Input pulse definition switch VCC VCC open RL PULSE GENERATOR VI VO DUT CL RT GND 001aaf883 Definitions for test circuit: RL = load resistance. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. b. Load circuitry Test data is given in Table 11. Fig 12. Load circuitry for switching times Table 11. Test data Test Input tr, tf Switch VI tPZH, tPHZ 6 ns VCC GND tPZL, tPLZ 6 ns GND VCC tPHL, tPLH 6 ns pulse open 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 14 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT109-1 (SO16) 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 15 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 14. Package outline SOT403-1 (TSSOP16) 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 16 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 15. Package outline SOT763-1 (DHVQFN16) 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 17 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 13. Revision history Document ID Release date Data sheet status 74HC4852_2 20070530 Product data sheet Modifications: 74HC4852_1 • Supersedes 74HC4852_1 Typo corrected (“one of the eight switches” to “two of the eight switches”) in Section 1 “General description”. 20070323 Product data sheet 74HC4852_2 Product data sheet Change notice - - © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 18 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74HC4852_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 30 May 2007 19 of 20 74HC4852 NXP Semiconductors 4-channel analog MUX/DEMUX with injection-current effect control 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 30 May 2007 Document identifier: 74HC4852_2