Philips Semiconductors Product specification 9-bit D-type flip-flop with reset and enable (3-State) FEATURES 74ABT823 DESCRIPTION • High speed parallel registers with positive edge-triggered D-type The 74ABT823 Bus interface Register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. flip-flops • Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors The 74ABT823 is a 9-bit wide buffered register with Clock Enable (CE) and Master Reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems. • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 The register is fully edge-triggered. The state of each D input, one set-up time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. and 200 V per Machine Model • Power-up 3-State • Power-up Reset QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 4.4 ns tPLH tPHL Propagation delay CP to Qn CL = 50pF; VCC = 5V CIN Input capacitance VI = 0V or VCC 4 pF COUT Output capacitance Outputs disabled; VO = 0V or VCC 7 pF ICCZ Total supply current Outputs disabled; VCC =5.5V 500 nA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 24-Pin Plastic DIP –40°C to +85°C 74ABT823 N 74ABT823 N SOT222-1 24-Pin plastic SO –40°C to +85°C 74ABT823 D 74ABT823 D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT823 DB 74ABT823 DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT823 PW 74ABT823PW DH SOT355-1 PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION Output enable input (active-Low) 1 OE 2, 3, 4, 5, 6, 7, 8, 9, 10 D0-D8 Data inputs 23, 22, 21, 20, 19,18, 17, 16, 15 Q0-Q8 Data outputs Q3 19 Q4 13 CP Clock pulse input (active rising edge) 18 Q5 17 Q6 14 CE Clock enable input (active-Low) 11 MR Master reset input (active-Low) OE 1 24 VCC D0 2 23 Q0 D1 3 22 Q1 D2 4 21 Q2 D3 5 20 D4 6 D5 7 D6 8 D7 9 16 Q7 D8 10 15 Q8 MR 11 14 CE 12 GND Ground (0V) GND 12 13 CP 24 VCC Positive supply voltage TOP VIEW SA00227 1995 Sep 06 1 853–1617 15703 Philips Semiconductors Product specification 9-bit D-type flip-flop with reset and enable (3-State) LOGIC SYMBOL 74ABT823 LOGIC SYMBOL (IEEE/IEC) 1 EN 11 2 3 4 5 6 7 8 9 10 R 14 G1 13 1C2 D0 D1 D2 D3 D4 D5 D6 D7 D8 13 CP 14 CE 11 1 2 23 2D 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 MR OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 23 22 21 20 19 18 17 16 15 SA00228 SA00229 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE OE MR CE CP Dn Q0 – Q8 L L X X X L Clear L H L ↑ h H Load and read data L H L ↑ l L L H H ↑ X NC H X X X X Z H h Hold High impedance = High voltage level = High voltage level one set-up time prior to the Low-to-High clock transition = Low voltage level = Low voltage level one set-up time prior to the Low-to-High clock transition L l NC X Z ↑ ↑ = = = = = No change Don’t care High impedance “off” state Low to High clock transition Not a Low-to-High clock transition LOGIC DIAGRAM 14 CE D0 D1 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 10 13 CP CP CP D R CP D Q R CP D R Q Q CP D D RR Q R CP CP D Q R CP D Q R CP D Q R D Q R Q 11 MR 1 OE 23 Q0 22 Q1 21 20 Q2 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 SA00230 1995 Sep 06 2 Philips Semiconductors Product specification 9-bit D-type flip-flop with reset and enable (3-State) 74ABT823 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT Min Max 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 5 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range 1995 Sep 06 2.0 3 V Philips Semiconductors Product specification 9-bit D-type flip-flop with reset and enable (3-State) 74ABT823 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Min VIK VOH Input clamp voltage High-level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA Typ Max –0.9 –1.2 Min UNIT Max –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V II Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.0V; VO = 0.5V; V OE = VCC; VI = GND or VCC ±5.0 ±50 ±50 µA IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA –100 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC 0.5 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 27 34 34 mA VCC = 5.5V; Outputs 3-State; VI = GND or VCC 0.5 250 250 µA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.5 1.5 1.5 mA IOFF IPU/IPD IO Output current1 ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 VCC = 5.5V; VO = 2.5V –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V 10%, a transition time of up to 100µsec is permitted. AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM Min Typ Max Min UNIT Max fMAX Maximum clock frequency 1 125 200 tPLH tPHL Propagation delay CP to Qn 1 2.1 2.2 4.3 4.4 5.9 6.1 2.1 2.2 6.8 6.7 ns tPHL Propagation delay MR to Qn 2 2.0 4.1 6.3 2.0 7.1 ns tPZH tPZL Output enable time to High and Low level 4 5 1.0 2.2 3.0 4.1 4.5 5.6 1.0 2.2 5.3 6.3 ns tPHZ tPLZ Output disable time from High and Low level 4 5 2.7 2.8 4.8 5.0 6.2 6.4 2.7 2.8 6.9 6.9 ns 1995 Sep 06 4 125 MHz Philips Semiconductors Product specification 9-bit D-type flip-flop with reset and enable (3-State) 74ABT823 AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25oC VCC = +5.0V WAVEFORM Tamb = -40 to +85oC VCC = +5.0V ±0.5V Min Typ Min UNIT ts(H) ts(L) Setup time, High or Low Dn to CP 3 2.1 2.1 0.5 0.2 2.1 2.1 ns th(H) th(L) Hold time, High or Low Dn to CP 3 1.3 1.3 0.0 –0.3 1.3 1.3 ns tw(H) tw(L) CP pulse width High or Low 1 2.9 3.8 1.9 2.8 2.9 3.8 ns ts(H) ts(L) Setup time, High or Low CE to CP 3 2.0 3.3 –0.5 1.5 2.0 3.3 ns th(H) th(L) Hold time, High or Low CE to CP 3 1.0 2.0 –1.4 0.7 1.0 2.0 ns tw(L) MR pulse width, Low 2 5.5 4.0 5.5 ns trec Recovery time MR to CP 2 2.5 0.6 2.5 ns 1995 Sep 06 5 Philips Semiconductors Product specification 9-bit D-type flip-flop with reset and enable (3-State) 74ABT823 AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V MR VM VM 1/fMAX tw(L) CP VM tREC VM CP tW(H) tPHL tPLH VM Qn VM tW(L) tPHL VM Qn VM SA00232 Waveform 2. Master Reset Pulse WIdth, Master Reset to Output Delay and Master Reset to Clock Recovery Time SA00159 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency Dn, CE ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ VM VM ts(H) VM th(H) OE VM ts(L) Qn CP VM Qn tPLZ VM VOL+0.3V 0V SA00067 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 1995 Sep 06 VOH–0.3V SA00066 VM tPZL VM Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 3. Data Setup and Hold Times VM tPHZ 0V NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00231 OE VM tPZH th(L) VM VM 6 Philips Semiconductors Product specification 9-bit D-type flip-flop with reset and enable (3-State) 74ABT823 TEST CIRCUIT AND WAVEFORM VCC 7.0V PULSE GENERATOR VIN tW 90% VOUT VM NEGATIVE PULSE CL 10% 0V RL tTHL (tF) tTLH (tR) tTLH (tR) tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open AMP (V) VM 10% RL D.U.T. RT 90% 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 74ABT Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SA00012 1995 Sep 06 7