PHILIPS PCD5092

INTEGRATED CIRCUITS
DATA SHEET
PCD5092
DECT baseband controller
Objective specification
Supersedes data of 1996 Oct 30
File under Integrated Circuits, IC17
1997 Jul 21
Philips Semiconductors
Objective specification
DECT baseband controller
PCD5092
CONTENTS
1
FEATURES
1.1
DSP software features
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
BLOCK DIAGRAM
5
PINNING INFORMATION
5.1
5.2
Pinning
Pin description
6
FUNCTIONAL DESCRIPTION
7
PACKAGE OUTLINE
8
SOLDERING
8.1
8.2
8.3
8.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
9
DEFINITIONS
10
LIFE SUPPORT APPLICATIONS
11
PURCHASE OF PHILIPS I2C COMPONENTS
1997 Jul 21
2
Philips Semiconductors
Objective specification
DECT baseband controller
1
PCD5092
• Easy interfacing with radio circuits, operating at other
supply voltage (RF supply pin with level shifter for RF
signals)
FEATURES
• 80C51 ports P0, P1, P2 and P3 available for interfacing
to display, keyboard, I2C-bus, interrupt sources and/or
external memory. Integrated 64 kbyte ROM, 3 kbytes of
data memory and 1 kbyte SDR-RAM. External program
memory is addressable up to 128 kbytes
• On-chip comparator for use as data-slicer
• Low power oscillator with integrated frequency
adjustment
• +2.7 to +5 V port (P0 to P3) interface
• QFP100 package
• TDMA frame (de)multiplexing. Transmission or
reception can be programmed for any slot.
• Power-on-reset
• Ciphering, scrambling, CRC checking/generation and
protected B-fields
• Low supply voltage (2.7 to 3.6 V)
• Programmable power-down modes
• CMOS technology.
• Speech and data buffering space for six handsets
• Local call and B-field loop-back
1.1
• Two interrupt lines for BML and DSP to interrupt 80C51
• ADPCM encoding and decoding complying with G.721
• On-chip, three-channel time-multiplexed 8-bit
Analog-to-Digital Converter (ADC) for RSSI
measurement, one for battery voltage measurement
and one channel available for other purposes
DSP software features
• u-law encoding and decoding complying with G.711
• Echo cancellation and network echo suppressor
• Speech filters
• On-chip 8-bit Digital-to-Analog Converter (DAC) for
electronic potentiometer function
• Programmable gain in speech paths
• Phase error measurement and phase error correction by
hardware
• Ringer and tone (DTMF) generator
• DACs and ADCs for dynamic earpiece and dynamic or
electret microphone
• Telephone Answering Machine (TAM) switch.
• Side tone and soft mute
• Automatic gain control
• Very low ohmic buzzer output
For each DSP software version a separate manual is
available in which detailed information is provided on how
parameters must be set. For further information please
contact Philips Semiconductors.
• Serial interface to external ADPCM CODEC (PCD5032)
or 8 kHz u-law samples
2
• On-chip reference voltage
• On-chip supply for electret microphone
• Speech switch for Digital Telephone Answering
Machine (DTAM) connected to SPI interface
The PCD5092 is designed for GAP-compliant single a/b
line basestations with answering machine switch. It has an
embedded 80C51 microcontroller with twice the
performance of the classic architecture, 64 kbytes of
PROM program memory and 3 kbytes of data memory
on-chip. In addition there is 1 kbyte of on-chip data
memory that is shared with on-chip Burst Mode Logic
(BML) and DSP, the System Data RAM (SDR).
• IOM-2 interface (Siemens registered trademark)
• Serial interface to synthesizer for frequency
programming
• Programmable polarity and timing of radio-control
signals
• GMSK pulse shaper
3
GENERAL DESCRIPTION
ORDERING INFORMATION
TYPE
NUMBER
PCD5092H
1997 Jul 21
PACKAGE
NAME
QFP100
DESCRIPTION
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm
3
VERSION
SOT317-2
1997 Jul 21
4
CLK100
XTAL1
XTAL2
GP_CLK7
DPLL_DATA
T_GMSK
R_SLICED
SLICE_CTR
R_PWR
R_ENABLE
REF_CLK
SYNTH_LOCK
S_ENABLE
S_CLK
S_DATA
VCO_BND_SW
S_PWR
ANT_SW0
ANT_SW1
T_ENABLE
T_PWR_RMP
T_DATA
R_DATAP
R_DATAM
A16
PSE
EA
ALE
VDDO
VSSO
EN_WATCHDOG
RESET_OUT
M_RESET
RESET
GENERATOR
(RGE)
WATCHDOG
TIMER
(WDT)
XTAL
OSCILLATOR
(XOSC)
PORT 2
8
PORT 2.0 to
PORT 2.7
IB-BUS
4fs
POWER-ON-RESET
(POR)
ANALOG VOLTAGE
REFERENCE
(AVR)
VDDA
DIGITAL
SIGNAL
PROCESSOR
(DSP)
4fs
VBGP
VDD
ANALOG
VOLTAGE
SOURCE
(AVS)
VADC
Vref
VANLO
DIGITAL
DECIMATING
FILTER
(DDF)
DIGITAL
NOISE
SHAPER
(DNS)
Fig.1 Block diagram.
VDD
I2C-BUS
PORT 3
8
PORT 3.0 to
PORT 3.7
MICROCONTROLLER
MICROCONTROLLER-RAM
(256 BYTES)
DIGITAL
CONTROL
OF
ANALOG
(DCA)
SYSTEM
DATA
RAM
(SDR)
(1 kBYTE)
VDD
AB-MICROCONTROLLER
INTERFACE (ABCIF)
AUX-RAM
(3 kBYTES)
ISB BUS
CONTROLLER
(IBC)
BURST
MODE
LOGIC
(BML)
ROM
(64 kBYTES)
PORT 1
TIMING CONTROL
BLOCK
(TICB)
LEVEL
SHIFTER
VDD
80CL51- CORE
PORT 0
CLOCK
GENERATOR
(CLG)
VDD
AGM
VDDA
VDD_RF
VDD
8
PORT 1.0 to
PORT 1.7
108fs
108fs
5×
VSS
VSSA
PCD5092
2×
VDD3V
ARF
MUX
3:1
SUBTRACT
PEAK-HOLD
AUXILIARY ADC (AAD)
CODEC
ATS
Σ∆
1-BIT ADC
ARD
BUZZER BUFFER
(ABB)
AMP
SPEECH INTERFACE
IOM/ADPCM
(SPI)
Vref
MBH946
3×
VDD5V
CDC-on
ARA
VDDA
TEST CONTROL BLOCK
(TCB)
1-BIT ADC
VDDA
VDD
VDD_RF
VBAT
RSSI_AN
VANLI
Vref
VMIC
MICP
MICM
LIFP
LIFM
EARP
EARM
BZP
BZM
DO
DI
FS1
DCK
CLK3
TST1
TST2
digital pins
analog pins
4
8
PORT 0.0 to
PORT 0.7
DECT baseband controller
handbook, full pagewidth
Philips Semiconductors
Objective specification
PCD5092
BLOCK DIAGRAM
Philips Semiconductors
Objective specification
DECT baseband controller
81 P2.3
82 P2.4
83 P2.5
84 P2.6
85 P2.7
86 PSE
87 ALE
89 VSS5
88 EA
90 VDD5V_3
91 P0.7
92 P0.6
93 P0.5
94 P0.4
95 P0.3
96 P0.2
97 P0.1
handbook, full pagewidth
98 P0.0
Pinning
99 M_RESET
ANT_SW1
1
80
TST2
ANT_SW0
2
79
TST1
CLK100
3
78
VSS4
T_ENABLE
4
77
VDD5V_2
T_PWR_RMP
5
76
A16
T_DATA
6
75
P2.2
T_GMSK
7
74
P2.1
VCO_BND_SW
8
73
P2.0
SYNTH_LOCK
9
72
P3.7
S_ENABLE 10
71
P3.6
S_DATA 11
70
P3.5
S_CLK 12
69
P3.4
S_PWR 13
68
P3.3
REF_CLK 14
67
P3.2
VSS1 15
66
P3.1
65
P3.0
64
VSS3
SLICE_CTR 18
63
VSS2
R_PWR 19
62
BZP
R_DATAP
20
61
BZM
R_DATAM
21
60
VDD3V_2
R_ENABLE
22
59
P1.7
RSSI_AN
23
58
P1.6
VANLI
24
57
P1.5
VBAT
25
56
P1.4
CLK3
26
55
P1.3
DCK
27
54
VDD5V_1
PCD5092
VDD_RF 16
VDD3V_1 17
Fig.2 Pin configuration (QFP100).
1997 Jul 21
5
P1.2 50
P1.1 49
P1.0 48
EN_WATCHDOG 47
EARP 46
EARM 45
VDDA 44
VBGP 43
Vref 42
VMIC 41
MICP 40
VSSA 38
GP_CLK7
LIFP 37
51
LIFM 36
30
VDDO 35
DPLL_DATA
DO
VSSO 34
R_SLICED
52
VANLO 33
53
29
XTAL1 32
28
XTAL2 31
DI
FS1
MICM 39
5.1
PINNING INFORMATION
100 RESET_OUT
5
PCD5092
MGD799
Philips Semiconductors
Objective specification
DECT baseband controller
5.2
PCD5092
Pin description
Table 1
QFP100 package
SYMBOL
ANT_SW1
PIN
I/O
STATE
AFTER
RESET
1
O
H
ISP2DRF3
PIN TYPE
PIN DESCRIPTION
antenna switch 1 output
ANT_SW0
2
O
H
ISP2DRF3
antenna switch 0 output
CLK100
3
O
H
ISP2DPES
100 Hz signal related to DECT frame timing output
T_ENABLE
4
O
H
ISP2DRF3
enable transmitter output
T_PWR_RMP
5
O
L
ISP2DRF3
switch transmitter power output
T_DATA
6
O
off
ISF2DRF3
unmodulated transmitter data output
T_GMSK
7
O
L
ANAIOD1
GMSK modulated transmitter data output
VCO_BND_SW
8
O
L
ISP2DRF3
VCO band switch output
SYNTH_LOCK
9
I
−
DIPP0RF3
synthesizer lock input
S_ENABLE
10
O
L
ISP2DRF3
synthesizer enable output
S_DATA
11
O
L
ISP2DRF3
serial synthesizer data output
S_CLK
12
O
L
ISP2DRF3
clock for serial synthesizer interface output
S_PWR
13
O
H
ISP2DRF3
switch synthesizer power output
REF_CLK
14
O
running
ISP4DRF3
13.824 MHz reference clock for synthesizer output
VSS1
15
−
−
supply
negative supply voltage 1
VDD_RF
16
−
−
supply
positive supply voltage for RF interface level shifters
VDD3V_1
17
−
−
supply
positive supply voltage 1 (+3 V)
SLICE_CTR
18
O
L
ISP2DRF3
switch slicer time constant output
R_PWR
19
O
H
ISP2DRF3
switch receiver power output
R_DATAP
20
I
−
ANAIOD2
positive input for receiver data
R_DATAM
21
I
−
ANAIOD2
negative input for receiver data
R_ENABLE
22
O
H
ISP2DRF3
enable receiver output
RSSI_AN
23
I
−
ANAIOD1
analog input for RSSI measurement
VANLI
24
I
−
ANAIOD1
analog input to ADC
VBAT
25
I
−
ANAIOD1
analog input for battery voltage measurement
CLK3
26
O
L
ISP2DPES
3.456 MHz clock output for external ADPCM codec
DCK
27
I/O
input
ISF2DPES
ISF2UPES
ADPCM output or IOM data clock input/output
(ISF2UPES in PCD5090/xxx, PCA5097/xxx)
DI
28
I
−
DIPP0PES
ADPCM or IOM data input
FS1
29
I/O
input
ISF2DPES
ISF2UPES
8 kHz framing input/output
(ISF2UPES in PCD5090/xxx, PCA5097/xxx)
DO
30
O
off
ISI8DPES
ADPCM or IOM data output
XTAL2
31
O
running
ANAIOD1
crystal oscillator output
XTAL1
32
I
−
ANAIOD1
crystal oscillator input
VANLO
33
O
1.0 V
ANAIOD1
analog output from D/A converter
1997 Jul 21
6
Philips Semiconductors
Objective specification
DECT baseband controller
PCD5092
PIN
I/O
STATE
AFTER
RESET
VSSO
34
−
−
supply
negative supply voltage for the oscillator
VDDO
35
−
−
supply
positive supply voltage for the oscillator
LIFM
36
I
0.7 V
ANAIOD1
negative input from line interface
LIFP
37
I
0.7 V
ANAIOD1
positive input from line interface
VSSA
38
−
−
supply
negative supply voltage for analog circuits
MICM
39
I
0.7 V
ANAIOR1
negative input from microphone
MICP
40
I
0.7 V
ANAIOR1
positive input from microphone
VMIC
41
O
off
ANAIOD1
positive microphone supply voltage (+2 V)
Vref
42
O
2.0 V
ANAIOD1
reference voltage (+2 V)
VBGP
43
O
1.25 V
ANAIOR1
bandgap output voltage (+1.25 V)
VDDA
44
−
−
supply
positive supply voltage for analog circuits
EARM
45
O
1.4 V
ANAIOD1
negative output to earpiece
EARP
46
O
1.4 V
ANAIOD1
positive output to earpiece
EN_WATCHDOG
47
I
−
DIUP0PES
watchdog enable input
P1.0
48
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P1.1
49
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P1.2
50
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
GP_CLK7
51
O
L
ISP2DPES
general purpose 6.912 MHz output
DPLL_DATA
52
O
L
ISP2DPES
data after clock recovery network
R_SLICED
53
O
L
ISP2DPES
R_DATA comparator output
VDD5V_1
54
−
−
supply
positive supply voltage 1 for the +5 V interface
P1.3
55
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P1.4
56
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P1.5
57
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P1.6
58
I/O
off
ISI8DPES
bidirectional 80C51 port pin
P1.7
59
I/O
off
ISI8DPES
bidirectional 80C51 port pin
VDD3V_2
60
−
−
supply
positive supply voltage 2 (+3 V)
BZM
61
O
L
ANAIOD2
negative buzzer output
BZP
62
O
L
ANAIOD2
positive buzzer output
VSS2
63
−
−
supply
negative supply voltage 2
VSS3
64
−
−
supply
negative supply voltage 3
P3.0
65
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P3.1
66
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P3.2
67
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P3.3
68
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P3.4
69
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P3.5
70
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
SYMBOL
1997 Jul 21
PIN TYPE
7
PIN DESCRIPTION
Philips Semiconductors
Objective specification
DECT baseband controller
PCD5092
PIN
I/O
STATE
AFTER
RESET
PIN TYPE
P3.6
71
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P3.7
72
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P2.0
73
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P2.1
74
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P2.2
75
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
A16
76
O
L
ISP4DPES
address bit 16 for 128 kbytes external program memory
VDD5V_2
77
−
−
supply
positive supply voltage 2 for the +5 V interface
VSS4
78
−
−
supply
negative supply voltage 4
TST1
79
I
−
DIDP0PES
test input 1
TST2
80
I
−
DIDP0PES
test input 2
P2.3
81
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P2.4
82
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P2.5
83
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P2.6
84
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
SYMBOL
PIN DESCRIPTION
P2.7
85
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
PSE
86
O
H
ISQ2CPES
program store enable (80C51); active LOW
ALE
87
O
H
ISQ4CPES
address latch enable (80C51)
EA
88
I
−
ISF2DPES
external access enable (80C51); active LOW
VSS5
89
−
−
supply
negative supply voltage 5
VDD5V_3
90
−
−
supply
positive supply voltage 3 for the +5 V interface
P0.7
91
I/O
off
H
ISP2DPES
ISQ2CPES
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
P0.6
92
I/O
off
H
ISP2DPES
ISQ2CPES
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
P0.5
93
I/O
off
H
ISP2DPES
ISQ2CPES
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
P0.4
94
I/O
off
H
ISP2DPES
ISQ2CPES
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
P0.3
95
I/O
off
H
ISP2DPES
ISQ2CPES
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
P0.2
96
I/O
off
H
ISP2DPES
ISQ2CPES
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
P0.1
97
I/O
off
H
ISP2DPES
ISQ2CPES
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
P0.0
98
I/O
off
H
ISP2DPES
ISQ2CPES
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
M_RESET
99
I
−
DIDP0PES
master reset input (Schmitt trigger)
RESET_OUT
100
O
H
ISF2DPES
reset output
1997 Jul 21
8
Philips Semiconductors
Objective specification
DECT baseband controller
6
PCD5092
FUNCTIONAL DESCRIPTION
The PCD509x is a family of single-chip controllers, designed for use in Digital Enhanced Cordless Telecommunications
systems (DECT). The family is designed for minimum component-count and minimum power consumption. All controllers
include an embedded 80C51 microcontroller with on-chip memory and I2C-bus. The Philips DECT RF interface is
implemented. The Burst Mode Logic (BML) performs the time-critical MAC layer functions for applications in DECT
handsets and base stations. The ADPCM transcoding is in compliance with the CCITT recommendation G.721 and
includes receive and transmit filters.
handbook, full pagewidth
EARPIECE
RADIO
CIRCUITS
PCD5091
MICROPHONE
MGD797
a. Handset.
handbook, full pagewidth
RADIO
CIRCUITS
LINE
INTERFACE
(e.g. TEA1118)
PCD5092/
PCD5094
a/b line
u-law TAM switch
MBH945
b. Basestation (PCD5092) with analog interface and echo cancellation; up to 6 portables can be handled.
handbook, full pagewidth
EARPIECE
RADIO
CIRCUITS
PCD5093
MICROPHONE
2
2 x IOM or
2 x ADPCM-CODEC or
a combination
MGD795
c. Base with digital interface and analog handset connected; up to 6 portables can be handled.
Fig.3 Block diagrams of DECT systems with PCX509x.
1997 Jul 21
9
Philips Semiconductors
Objective specification
DECT baseband controller
7
PCD5092
PACKAGE OUTLINE
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT317-2
c
y
X
80
A
51
81
50
ZE
Q
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
L
31
100
detail X
30
1
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
3.20
0.25
0.05
2.90
2.65
0.25
0.40
0.25
0.25
0.14
20.1
19.9
14.1
13.9
0.65
24.2
23.6
18.2
17.6
1.95
1.0
0.6
1.4
1.2
0.2
0.15
0.1
Z D (1) Z E(1)
0.8
0.4
1.0
0.6
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT317-2
1997 Jul 21
EUROPEAN
PROJECTION
10
o
7
0o
Philips Semiconductors
Objective specification
DECT baseband controller
8
8.1
PCD5092
8.3
SOLDERING
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
8.2
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Reflow soldering
Even with these conditions do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
8.4
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1997 Jul 21
Wave soldering
11
Philips Semiconductors
Objective specification
DECT baseband controller
9
PCD5092
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Short-form specification
The data in this specification is extracted from a full data sheet with the same type
number and title. For detailed information see the relevant data sheet or data handbook.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
10 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
11 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Jul 21
12
Philips Semiconductors
Objective specification
DECT baseband controller
PCD5092
NOTES
1997 Jul 21
13
Philips Semiconductors
Objective specification
DECT baseband controller
PCD5092
NOTES
1997 Jul 21
14
Philips Semiconductors
Objective specification
DECT baseband controller
PCD5092
NOTES
1997 Jul 21
15
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
437027/00/02/pp16
Date of release: 1997 Jul 21
Document order number:
9397 750 01657