PHILIPS TDA10045H

INTEGRATED CIRCUITS
DATA SHEET
TDA10045H
DVB-T channel receiver
Product specification
Supersedes data of 2000 Jun 21
File under Integrated Circuits, IC02
2001 Nov 08
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
FEATURES
• 2 and 8 kbytes Coded Orthogonal Frequency Division
Multiplexer (COFDM) demodulator (fully DVB-T
compliant: ETSI 300-744)
• All modes supported, including hierarchical modes
• Fully automatic transmission parameters detection
(including Fast Fourier Transformer (FFT) size and
guard interval)
GENERAL DESCRIPTION
The TDA10045H is a single-chip channel receiver for
2 and 8 kbytes COFDM modulated signals based on the
ETSI specification (ETSI 300-744). The device interfaces
directly to an IF signal, which could be either 1st or 2nd IF
and integrates a 10-bit Analog-to-Digital Converter (ADC),
a Numerically Controlled Oscillator (NCO) and a
Phase-Locked Loop (PLL), simplifying external logic
requirements and limiting system costs.
• Digital Signal Processor (DSP) based synchronization
(software can be upgraded on the fly)
• No extra-host software required
• On-chip 10-bit Analog-to-Digital Converter (ADC)
• 2nd or 1st IF variable analog input
• Only fundamental crystal oscillator required (4 MHz
typical ±100 ppm)
The TDA10045H performs all the COFDM demodulation
tasks from IF signal to the MPEG-2 transport stream. An
internal DSP core manages the synchronization and the
control of the demodulation process, and implements
specially developed software for robustness against
co-channel and adjacent channel interference, to deal with
Single Frequency Network (SFN) echo situations, and to
assist in a very fast scan of the bandwidth. After baseband
conversion and FFT demodulation, the channel frequency
response is estimated, which is based on the scattered
pilots, and filtered in both time and frequency domains.
This estimation is used as a correction on the signal,
carrier by carrier. A common phase error and estimator is
used to deal with the tuner phase noise. The Forward Error
Correction (FEC) decoder is automatically synchronized
by the frame synchronization algorithm that uses the TPS
information included in the modulation. An embedded
‘pulse killer’ algorithm enables the bad effects of short and
strong impulsive noise interference that could be caused
by electrical domestic devices and/or car traffic to be
greatly reduced.
• 6, 7 and 8 MHz channels with the same crystal
• Pulse killer algorithm to protect against impulse noise
• Digital frequency correction (±90 kHz)
• Frequency offset (±1/6 MHz) automatic estimator to
speed-up the scan
• RF tuner input power measurement
• Parallel or serial transport stream interface
• BER measurement (before and after Viterbi decoder)
• Signal-to noise ratio estimation
• Constellation, CSI and channel frequency response
outputs
• TPS bits I2C-bus readable (including spare ones)
• Controllable dedicated I2C-bus for the tuner
(5 V tolerant)
• 3 low frequency spare DACs and 2 spare inputs
• CMOS 0.2 µm technology.
This device is controlled via an I2C-bus (master). The chip
provides 2 switchable I2C-buses derived from the master:
a tuner I2C-bus to be disconnected from the I2C-bus
master when not necessary and an EEPROM I2C-bus.
The DSP software code can be fed to the chip via the
master I2C-bus or via the dedicated EEPROM I2C-bus.
APPLICATIONS
• DVB-T fully compatible
• Digital data transmission using COFDM modulation.
Designed in 0.2 µm CMOS technology and housed in a
100 pin QFP package, the TDA10045H operates over the
commercial temperature range.
2001 Nov 08
2
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
ORDERING INFORMATION
TYPE
NUMBER
TDA10045H
2001 Nov 08
PACKAGE
VERSION
NAME
QFP100
DESCRIPTION
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm
3
SOT317-2
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A
10
D
C
analog IF
(VIM, VIP)
∆Σ
BASEBAND
CONVERSION
TIME
RECOVERY
(NCO)
2fs
FFT
CPE
CALCULATION
COARSE
TIME
ESTIMATOR
PARTIAL CHANNEL
ESTIMATION
TIME
INTERPOLATION
PLL
SP_IN(1:0)
4
DS_SPARE(3:1)
spare inputs
DSP CORE
3 SPARE ∆Σ
SCL_EEP
SDA_EEP
optional
SCL
SDA
I2C-BUS
3* 10
FREQUENCY
INTERPOLATION
SYNCHRONIZATION
FREQUENCY, TIME, FRAME, RECOVERY
FFT WINDOW POSITIONING
TPS DECODING
INTERFACE
CONFIDENCE
CALCULATION
TDA10045H
SCL_TUN
SDA_TUN
MPEG-2
OUTPUT
INTERFACE
DESCRAMBLER
RS
DECODER
OUTER
FORNEY
DE-INTERLEAVER
CPT_UNCOR
VITERBI
DECODER
VBER
confidence
frequency response
BIT
DE-INTERLEAVER
CHANNEL
CORRECTION
(I,Q)
constellation
INNER
FREQUENCY
DE-INTERLEAVER
AND DE-MAPPER
CBER
Product specification
Fig.1 Block diagram.
MGU414
TDA10045H
CHANNEL DECODER
handbook, full pagewidth
XIN
COFDM
spectrum
CARRIER
RECOVERY
fs
SACLK
CHANNEL ESTIMATION
AND CORRECTION
DIGITAL FRONT-END
AND COFDM
DEMODULATION
AGC
Philips Semiconductors
10
digital IF
FI (9:0)
DVB-T channel receiver
BLOCK DIAGRAM
2001 Nov 08
VAGC
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
PINNING
SYMBOL
PIN
TYPE
VDDD33
1
−
digital supply voltage for the pads (3.3 V typ.)
VSSD
2
−
digital ground supply (0 V
DS_SPARE3
3
O
spare delta-sigma output; managed by the DSP to generate an analog level
(after a RC low-pass filter)
VAGC
4
O
output value from the Delta-Sigma modulator, used to control a log-scaled
amplifier (after analog filtering)
SCL_EEP
5
O
extra I2C-bus clock to download DSP code from an external EEPROM (optional
mode); can be connected to the master I2C-bus
VDDD33
6
−
digital supply voltage for the pads (3.3 V typ.)
VSSD
7
−
digital ground supply (0 V)
SDA_EEP
8
I/OD
extra I2C-bus data bus to download DSP code from an external EEPROM
(optional mode). It can be connected to the master I2C-bus; this pin is
open-drain which requires an external pull-up resistor (to VDDD33 or VDDD50),
even if not used.
SCL_TUN
9
OD(1)
tuner I2C-bus serial clock signal; this signal is derived from the master SCL and
is open-drain which requires an external pull-up resistor (to VDDD33 or VDDD50),
even if not used
SDA_TUN
10
I/OD
tuner I2C-bus serial data signal; this signal is derived from the master SDA and
is open-drain which requires an external pull-up resistor (to VDDD33 or VDDD50),
even if not used
SCL
11
I(2)
SDA
12
I/OD
n.c.
13
−
14
I(2)
asynchronous reset signal; active LOW
15
I(2)
EEPADDR is the LSB of the I2C-bus address of the EEPROM. The MSBs are
internally set to 101000. Therefore the complete I2C-bus address of the
EEPROM is (MSB to LSB): 1, 0, 1, 0, 0, 0, EEPADDR.
16 and 17
I(2)
SADDR[1:0] are the 2 LSBs of the I2C-bus address of the TDA10045; the MSBs
are internally set to 00010; therefore the complete I2C-bus address of the
TDA10045 is (MSB to LSB): 0, 0, 0, 1, 0, SADDR[1] and SADDR[0]
18
−
digital supply voltage for the core (1.8 V typ.)
digital ground supply (0 V)
CLR#
EEPADDR
SADDR[1:0]
VDDD18
DESCRIPTION
I2C-bus master serial clock; up to 700 kbit/s
I2C-bus master serial data input/output, open-drain I/O pad, which requires an
external pull-up resistor (to VDDD33 or VDDD50)
not connected
19
−
20 to 23
I(2)
test mode bus; for test purpose; must be set to ‘0000’
SCAN_EN
24
I(2)
scan enable for production test; connected to GND
VDDD50
25
−
digital supply voltage (5 V typ.); can be set to 3.3 V (with caution) if the 5 V
tolerant I/O is not required
VSSD
26
−
digital ground supply (0 V)
DWNLOAD
27
I(2)
processor control, boot mode; if set to logic 0, the DSP downloads the software
from an external EEPROM on the dedicated I2C-bus (pins SDA_EEP and
SCL_EEP). If set to logic 1 the software is downloaded in the I2C-bus register
CODE_IN from the host; in this case the external EEPROM is not needed.
SP_IN[1:0]
28 and 29
I(2)
spare inputs
VSSD
TM[3:0]
2001 Nov 08
5
Philips Semiconductors
Product specification
DVB-T channel receiver
SYMBOL
PIN
TYPE
FFT_WIN
30
I/O
TDA10045H
DESCRIPTION
output or input signal indicating the start of the active data; equals 1 during
complex sample 0 of the active FFT block; can be used to synchronize 2 chips
VDDD33
31
−
digital supply voltage for the pads (3.3 V typ.)
VSSD
32
−
digital ground supply (0 V)
SACLK
33
O
sampling frequency output; this output clock can be fed to an external (10-bit)
ADC as a sampling clock; SACLK can also provide twice the sampling clock
FI[9:5]
34 to 38
I/O
input data from an external ADC, FI must be tied to ground when unused,
positive notation (from 0 to 1023) or twos complement notation (from
−512 to +511). In internal ADC mode, these outputs can be used to monitor
extra demodulator output signals (constellation or frequency response).
VDDD18
39
−
digital supply voltage for the core (1.8 V typ.)
VSSD
40
−
digital ground supply (0 V)
FI[4:0]
41 to 45
IO
input data from an external ADC, FI must be tied to ground when unused,
positive notation (from 0 to 1023) or twos complement notation (from
−512 to +511). In internal ADC mode, these outputs can be used to monitor
extra demodulator output signals (constellation or frequency response).
VDDD50
46
−
digital supply voltage (5 V typ.); can be set to 3.3 V (with caution) if 5 V tolerant
I/O is not required
VSSD
47
−
digital ground supply (0 V)
IT
48
OD(1)
interrupt line; this output interrupt line can be configured by the I2C-bus
interface. This pin is an open-drain output and therefore requires an external
pull-up resistor (to VDDD33 or VDDD50).
FEL
49
OD(1)
front-end lock; FEL is an open-drain output and therefore requires an external
pull-up resistor (to VDDD33 or VDDD50)
n.c.
50
−
not connected
n.c.
51
−
not connected
52
I(2)
asynchronous reset signal for boundary scan; connected to GND if not used
TMS
53
I(2)
mode programming signal for boundary scan; connected to GND if not used
TDI
54
I(2)
input port for boundary scan; connected to GND if not used
TCK
55
I(2)
clock signal for boundary scan; connected to GND if not used)
TDO
56
O
output port for boundary scan; not connected if not used
TRSTN
VDDD18
57
−
digital supply voltage for the core (1.8 V typ.)
VSSD
58
−
digital ground supply (0 V)
DS_SPARE2
59
O
spare delta-sigma output; managed by the DSP or by an I2C-bus register to
generate an analog level (after a RC low-pass filter)
DS_SPARE1
60
O
spare delta-sigma output; managed by the DSP to handle a low frequency DAC
(automatic first stage tuner AGC measurement or 2nd AGC loop control as
examples)
VDDD33
61
−
digital supply voltage for the pads (3.3 V typ.)
VSSD
62
−
digital ground supply (0 V)
UNCOR
63
O
RS error flag, active HIGH on one RS packet if the RS decoder fails to correct
the errors
PSYNC
64
O
pulse synchro; this output signal goes HIGH on a rising edge of OCLK when a
synchro byte is provided, then goes LOW until the next synchro byte
2001 Nov 08
6
Philips Semiconductors
Product specification
DVB-T channel receiver
SYMBOL
DEN
OCLK
TDA10045H
PIN
TYPE
DESCRIPTION
65
O
output data validation signal; active HIGH during the valid and regular data bytes
66
O
output clock; OCLK is the output clock for the parallel DO[7:0] outputs
DO[7:5]
67 to 69
O
output data carrying the current sample of the current MPEG2 packet
(188 bytes), delivered on the rising edge of OCLK by default when the serial
mode is selected. The output data is delivered by DO[0].
VDDD18
70
−
digital supply voltage for the core (1.8 V typ.)
71
−
digital ground supply (0 V)
DO[4:0]
72 to 76
O
output data carrying the current sample of the current MPEG2 packet
(188 bytes), delivered on the rising edge of OCLK by default when the serial
mode is selected. The output data is delivered by DO[0].
VDDD33
77
−
digital supply voltage for the pads (3.3 V typ.)
VSSD
78
−
digital ground supply (0 V)
XIN
79
I(2)
crystal oscillator input pin
XOUT
80
O
crystal oscillator output pin; typically a fundamental crystal oscillator is
connected between pins XIN and XOUT
VSSD
VDDD18
81
−
digital supply voltage for the core (1.8 V typ.)
VSSD
82
−
digital ground supply (0 V)
n.c.
83
−
not connected
VCCD(PLL)
84
−
power supply input for the digital circuits of the PLL module (1.8 V typ.)
DGND
85
−
ground return for the digital circuits of the PLL module
n.c.
86
−
not connected
PPLGND
87
−
ground return for the analog circuits of the PLL module
VCCA(PLL)
88
−
power supply input for the analog circuits of the PLL module (3.3 V typ.)
VSSA3
89
−
ground return for the analog circuits
VDDA3
90
−
power supply input for the analog circuits; the DC voltage should be 3.3 V
VIP
91
−
positive input to the ADC; this pin is DC biased to half supply through an internal
resistor divider (2 × 20 kΩ resistors). In order to remain in the range of the ADC,
the voltage difference between pins VIP and VIM should be between −0.5 and
+0.5 V.
VIM
92
−
negative input to the ADC; this pin is DC biased to half supply to remain in the
range of the ADC, the voltage difference between pins VIP and VIM should be
between −0.5 and +0.5 V through an internal resistor divider (2 × 20 kΩ
resistors)
Vref(neg)
93
−
negative reference voltage for the ADC
Vref(pos)
94
−
positive reference voltage for the ADC
VDDA3
95
−
power supply input for the analog circuits; the DC voltage should be 3.3 V
VSSA3
96
−
ground return for analog circuits
VSSA2
97
−
ground return for the analog clock drivers
VDDA2
98
−
power supply input for the analog clock drivers; the DC voltage should be 3.3 V
VSSA1
99
−
ground return for the digital switching circuitry
VDDD1
100
−
power supply input for the digital switching circuitry; sensitive to the supply
noise; the DC voltage should be 1.8 V
2001 Nov 08
7
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
Notes
1. OD are open-drain outputs, so they must be connected to a pull-up resistor to either VDDD33 or VDDD50
2. All inputs (I) are TTL, 5 V tolerant, (if VDD50 is set to 5 V).
82 VSSD
81 VDDD18
84 VCCD(PLL)
83 n.c.
85 DGND
86 n.c.
88 VCCA(PLL)
87 PPLGND
89 VSSA3
91 VIP
90 VDDA3
92 VIM
93 Vref(neg)
94 Vref(pos)
96 VSSA3
95 VDDA3
98 VDDA2
97 VSSA2
handbook, full pagewidth
99 VSSA1
100 VDDD1
3. Foundry test I/O inputs must be connected to GND.
VDDD33
1
80 XOUT
VSSD
2
79 XIN
DS_SPARE3
3
VAGC
4
78 VSSD
77 VDDD33
SCL_EEP
5
76 DO[0]
VDDD33
6
75 DO[1]
VSSD
7
74 DO[2]
SDA_EEP
8
73 DO[3]
SCL_TUN
9
72 DO[4]
SDA_TUN 10
71 VSSD
SCL 11
70 VDDD18
69 DO[5]
SDA 12
n.c. 13
68 DO[6]
CLR# 14
67 DO[7]
EEPADDR 15
66 OCLK
TDA10045H
SADDR[1] 16
65 DEN
SADDR[0] 17
64 PSYNC
VDDD18 18
63 UNCOR
62 VSSD
VSSD 19
TM[3] 20
TM[2] 21
61 VDDD33
60 DS_SPARE1
TM[1] 22
59 DS_SPARE2
TM[0] 23
58 VSSD
57 VDDD18
SCAN_EN 24
VDDD50 25
56 TDO
VSSD 26
55 TCK
54 TDI
DWNLOAD 27
SP_IN[1] 28
53 TMS
SP_IN[0] 29
52 TRSTN
51 n.c.
Fig.2 Pin configuration.
2001 Nov 08
8
n.c. 50
FEL 49
IT 48
FI[0] 45
VDDD50 46
VSSD 47
FI[1] 44
FI[2] 43
FI[3] 42
FI[4] 41
VDDD18 39
VSSD 40
FI[5] 38
FI[6] 37
FI[7] 36
FI[8] 35
FI[9] 34
SACLK 33
VDDD33 31
VSSD 32
FFT_WIN 30
MGU413
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
LIMITING VALUES
In accordance with the Absolute Maximum Rate System (IEC 60134); note 1.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDDD18
digital supply voltage for the core
−0.5
+2.1
V
VDDD33
digital supply voltage for the pads
−0.5
+3.8
V
VI
DC input voltage
−0.5
+5.5
V
II
DC input current
−
±20
mA
Tlead
lead temperature
−
300
°C
Tstg
storage temperature
−65
+150
°C
Tj
junction temperature
−
150
°C
Tamb
ambient temperature
0
70
°C
Note
1. Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute
Maximum Ratings conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
2001 Nov 08
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
9
in free air
VALUE
UNIT
tbf
K/W
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Core and pads
VDDD33
digital supply voltage for the
pads
VDDD = 3.3 V ± 10%
2.97
3.3
3.63
V
VDDD18
digital supply voltage for the
core
VDDD = 1.8 V ± 5%
1.7
1.8
1.9
V
VDDD50
5 V supply voltage
only for 5 V
requirements; note 1
4.75
5.0
5.25
V
Tamb
ambient temperature
0
−
70
°C
VIH
HIGH-level input voltage
TTL input; note 2
2
−
VDDD50
V
VIL
LOW-level input voltage
TTL input
0
−
0.8
V
VOH
HIGH-level output voltage
IOH = ±2 mA
2.4
−
−
V
VOL
LOW-level output voltage
IOL = ±2 mA
−
−
0.4
V
Ci
input capacitance
−
−
5
pF
Co
output capacitance
−
−
5
pF
PLL
VCCD(PLL)
digital PLL supply voltage
VCCD = 1.8 V ± 5%
1.7
1.8
1.9
V
VCCA(PLL)
analog PLL supply voltage
VCCA = 3.3 V ± 10%
2.97
3.3
3.63
V
VDDD1
digital ADC supply voltage
VDDD = 1.8 V ± 5%
1.7
1.8
1.9
V
VDDA2, VDDA3
analog ADC supply voltage
VDDA = 3.3 V ± 10%
2.97
3.3
3.63
V
Vi(ADC)
analog ADC inputs pins VIP
and VIM
−0.5
−
VDDD3 + 0.5
V
Vi
signal input
IR = VIP − VIM;
depending on SW
register
−0.5 to −1.0
−
+0.5 to +1.0
V
ADC
Vref(pos)
positive reference voltage
with SW register = 11 1.95
2.15
2.35
V
Vref(neg)
negative reference voltage
with SW register = 11 0.95
1.15
1.35
V
Vi(offset)
input offset voltage
−25
−
+25
mV
Ri
input resistance pin VIP or
VIM
−
10
Ci
input capacitance pin VIP or
VIM
−
5
10
pF
BW
input full power bandwidth
40
50
−
MHz
2001 Nov 08
3 dB bandwidth
10
kΩ
Philips Semiconductors
Product specification
DVB-T channel receiver
SYMBOL
PARAMETER
TDA10045H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Power consumption
IDDD
Ptot
digital supply current on
pins:
fs = 29 Mhz; direct IF
application
VDDD18 and VDDD1
−
140
160
mA
VDDD33
−
3
−
mA
VCCD(PLL), VDDA2 and VDDA3
−
35
−
mA
VDDD50
−
5
−
mA
total power dissipation
−
400
470
mW
Notes
1. The voltage level of the 5 V supply must always exceed, or at least equal, the voltage level of the 3.3 V supply during
power-up and down in order to guarantee protection against latch-up.
2. All inputs are 5 V tolerant.
2001 Nov 08
11
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
APPLICATION INFORMATION
handbook, full pagewidth
I2C-BUS
EEPROM
RC
optinal
IF1
RF
TUNER +
SAWs
RF_AGC
IF1 or
IF2
IF_AGC
VIP
IF
INTERFACE
SCL
SDA
VAGC
VIM
XIN
A
D
C
XOUT
SDA_EEP
SCL_EEP
10
PSYNC
UNCOR
optional IF2
downconversion
reference
frequency
DEN
TDA10045H
OCLK
8
SACLK
RC
DO[7:0]
SDA_TUN
SCL_TUN
RC
DS_SPARE_1
SCL, SDA
SP_IN(0)
optional ADC
I2C-bus
MGU415
Fig.3 DVB-T front-end receiver.
VDDD50 VDDD33 VDDD18
handbook, full pagewidth
XIN
VSSD
XOUT
VAGC
SDA_TUN
FI[9:0]
10
SCL_TUN
IT
FEL
TDA10045H
CLR#
PSYNC
VIP
UNCOR
VIM
DEN
I2C-BUS
INTERFACE
OCLK
DSP INTERFACE
JTAG
8
DO[7:0]
MGU416
SADDR(1:0)
SCL
SDA
SDA_EEP
SCL_EEP
SP_IN
BS_SPARE
Fig.4 Application diagram.
2001 Nov 08
12
TDI TDO
TCK
TMS
TRST
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
Tuner
TDA10045H
• A RF tracking filter tracks the RF wanted frequency and
suppresses the image
• The chip is controlled by an I2C-bus and driven by an
external low-cost crystal oscillator
• A first local wideband AGC is usually done at RF level,
the AGC level information could be provided externally
and the chip offers facilities to measure this level by the
optional ADC (this measurement is automatically made
by the DSP, the host has just to read the result)
• The software of the embedded DSP can be downloaded
from the main I2C-bus or from a dedicated I2C-bus
connected to an external slave I2C-bus EEPROM
• An internal bidirectional switch enables the tuner to be
programmed through the chip and then switch-off the
link in order to avoid phase noise distortions due to
I2C-bus traffic.
• A mixer oscillator and a PLL downconverts the RF signal
to intermediate frequency IF1 (36.125 MHz typ.)
• SAW filters eliminate the power of the adjacent channels
around IF1.
IF interface
• It is either an analog IF amplifier when IF1 is sampled
(direct IF: digital downconversion concept) or an analog
IF amplifier followed by a downconversion from IF1 to
IF2 at a few MHz (e.g. 4.57 MHz)
• When this second solution is used, the ADC sampling
clock could be used (after low-pass filtering) as a
reference clock for downconversion (twice the ADC
sampling clock could also be provided)
• The IF amplifier is controlled by the digital AGC of the
chip. A simple RC circuit filters the single bit
(∆Σ modulated) AGC control (VAGC)
• The sampling clock could also be used to control an
external ADC, the inputs to the chip will then be digital
(FI[9:0]).
2001 Nov 08
13
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
PACKAGE OUTLINE
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT317-2
c
y
X
80
A
51
81
50
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
L
31
100
detail X
30
1
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
3.20
0.25
0.05
2.90
2.65
0.25
0.40
0.25
0.25
0.14
20.1
19.9
14.1
13.9
0.65
24.2
23.6
18.2
17.6
1.95
1.0
0.6
0.2
0.15
0.1
Z D (1) Z E(1)
0.8
0.4
1.0
0.6
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT317-2
2001 Nov 08
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-08-01
99-12-27
MO-112
14
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
2001 Nov 08
15
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, HBGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DATA SHEET STATUS
DATA SHEET STATUS(1)
PRODUCT
STATUS(2)
DEFINITIONS
Objective data
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
2001 Nov 08
16
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
ICs with MPEG-2 functionality  Use of this product in
any manner that complies with the MPEG-2 Standard is
expressly prohibited without a license under applicable
patents in the MPEG-2 patent portfolio, which license is
available from MPEG LA, L.L.C., 250 Steele Street, Suite
300, Denver, Colorado 80206.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2001 Nov 08
17
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
NOTES
2001 Nov 08
18
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
NOTES
2001 Nov 08
19
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA73
© Koninklijke Philips Electronics N.V. 2001
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/04/pp20
Date of release: 2001
Nov 08
Document order number:
9397 750 08496