PHILIPS PCD5042H

INTEGRATED CIRCUITS
DATA SHEET
PCD5042
DECT burst mode controller
Objective specification
File under Integrated Circuits, IC17
1996 Oct 31
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
CONTENTS
FEATURES
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
BLOCK DIAGRAM
5
PINNING
6
FUNCTIONAL DESCRIPTION
6.1
6.1.1
6.1.2
6.2
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.7
Internal bus and data memory
Internal Bus
Data Memory
Clock generation and correction
Programmable communication controller and
program memory
PCC
PCC functions
Speech interface
12-slot mode
32-slot mode
Muting
Local call
RF interface
Serial receiver
Serial transmitter
Seamless handover
RF control signals
Synthesizer programming
RSSI measurement
Local call switching
Data synchronization
Ciphering machine
Comparator/data slicer on PCD5042HZ
Microcontroller Interface
Function of the microcontroller interface
Microcontroller interrupts
Watchdog
Power-down
Survey of registers
7
LIMITING VALUES
8
CHARACTERISTICS
9
PACKAGE OUTLINES
10
SOLDERING
10.1
10.2
10.3
10.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
11
DEFINITIONS
12
LIFE SUPPORT APPLICATIONS
1996 Oct 31
2
Philips Semiconductors
Objective specification
DECT burst mode controller
1
PCD5042
FEATURES
2
GENERAL DESCRIPTION
• On-chip pre-programmed Communication Controller
with embedded firmware for implementation of Traffic
Bearer Control (TBC), MAC message handling,
scanning, and control of the device’s other functional
units.
The PCD5042 DECT Burst Mode Controller (BMC) is a
custom IC that performs the DECT Physical Layer and
MAC Layer time-critical functions, for use in DECT base
station products which comply with the following
standards:
• Fixed Part (FP) modes
• DECT CI part 2: Physical layer (DE/RES 3001-2)
• TDMA frame (de)multiplexing
• DECT CI part 3 : Medium Access Control layer
(DE/RES 3001-3)
• Encryption
• DECT CI part 7: Security features for DECT
(DE/RES 3001-7)
• Scrambling
• CRC generation and checking
• DECT CI part 9: Public Access Profile
(DE/RES 3001-9).
• Beacon transmission control (by P00 packets)
• On-chip comparator for receive data slicer function (only
available in the LQFP80 package)
The PCD5042 has interfaces to:
• Up to 4 ADPCM CODECs in a simple base station (with
up to 4 analogue lines) without glue logic
• Switches up to12 active speech channels from speech
interface to 1152 kbits/s. radio interface, and vice versa
• n x 64 kbits/s highway, where n = 1 to 32, for systems
requiring more than 4 connections to the network
• Dual channel speech/data capability
• RSSI measurement, with on-chip 6-bits peak/hold
detector
• A radio transceiver; the interface is fully decoded, and
includes power-down signals
• Local call switching for up to 6 internal calls on RF
side/local call switching on speech side.
• An external microcontroller.
• Quality control report
The PCD5042 is designed to be connected to an ADPCM
CODEC (Philips’ PCD5032, for example) and an
80C51-type microcontroller. Other microcontrollers (e.g.
68000) and CODECs can also be supported.
• Digital Phase Locked Loop (DPLL)
• Synchronization (handset to active bearer, base station
to cluster of RFPs)
• Seamless handover procedure
• Fast (hardware) and slow (software) mute function
• 1 kbyte extended RAM memory
• On-chip crystal oscillator (13.824 MHz)
• Programmable microcontroller clock frequency
• Programmable interrupts
• Watchdog with two programmable time-outs
• Low power consumption in standby mode
• Low supply voltage (2.7 to 5.5 V)
• SACMOS technology.
3
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
PCD5042H
QFP64
PCD5042HZ
LQFP80 plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm
1996 Oct 31
plastic quad flat package; 64 leads (lead length 1.95 mm); body
14 × 20 × 2.8 mm
3
VERSION
SOT319-2
SOT315-1
Philips Semiconductors
Objective specification
DECT burst mode controller
4
PCD5042
BLOCK DIAGRAM
handbook, full pagewidth
PCD5042
TIMING, CONTROL,
CLOCK
GENERATION
DECT
BURST MODE
CONTROLLER
to CODEC/
Highway
SPEECH
INTERFACE
3-wire synthesizer
interface
internal
bus
RF INTERFACE
PROGRAMMABLE
COMMUNICATION
CONTROLLER (PCC)
MICROCONTROLLER
INTERFACE
PCC
PROGRAM MEMORY
4 kbyte ROM
Rx/Tx data
8051/68000
interface
DATA MEMORY
2 kbyte RAM
MBH741
Fig.1 Block diagram.
5
PINNING (see Figs 2 and 3)
PIN
SYMBOL
AD0 to AD7
TYPE(2)
QFP64
LQFP80(1)
1 to 8
80, 1, and
3 to 7
I/O
DESCRIPTION
address/Data bus
ALE
9
9
I
address latch enable
CS
10
11
I
chip select (active LOW)
13 to 11
14 to 12
I
address bus
VDD1
14
15
P
positive supply 1
PROC_CLK
15
16
O
microcontroller clock; programmable from fCLK/64 to fCLK,
where fCLK is the crystal oscillator frequency
VSS1
16
17
P
negative supply 1
XTAL1
17
20
I
crystal oscillator input
XTAL2
18
21
O
crystal oscillator output
VSS2
19
22
P
negative supply
RESET_OUT
20
23
O
watchdog timer output; intended to reset the external
microcontroller when expired
RD
21
24
I
read (active LOW)
WR
22
25
I
write (active LOW)
RDY
23
26
O
ready signal (active LOW), to initiate wait states in the
microcontroller (open drain)
A8 to A10
1996 Oct 31
4
Philips Semiconductors
Objective specification
DECT burst mode controller
PIN
SYMBOL
QFP64
LQFP80(1)
PCD5042
TYPE(2)
DESCRIPTION
INT
24
27
O
interrupt (active LOW)
CLK100
25
29
O
100 Hz frame timer
VSS3
26
31
P
negative supply 3
DO
27
32
O
3-state data output on the speech interface
FS3
−
33
I/O
8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
FS1
28
34
I/O
8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
FS4
−
35
I/O
8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
FS2
29
36
O
8 kHz framing signal to ADPCM CODEC 2 in the base station
mode
DI
30
37
I
data input on the speech interface
DCK
31
38
O
simple base + handset; 1152 kHz data clock (output),
otherwise 2048 kHz data clock (input) signal
CLK3
32
39
O
3.456 MHz clock (nominal value, used to adjust system
timing)
ANT_SW
33
40
O
selects one of two antennas
T_ENABLE
34
41
O
Transmitter Enable (active LOW)
T_POWER_RMP
35
43
O
Transmitter Power Ramp control
RMT_STAT
36
44
I
serial 8-bit data can be read in for each slot; REMote radio
SYNTH_LOCK
37
45
I
lock indication from synthesizer
VSS4
38
46
P
negative supply 4
REF_CLK
39
47
O
reference frequency for the synthesizer, i.e. the crystal
oscillator clock fCLK
VDD2
40
48
P
positive supply 2
S_ENABLE
41
49
O
synthesizer enable
S_CLK
42
51
O
clock signal, to be used with S_DATA
S_DATA
43
52
O
serial data to the synthesizer
S_POWER_DWN
44
53
O
synthesizer power-down control
VCO_BND_SW
45
54
O
VCO bandswitch control signal
1200 HZ
46
55
O
control signal for dual synthesizer schemes
T_DATA
47
56
O
serial output data to transmitter
SET_OFF_IN
48
57
I
switches off the crystal oscillator, and prevents all RF signals
from becoming active
TEST1
49
58
I
selects various test modes.; normal operation set to 0
RSSI_AN
50
60
I
analog signal (for basic DECT systems), peak signal strength
measured after a lowpass filter
TEST2
51
−
I
selects various test modes; normal operation set to 0
TEST3
52
61
I
selects various test modes; normal operation set to 0
R_DATA
53
63
I
receive data
1996 Oct 31
5
Philips Semiconductors
Objective specification
DECT burst mode controller
PIN
SYMBOL
QFP64
LQFP80(1)
PCD5042
TYPE(2)
DESCRIPTION
R_ENABLE
54
64
O
receiver enable (active LOW)
R_POWER_DWN
55
65
O
receiver power-down
COMP_NE
−
66
I
digital input comparator not_enable (active LOW)
SLICE_CTR
56
67
O
slice time constant control
COMP_OUT
−
68
O
digital comparator output
VDD3
57
69
P
positive supply 3
VSS5
58
70
P
negative supply 5
COMP_INM
−
71
I
analog comparator input negative
VREF
59
72
I
reference input for the A/D converter
COMP_INP
−
73
I
analog input positive
VDD(RAM)
60
74
P
power supply for data RAM
SYNCPORT
61
76
I/O
in the base station the signal is the SYNCPORT
RESET
62
77
I
BMC master reset signal
MEM_SEL
63
78
I
selects PCC program memory at microcontroller interface
EN_WATCHDOG
64
79
I
enable watchdog input; when HIGH, the watchdog timer of
the BMC is enabled
Notes
1. Un-referenced pins for the LQFP80 package are not connected. FS3, FS4 and the comparator signals are only
available in the LQFP80 package.
2. All signals which are input or I/O, and which can be floating, need to be pulled up to VDD or down to VSS in order to
protect the device against cross-currents. Exceptions are VREF and RSSI_AN, which do not have to be protected.
1996 Oct 31
6
Philips Semiconductors
Objective specification
52 TEST3
53 R_DATA
54 R_ENABLE
55 R_POWER_DWN
56 SLICE_CTR
57 VDD3
58 VSS5
59 VREF
60 VDD(RAM)
PCD5042
61 SYNCPORT
62 MEM_RESET
handbook, full pagewidth
63 MEM_SEL
64 EN_WATCHDOG
DECT burst mode controller
AD0 1
51 TEST2
AD1 2
50 RSSI_AN
AD2 3
49 TEST1
AD3 4
48 SET_OFF_IN
AD4 5
47 T_DATA
AD5 6
46 1200_Hz
AD6 7
45 VCO_BND_SW
AD7 8
44 S_POWER_DWN
ALE 9
43 S_DATA
PCD5042H
CSN 10
42 S_CLK
AD10 11
41 S_ENABLE
AD9 12
40 VDD2
AD8 13
39 REF_CLK
38 VSS4
VDD1 14
PROC_CLK 15
37 SYNTH_LOCK
VSS1 16
36 RMT_STAT
XTAL1 17
35 T_POWER_RMP
XTAL2 18
34 T_ENABLE
VSS2 19
CLK3 32
DCK 31
DI 30
FS2 29
FS1 28
DO 27
VSS3 26
CLK100 25
INT 24
RDY 23
WR 22
RD 21
RESET_OUT 20
33 ANT_SW
MBH743
Fig.2 Pin configuration, PCD5042H (QFP64 package).
1996 Oct 31
7
Philips Semiconductors
Objective specification
61 TEST2
62 TEST3
63 R_DATA
64 R_ENABLE
65 R_POWER_DWN
66 COMP_NE
67 SLICE_CTR
68 COMP_OUT
69 VDD3
70 VSS5
71 COMP_INN
72 VREF
PCD5042
73 COMP_INP
74 VDD(RAM)
75 n.c.
76 SYNCPORT
77 RESET
78 MEM_SEL
80 AD0
handbook, full pagewidth
79 EN_WATCHDOG
DECT burst mode controller
AD1
1
60 RSSI_AN
n.c.
2
59 n.c.
AD2
3
58 TEST1
AD3
4
57 SET_OFF_IN
AD4
5
56 T_DATA
AD5
6
55 1200_Hz
AD6
7
54 VCO_BND_SW
AD7
8
53 S_POWER_DWN
ALE
9
52 S_DATA
51 S_CLK
n.c. 10
PCD5042HZ
CSN 11
50 n.c.
49 S_ENABLE
AD10 12
AD9 13
48 VDD2
AD8 14
47 REF_CLK
46 VSS4
VDD1 15
PROC_CLK 16
45 SYNTH_LOCK
44 RMT_STAT
VSS1 17
n.c. 18
43 T_POWER_RMP
n.c. 19
42 n.c.
41 T_ENABLE
Fig.3 Pin configuration, PCD5042HZ (LQFP80 package).
1996 Oct 31
8
ANT_SW 40
CLK3 39
DCK 38
DI 37
FS2 36
FS4 35
FS1 34
FS3 33
DO 32
VSS3 31
n.c. 30
CLK100 29
n.c. 28
INT 27
RDY 26
WR 25
RD 24
RESET_OUT 23
VSS2 22
XTAL2 21
XTAL1 20
MBH745
Philips Semiconductors
Objective specification
DECT burst mode controller
6
PCD5042
Nominally, the frequency on pin CLK3 is 3.456 MHz. This
frequency is obtained by dividing the crystal frequency by
4. Sometimes, the crystal frequency will be divided by 3
or by 5, to synchronize the combination of the ADPCM
CODEC and the device to an external source. External
synchronization for base station applications is achieved
as follows:
FUNCTIONAL DESCRIPTION (see Fig.1)
The PCD5042 has dedicated hardware blocks containing
logic for time-critical functions requiring bit or byte-time
accuracy. Other functions requiring only slot-time
accuracy are performed by software in the
Preprogrammed Communication Controller (PCC). This
approach offers maximum flexibility during prototyping.
6.1
6.1.1
• Master base station. The master base station provides
a 100 Hz signal to slave base stations on pin
SYNCPORT. If the PCD5042 is connected to a digital
interface (32-slot mode speech interface), the external
synchronization will be done on the incoming 8 kHz
signal. If it is connected to an analog line (12-slot mode
speech interface), it will use its own crystal oscillator as
reference.
Internal bus and data memory
INTERNAL BUS
The function of the internal bus is:
• To provide access for all functional blocks to the
common data memory
• To provide access for the microcontroller-interface and
the PCC to all other functional blocks.
• Slave base station. The slave base station will use the
incoming SYNCPORT signal as synchronization
reference.
All functional blocks (speech-interface, RF-interface,
microcontroller-interface and PCC) can autonomously use
the internal bus to communicate with the common data
memory.
6.3
A bus controller is used to handle the bus priority
mechanism. When several blocks request access
simultaneously, the request with the highest priority is
handled first.
6.1.2
6.3.1
DATA MEMORY
6.3.2
PCC FUNCTIONS
The most important functions of the PCC are to:
• Perform the appropriate actions on received messages:
PMID and FMID checking, RFPI checking, TBC
handling
Clock generation and correction (see Fig.4)
The device has an on-chip 13.824 MHz crystal oscillator.
From this source, a few frequencies are derived for internal
and external use. Frequencies generated for external use
are:
• Prepare A-field messages for transmission
• Prepare the RF-interface for the coming slot
• Perform the procedures for RSSI and set-up scan,
maintain scan counters and timers, assemble the RSSI
field in the common data memory
• 13.824 MHz for the synthesizer reference
(pin REF_CLK). This output is only provided if the
synthesizer power-down control (output on
pin S_POWER_DWN) is not selected.
• Filter events and indicate them to the microcontroller by
interrupt.
• 0.144 to 13.824 MHz for the microcontroller clock
(pin PROC_CLK)
• 3.456 MHz for the ADPCM CODEC (pin CLK3)
• 1200 Hz (pin 1200_HZ) for dual synthesizer switching
• 100 Hz (pin CLK100) indicates start of frame.
1996 Oct 31
PCC
The PCC is a RISC-type controller and is used to control
functions which are slot-time accurate. It is well suited for
bit manipulation, and runs at a clock frequency of
6.912 MHz (equivalent to 3.4 Mips). After finishing a task,
it switches to a power saving state, from which it returns
after a pre-programmed time.
A large part of the data memory is used for the bit rate
adaptation between the DECT radio interface and the
speech interface. The data memory also acts as the main
communication interface between the external
microprocessor and the PCC.
6.2
Programmable communication controller and
program memory
9
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
13.824 MHz system clock
handbook, full pagewidth
2
6.912 MHz system clock
4 (±1)
clock corrections in this level
unless disabled PCD5041's mode register
3.456 MHz system
clock for ADPCM codec
3
1152 kHz
system/bit clock
bit counter
480
slot counter
24
144
FSx signals
(8 kHz)
slot counter
100 Hz
frame sync
COMPARATOR
16
MBH708
'SYNC' event
Fig.4 Internal clocking scheme of the PCD5042.
6.4
signals can be used (FS1 to FS4). When more CODECs
are to be connected, the FS5 to FS12 signals have to be
generated externally. When using the framing signals
FS1 to FS4, no interface logic is required when using the
PCD5032 ADPCM CODEC.
Speech interface
The speech interface block performs the following
functions:
• Connection to a 1152 kbits/s interface in a handset and
a simple base station in the so called ‘12 slot mode’
A speech-slot control table is used to determine where to
store/fetch speech data for transmission and reception.
The hardware speech-interface is capable of addressing
the right speech buffer for the relevant speech slot, and will
maintain a counter carrying the offset to the correct
stored/fetched address.
• Connection to a n x 64 kbits/s interface in base stations
in the so called ‘32 slot mode’
• Autonomous storing/fetching of ADPCM speech data
in/from the PCD5042’s common data memory, using
internal addressing logic
• Muting of speech data
6.4.2
• Local call.
6.4.1
The 32-slot mode is used to connect the PCD5042 to a
digital interface with a data rate of n × 64 kbits/s; where
n = 1 to 32 is the number of speech slots. This equates to
data rates from 64 kbits/s to 2048 kbits/s.
Up to 12 of the 32 speech slots can be used
simultaneously. The same kind of speech-slot control table
used in the 12-slot mode is used for the 32-slot mode.
12-SLOT MODE
The 12-slot mode is selected if up to 4 ADPCM CODECs
are connected to the PCD5042, where the PCD5042 is the
master of these CODECs. In a handset, or in a simple
base stations which is connected with up to 4 analog lines
to the public network, the PCD5042 is master of the
CODECs. Each CODEC is connected with a separate
framing reference signal (FS1 to FS4) to the PCD5042. In
the QFP64 package, 2 framing signals FS1 and FS2 are
available, whereas in the LQFP80 package 4 framing
1996 Oct 31
32-SLOT MODE
6.4.3
MUTING
Due to various reasons the quality of the incoming speech
data may be degraded significantly. By muting the speech
10
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
data, these disturbances are not audible (or are less
audible) to the user. The PCD5042 performs two types of
muting:
6.5.1
The serial receiver processes the data, which comes from
the RF section, and which is already filtered by the
synchronization part. The data is latched, using the
recovered data clock.
• Fast muting
• Slow muting.
The serial receiver will collect the complete A-field and
B-field and store it in the common data memory. Before the
A-field is received, the A-field start address is programmed
by the PCC. Upon reception of A-field nibbles, the address
is updated by the serial receiver. Meanwhile, the PCC will
program the B-field start address.
Fast muting, which is performed by the PCD5042
automatically, is nothing more than a repetition of the
previously received frame (80 speech samples) to the
ADPCM CODEC. It is issued if no Sync word was
detected. Slow muting is issued by the microcontroller,
after having detected a degradation of quality. A slow mute
is implemented as a continuous ‘0000’ nibble transmission
to the ADPCM CODEC, until slow mute is released.
6.4.4
In Fig.6 the data flow in the serial receiver is shown. Note
that almost no decoding of messages is required. Only the
header of the A-field needs to be decoded to check if a
ciphered message is being received or transmitted, which
requires the ciphering to be switched on in the A-field also.
LOCAL CALL
A local call option is implemented, in order to loopback
data from one CODEC to another CODEC, and vice versa,
see Fig.5.
6.5.2
0
1
0
1
0
1
DO
1
SERIAL TRANSMITTER
The serial transmitter performs the reverse of the receiver
functions. Several blocks used in the receiver are also
used in the transmitter. Amongst these are the
CRC-generators, the scrambler, and the address
registers. Figure 7 shows the serial transmitter structure.
handbook, halfpage
0
SERIAL RECEIVER
By transmitting the X-CRC twice, the Z-field is transmitted.
The handling of the address registers is the same for the
transmitter. Transmission of the synchronization sequence
(S-field) is done using the same method as the A-field and
B-field. The S-field is stored in the common data memory
and will be fetched by the transmitter, just before
transmission.
DI
speech slots
speech buffer
pair
Two additional functions are not shown in Fig.7:
MBH710
• In the handset the data in the serial transmitter may be
advanced by a programmable number of bit periods.
This is done to compensate for the delay in the RF
section
Fig.5 Local call switching on speech interface.
6.5
• The transmitted data can be inverted (using a switch in
the PCD5042 mode register), in order to connect the
PCD5042 to VCOs requiring negative modulation.
RF interface
Most of the functions performed by the RF interface are
under control of the PCC. Specifically, the processing of
non-speech data and the programming of functions and
registers is done via the PCC.
1996 Oct 31
11
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
handbook, full pagewidth
DATA MEMORY
DATA MEMORY READ CONTROL
nibble-parallel
bit-serial
DE-CIPHER
CIPHER
CONTROL
other
ok
DE-CIPHER
R-CRC
cs
MUX
MUX
Cs-DEC.
Bprotect
UNSCRAMBLE
ok
ok
R-CRC
X-CRC
A-MAP
B-MAP
D-MAP
MBH737
D00
D32
Fig.6 Serial receiver structure.
handbook, full pagewidth
DATA MEMORY
DATA MEMORY READ CONTROL
nibble-parallel
bit-serial
CIPHER
CIPHER
CIPHER
CONTROL
other
R-CRC
cs
MUX
MUX
Cs-DEC.
Bprotect
UNSCRAMBLE
R-CRC
X-CRC
A-MAP
B-MAP
D-MAP
MBH736
D00
D32
Fig.7 Serial transmitter structure.
1996 Oct 31
12
Philips Semiconductors
Objective specification
DECT burst mode controller
6.5.3
PCD5042
To program various types of synthesizers, a 3-byte shift
register is present. Three data formats are supported:
8, 16 or 24 bit words can be selected. The transfer of data
from a frequency table in the common data memory to the
shift register is under control of the PCC.
SEAMLESS HANDOVER
Seamless handover guarantees that when speech
information is switched from one slot to another, no speech
samples are lost, added or displaced. Seamless handover
is achieved in the RF interface by:
• Using a look-up table containing the correct start
addresses of the B-fields in the data memory
6.5.6
The RSSI measurement in the PCD5042 RF-interface
block is done in 3 parts: a peak/hold detector, a 6-bit A/D
converter, and an RSSI control unit, which controls the
peak/hold detector and the A/D converter. Once per slot
time, a sample is fetched by the PCC and saved in the
appropriate area of the common data memory.
• The RF receive and transmit blocks move data to/from
the data memory block in 4-bit nibbles.
6.5.4
RF CONTROL SIGNALS
The timing of the control signals to the RF section is fixed,
but such that an RF delay between 1.5 and 7 µs can be
tolerated. Only the transmitter ramp signal and the
synthesizer enable are programmable within certain limits.
6.5.5
RSSI MEASUREMENT (see Fig.8)
If the radio receiver is active in a particular time slot, the
RSSI value will automatically be measured in that slot.
Adjustment to the RSSI_AN input level can be made with
VREF.
SYNTHESIZER PROGRAMMING
To program a synthesizer, a 3-wire serial interface is used.
The signals on this interface are:
• S_ENABLE (enable)
• S_CLK (clock)
• S_DATA (data).
RF-INTERFACE
handbook, full pagewidth
VREF
RSSI_AN
RSSI value
filtered width
= 30 µs
(τ =10 to 40 µs)
PEAK
HOLD
RSSI_AN
6
6-BIT
A/D
RSSI
CTRL
(HW)
RSSI
PROCESSING
(SW in PCC)
start_AD
write in memory
RSSI_CTR
MBH711
Fig.8 RSSI measurement path.
1996 Oct 31
internal
bus
13
Philips Semiconductors
Objective specification
DECT burst mode controller
6.5.7
PCD5042
Bit synchronization is done using a Digital PLL (DPLL),
with an oversampling factor of 12, i.e. the DPLL is running
at 12 times the data rate. The output from the DPLL is a
receive clock signal (RxC), which acts as the enable for a
20-bit shift register.
LOCAL CALL SWITCHING (see Fig.9)
The PCD5042 provides a local call switching function in
the base station. It will store incoming speech nibbles in
the common data memory, in the area reserved for that
particular receive slot. Then, during the transmit phase, it
passes the start pointer of the same data memory area to
the transmit block. Thus, the speech data is echoed to the
other user. To handle quality degradation for local calls, a
mute can be performed at the RF side of the speech buffer.
6.5.8
Sync word detection is achieved by checking the incoming
data pattern with the expected synchronization field
pattern, using a correlator.
The correlator has a programmable threshold, so it can
accept bit errors in the sync field pattern up to the
threshold level. Furthermore, the correlator window is
programmable. This means that ‘SlotSync’, which
indicates the slot synchronization event, can be detected
only during a certain period (the time window).
DATA SYNCHRONIZATION (see Fig.10)
The data synchronization is done in 2 phases:
• Bit synchronization
• Sync word detection.
handbook, full pagewidth
RF slots
Rx1
Rx2
Tx1
Tx2
MBH712
speech buffers
in data memory
Fig.9 Local call switching on the RF-side.
13.824 MHz
handbook, full pagewidth
R_DATA
(1152 kbits/s)
filtered
data in
FILTER
R×C
DPLL
EN
D
XOR
20-BIT SHIFT
REGISTER
Q16 to Q19
Q0 to Q15
base/handset
to serial
receiver logic
threshold
correlator
window
MBH713
CORRELATOR
(E98A)
SYNC
CHECK
(1010)
SlotSync
DPLL_sync
Fig.10 Schematic of the receiver synchronization part.
1996 Oct 31
14
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
The ‘DPLL_sync’ indication should only be used, when
‘SlotSync’ is active. It indicates that the last 4 bits of the
pre-amble field (the training sequence) are received
correctly, and thus indicates that the DPLL was in lock
(synchronized) in time. If the ‘SlotSync’ is active, and the
‘DPLL_sync’ is not, then a sliding interferer might have
been detected.
automatically by the cipher machine. The contents of the
memory space where IV and key are found, are the
responsibility of the PCC, and the external
microprocessor.
6.5.10
The PCD5042HZ contains a comparator/data slicer.
The comparator is a stand-alone circuit. No connections
other than power supply are made internally.
The comparator can be used as a data slicer for the
receiver input. The delay requirements listed in Chapter 8
were derived from this application. Another use of the
comparator is in a successive approximation A/D
converter to indicate battery low-voltage condition, or in a
power-on-reset circuit.
If ‘SlotSync’ is not detected, effectively no data is received
in that slot. This implies a ‘fast mute’ because speech data
received in the previous frame is not destroyed.
6.5.9
CIPHERING MACHINE
The description of the cipher machine is subject to
confidentiality. The specification of its algorithms are
delivered by ETSI under the terms of a Non-Disclosure
Agreement.
When the signal COMP_NE is LOW the comparator is
enabled. When COMP_NE is HIGH the comparator is
disabled, and the circuit consumes no power. If the
comparator is used as a data slicer for the receiver input,
the R_DATA is connected to COMP_OUT, the COMP_NE
is connected to R_ENABLE, both connection are done
externally. The pin COMP_INP is connected to the RF
mixer. A proper bias voltage (from the slicer time constant
control circuit) is connected to COMP_INM. Another use of
the comparator is in a successive approximation A/D
converter for battery voltage detection.
The cipher machine is under control of the TBC, which is
implemented in the PCC. The cipher machine generates
2 fields of ciphering bits:
• A_cipher (40 bits) for A-field messages (ciphers tail
only)
• B_cipher (320 bits) for speech in B-field.
The transmitted ciphered bits are then:
• A_ciphered: = A XOR A_cipher
• B_ciphered: = B XOR B_cipher.
The pins are protected against ESD damaging, with a
protection diode to the positive and negative supply rail.
The input pin COMP_NE has a pull-up resistor which
keeps the comparator in power-down mode by default.
On reception by the peer end point, deciphering consists
of the same operation thanks to the synchronous
generation of A_cipher and B_cipher.
handbook, halfpage
KEY
64 BITS
handbook, halfpage
A_cipher
(40 bits)
COMP_INP
COMP_OUT
CIPHER
MACHINE
KEY
64 BITS
COMPARATOR/DATA SLICER ON PCD5042HZ
COMP_INM
B_cipher
(320 bits)
COMP_NE
MBH715
MBH714
Fig.12 Circuit schematic of the comparator/data
slicer.
Fig.11 Cipher machine and its sources.
The cipher machine is time-multiplexed on a slot basis.
Initially, the Initialisation Vector (IV) and the key must be
loaded into the cipher machine. Transfer of the IV and key
from the common data area to the cipher machine is done
1996 Oct 31
15
Philips Semiconductors
Objective specification
DECT burst mode controller
6.6
6.6.1
PCD5042
6.6.3
Microcontroller Interface
The PCD5042 is equipped with a watchdog timer, which
generates a reset towards an external device (e.g. a µC)
after time-out. Two (fixed) time-out periods can be
programmed; 1.25 s and 82 s. The watchdog function can
be disabled by using the EN_WATCHDOG input pin.
FUNCTION OF THE MICROCONTROLLER INTERFACE
The microcontroller Interface will provide the following
services.
• Direct interface to processors which have an
INTEL-8051 compatible interface
• General interface to processors that can handle ‘wait
states’ e.g. 68000-family; in this case glue logic is
required
6.6.4
• A programmable interrupt register
The 13.824 MHz clock is never switched off. The Timing
Control, microcontroller interface, and Bus Controller keep
running, in order to remain synchronous with a base
station, and to keep the wake-up circuitry active. During
power-down the external microcontroller has still access to
the common data area.
• A watchdog timer with time-out periods of
1.25 or 82 seconds, depending on the programming.
The microcontroller can address the PCD5042 as any
other RAM memory connected to the microcontroller bus.
By writing the ‘Interface-Mode Register’, the
microcontroller can select the interface mode and its own
clock frequency.
6.7
Survey of registers
For a survey of all addresses occupied refer to
Tables 1 and 2. Some of the address locations are used
differently for read and write. The addresses 000 to 7DF
are occupied by RAM memory, while the upper 32 bytes
are assigned to the hardware registers. A part of the RAM
memory is allocated for use by the RF block, cipher block,
and the speech interface.
MICROCONTROLLER INTERRUPTS
The function of microcontroller Interrupts is to make
optimal use of the microcontroller’s processing power, and
to achieve optimal cooperation between time-critical tasks
and less time-critical tasks both executed in software.
Three registers are available to handle interrupts. These
are:
• Interrupt Event Register
• Interrupt Enable Register
• Interrupt Reset Register.
These registers are to be regarded together.
Corresponding bits in these registers relate to one and the
same event. Bits in the Interrupt Event Register are set by
the PCC and are to be reset by the external processor by
writing ‘1’s in the corresponding bits in the Interrupt Reset
Register. The mask in the Interrupt Enable Register
enables the interrupt if corresponding events do occur.
1996 Oct 31
POWER-DOWN
The PCC may switch off the 6.912 MHz internal clock, to
enter a power saving mode. All blocks, running on this
clock are then switched off (i.e. RF-interface, cipher block,
speech interface, PCC). This is called the power-down
state, and is only used in the handset mode.
• Processor clock signal of which the frequency is
programmable in order to adjust instantaneously
processor performance to processor work load
6.6.2
WATCHDOG
16
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
Table 1 Hardware register addresses
ADDRESS
WRITE
Table 2
READ
Fixed RAM locations
ADDRESS
ENTRY
7E0
−
−
740 to 747
cipher key vector #0
7E1
S-DATA1
−
748 to 74F
cipher key vector #1
7E2
S-DATA2
−
750 to 757
cipher key vector #2
7E3
S-DATA3
RMT-STAT
758 to 75F
cipher key vector #3
7E4
−
RF-STATUS
760 to 767
cipher key vector #4
7E5
B-field-shift
−
768 to 76F
cipher key vector #5
7E6
B-field-loc.
−
770 to 777
cipher key vector #6
7E7
A-field-loc.
−
778 to 77F
cipher key vector #7
7E8
window-wide-off
−
780 to 787
cipher key vector #8
7E9
window-wide-on
−
788 to 78F
cipher key vector #9
7EA
window-narrow-off
−
790 to 797
cipher key vector #10
7EB
window-narrow-on
−
798 to 79F
cipher key vector #11
7EC
T-power-rmp-on
−
7A0 to 7A7
cipher init vector
7ED
synth-off
−
7A8 to 7AA
not used
7EE
RF-control-port
sync-status
7AB
XZ field buffer
7EF
slot-cnt-off
slot-counter-copy
7AC to 7AF
S-field buffer
7F0
frame-cnt-ref
RSSI
7B0 to 7BB
cipher-slot-control-table
7F1
sync-ref-preset
bit-counter-copy1
7BC to 7BF
not used
7F2
bit-counter-preset
bit-counter-copy2
7C0 to 7DF
speech-slot-control-table
7F3
frame-counter
frame-counter
7F4
slot-counter
slot-counter
7F5
sync-control
sync-control
7F6
BMC-mode
BMC-mode
7F7
correlator-threshold measure
7F8
watchdog-1
−
7F9
watchdog-2
−
7FA
−
−
7FB
−
−
7FC
interrupt-event
interrupt-event
7FD
interrupt-enable
interrupt-enable
7FE
interrupt-reset
−
7FF
controller mode
controller mode
1996 Oct 31
17
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
7 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+6.5
V
Vi
all input voltages
−0.5
VDD + 0.5
V
II
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
Ptot
total power dissipation
−
+500
mW
PO
power dissipation per output
−
30
mW
IDD
supply current
−100
+130
mA
ISS
ground current
−100
+130
mA
Tstg
storage temperature range
−55
+100
°C
Tj
operating junction temperature
−
90
°C
8
CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
General
Tamb
operating ambient temperature
−25
−
+70
°C
VDD
supply voltage
2.7
−
5.5
V
VDD(ret)
RAM retention voltage
1.0
−
VDD
V
IDD
operating supply current
note 1
−
6
12
mA
IDD(stb)
standby supply current
note 2
−
1
3
mA
clock input duty cycle
All inputs LOW except WRN;
XTAL1 running at 14 MHz
45
−
55
%
0
−
0.3VDD
V
Digital I/O
VIL
LOW level input voltage
VOL
LOW level output voltage
0
−
0.3VDD
V
VIH
HIGH level input voltage
0.7VDD
−
VDD
V
VOH
HIGH level output voltage
0.7VDD
−
VDD
V
ILI
input leakage current
1.0
µA
IO(source)
output source current
VDD = 3.6 V;
0.4 V ≤VO ≤ VDD − 0.4 V
2.0
5.0
−
mA
IO(sink)
output sink current
VDD = 3.6 V;
0.4 V ≤VO ≤ VDD − 0.4 V
2.0
5.0
−
mA
IRDYN(sink)
RDYN output sink current
VDD = 3.6 V; VO = 0.4 V
2.0
5.0
−
mA
VDD = 5.0 V; VO = 0.4 V
−
6.0
−
mA
n = 1 to 32
−
n × 64 −
kHz
−
8
−
kHz
fDCK
DCK input frequency
fFS1
FS1 input frequency
1996 Oct 31
18
Philips Semiconductors
Objective specification
DECT burst mode controller
SYMBOL
PCD5042
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Oscillator (inputs XTAL1 and XTAL2)
gm
RF
transconductance
VDD = 2.7 V
0.6
−
−
mS
VDD = 3.6 V
−
1.6
−
mS
200
500
feedback resistance
kΩ
RSSI Peak detector (6-bit linear A-D converter, for RSSI measurement on input RSSI_AN)
input level
0
−
VDD
V
Vconv(RSSI_AN) voltage conversion range
0
−
VREF
V
Vi(RSSI_AN)
Vi(VREF)
VREF input voltage
Zi(VREF)
VREF input impedance
tconv
conversion time
during power-down high
impedance
integral non-linearity
differential non-linearity
Zi(RSSI_AN)
note 3
input impedance RSSI_AN
1.0
3.0
VDD
V
−
50
−
kΩ
18.4
−
−
µs
−
−
4
LSB
−
0.2
1.5
LSB
−
1
−
MΩ
PCD5042HZ comparator characteristics
IDD(stb)(comp)
supply current (standby)
note 4
−
10
−
µA
IDD(idle)(comp)
supply current (idle)
VDD = 3.0 V; note 4
−
135
−
µA
IDD(1MHz)
supply current (1 MHz)
VDD = 3.0 V; note 4
−
350
−
µA
ILI(comp)
input leakage current
note 5
−
−
1
µA
Ci
input capacitance
note 5
−
10
−
pF
Rpu
pullup resistance
note 6
−
200
−
kΩ
Vcm
input common mode range
note 7
1.0
−
VDD − 0.5 V
Vos
max. input offset voltage
note 8
−
5
−
mV
tpd
propagation delay
note 9
−
100
200
ns
∆tpd
delay difference
note 8 and 9
−
10
−
ns
VOL(comp)
output level LOW
IO = 2 mA
−
−
0.4
V
VOH(comp)
output level HIGH
IO = 2 mA
VDD − 0.4 −
−
V
tr
output rise time
CL = 50 pF
−
15
−
ns
tf
output fall time
CL = 50 pF
−
15
−
ns
ten
enable time
−
−
8
µs
1996 Oct 31
19
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
Notes to the characteristics
1. VDD = 3.0 V; fclk =13.824 MHz; no external load; one speech link active (under typical conditions).
2. VDD = 3.0 V; fclk =13.824 MHz; no external load; after reset.
3. Maximum differential non-linearity at supply voltage 5.5 V and VREF = 1 V.
4. Supply current IDD(stb)(comp) flows when COMP_NE is HIGH.
Supply current IDD(idle)(comp) flows when the comparator is in active mode (COMP_NE is LOW). It is the DC current
of the comparator when it is not switching, and V(COMP_INP) < V(COMP_INM).
The active mode supply current IDD(1MHz) includes the output pulse rate of 1 MHz.
5. For input pins COMP_INP, COMP_INM, COMP_NE.
6. For input pin COMP_NE.
7. The minimum input common mode voltage will be measured at DC levels with, COMP_INM at 1 V DC ±30 mV.
The same goes for the maximum input common mode voltage at (VDD − 0.5V).
8. These values are not tested in production, and are based upon theoretical estimates and laboratory tests.
9. The propagation delay tpd is measured from the time the differential input voltage equals the offset voltage, to the
50% point of the output transition. The initial differential input voltage is 100 mV and the propagation delay is
specified for an input overdrive of 30 mV, and a load capacitance of 50 pF. tpd is valid for both the positive and
negative going output transition. The maximum value is valid for the total ranges of temperature, supply voltage and
common mode input voltage. The worst case operation conditions are at the minimum supply voltage, the lowest
operating temperature and the minimum input common mode voltage. The delay difference ∆tpd gives the difference
between tpd for the rising output transition and tpd for the falling output transition and is valid for all operating
conditions. The test method to check the maximum delay difference is by measuring the RMS voltage of the output
signal.
1996 Oct 31
20
Philips Semiconductors
Objective specification
DECT burst mode controller
9
PCD5042
PACKAGE OUTLINES
QFP64: plastic quad flat package;
64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT319-1
c
y
X
51
A
33
52
32
ZE
Q
e
E HE
A
A2
(A 3)
A1
θ
wM
Lp
pin 1 index
bp
L
20
64
detail X
19
1
w M
bp
e
ZD
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
3.3
0.36
0.10
2.87
2.57
0.25
0.50
0.35
0.25
0.13
20.1
19.9
14.1
13.9
1
24.2
23.6
18.2
17.6
1.95
1.0
0.6
1.43
1.23
0.2
0.2
0.1
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT319-1
1996 Oct 31
EUROPEAN
PROJECTION
21
o
7
0o
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
c
y
X
A
60
41
40 Z E
61
e
Q
E HE
A A2
(A 3)
A1
w M
θ
bp
L
pin 1 index
80
Lp
21
detail X
20
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.16
0.04
1.5
1.3
0.25
0.25
0.13
0.18
0.12
12.1
11.9
12.1
11.9
0.5
HD
HE
14.15 14.15
13.85 13.85
L
Lp
Q
v
w
y
1.0
0.7
0.3
0.70
0.58
0.2
0.15
0.1
Z D (1) Z E (1)
θ
1.45
1.05
4
0o
1.45
1.05
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-03-24
95-12-19
SOT315-1
1996 Oct 31
EUROPEAN
PROJECTION
22
o
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
If wave soldering cannot be avoided, the following
conditions must be observed:
10 SOLDERING
10.1
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Even with these conditions:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• Do not consider wave soldering LQFP packages
LQFP48 (SOT313-2), LQFP64 (SOT314-2) or
LQFP80 (SOT315-1).
10.2
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
• Do not consider wave soldering QFP packages
QFP52 (SOT379-1), QFP100 (SOT317-1),
QFP100 (SOT317-2), QFP100 (SOT382-1) or
QFP160 (SOT322-1).
Reflow soldering
Reflow soldering techniques are suitable for all LQFP and
QFP packages.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
10.4
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
10.3
Wave soldering
Wave soldering is not recommended for LQFP or QFP
packages. This is because of the likelihood of solder
bridging due to closely-spaced leads and the possibility of
incomplete solder penetration in multi-lead devices.
1996 Oct 31
Repairing soldered joints
23
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
11 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
12 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Oct 31
24
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
NOTES
1996 Oct 31
25
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
NOTES
1996 Oct 31
26
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5042
NOTES
1996 Oct 31
27
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 1949
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580/xxx
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 247 9145, Fax. +7 095 247 9144
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
647021/00/01/pp28
Date of release: 1996 Oct 31
Document order number:
9397 750 01292