Philips Semiconductors Linear Products Product specification 8-Bit µp-compatible D/A converter NE/SE5018/5019 DESCRIPTION PIN CONFIGURATIONS The NE/SE5018/19 is a complete 8-bit digital-to-analog converter subsystem on one monolithic chip. The data inputs have input latches which are controlled by a latch enable pin. The data and latch enable inputs are ultra-low loading for easy interfacing with all logic systems. The latches appear transparent when the LE input is in the low state. When LE goes high, the input data present at the moment of transition is latched and retained until LE again goes low. This feature allows easy compatibility with most microprocessors. F, N Packages DIGITAL GND 1 DB0(LSB) 2 22 ANALOG GND 21 AMP COMP DB1 3 DB2 4 20 SUM MODE 19 V CC+ 18 V DB3 5 DB4 6 OUT 17 VCC– DB5 7 The chip also comprises a stable voltage reference (5V nominal) and high slew rate buffer amplifier. The voltage reference may be externally trimmed with a potentiometer for easy adjustment of full-scale while maintaining a low temperature coefficient. LE 10 16 DAC COMP 15 BIPOLAR OFFSET R 14 V REFIN 13 V OUT NC 11 12 V REFADJ DB6 8 DB7(MSB) 9 The output of the buffer amplifier may be offset so as to provide bipolar as well as unipolar operation. REF D Package1 DIGITAL GND 1 DB0(LSB) 2 FEATURES • 8-bit resolution • Input latches • Low-loading data inputs • On-chip voltage reference • Output buffer amplifier • Accurate to ± LSB (0.19%) • Monotonic to 8 bits • Amplifier and reference both short-circuit protected • Compatible with 8085, 6800 and many other µPs 24 ANALOG GND 23 AMP COMP DB1 3 DB2 4 22 SUM MODE 21 V DB3 5 DB4 6 20 V OUT 19 NC DB5 7 18 V CC– DB6 8 DB7(MSB) 9 NC 10 LE 11 VREFADJ 12 CC+ 17 DAC COMP 16 BIPOLAR OFFSET 15 NC 14 V REFIN 13 VREFOUT NOTE: 1. SOL and non-standard pinout APPLICATIONS • Precision 8-bit D/A converters • A/D converters • Programmable power supplies • Test equipment • Measuring instruments • Analog-digital multiplication ORDERING INFORMATION TEMPERATURE RANGE ORDER CODE DWG # 22-Pin Ceramic Dual In-Line Package (CERDIP) DESCRIPTION 0 to +70°C NE5018/5019F 0585B 22-Pin Ceramic Dual In-Line Package (CERDIP) -55°C to +125°C SE5018/5019F 0585B 22-Pin Plastic Dual In-Line Package (DIP) 0 to +70°C NE5018/5019N 0409B 22-Pin Plastic Dual In-Line Package (DIP) -55°C to +125°C SE5018/5019N 0409B 24-Pin Small Outline Large (SOL) Package 0 to +70°C NE5018/5019D 0173D August 31, 1994 751 853-0845 13721 Philips Semiconductors Linear Products Product specification 8-Bit µp-compatible D/A converter NE/SE5018/5019 BLOCK DIAGRAM (19) VCC+ VREF (13) OUT INT VREF + – 15k VREF (12) ADJ (10) LE 5k 5k (1) (9) (8) (7) (6) (5) (4) (3) (2) DIGITAL DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 GND MSB LSB LATCHES AND SWITCH DRIVERS (20) SUM NODE (18) + – VOUT 5k AMP (21) COMP (22) ANALOG GND DAC CURRENT OUTPUT DAC SWITCHES (14) 5k VREF IN 5k + – DAC (16) COMP (15) BIPOLAR OFFSET VCC– (17) ABSOLUTE MAXIMUM RATINGS RATING UNIT VCC+ SYMBOL Positive supply voltage 18 V VCC- Negative supply voltage -18 V VIN Logic input voltage 0 to 18 V VREF IN Voltage at VREF input 12 V VREF ADJ Voltage at VREF adjust 0 to VREF V VSUM Voltage at sum node 12 V IREF SC Short-circuit current to ground at VREF OUT Continuous IOUTSC Short-circuit current to ground or either supply at VOUT Continuous PD TA PARAMETER Maximum power dissipation, TA=25°C (still-air)1 F package 1740 mW N package 2190 mW D package 1600 mW SE5018 -55 to +125 °C NE5018 0 to +70 °C -65 to +150 °C 300 °C Operating temperature range TSTG Storage temperature range TSOLD Lead soldering temperature (10 seconds) NOTES: 1. Derate above 25°C at the following rates: F package at 13.9mW/°C N package at 17.5mW/°C D package at 12.8mW/°C August 31, 1994 752 Philips Semiconductors Linear Products Product specification 8-Bit µp-compatible D/A converter NE/SE5018/5019 DC ELECTRICAL CHARACTERISTICS VCC+=+15V, VCC-=-15V, SE5018. -55°C≤TA≤125°C, NE5018. 0°C≤TA≤70°C, unless otherwise specified. 1 Typical values are specified at 25°C. SYMBOL PARAMETER TEST CONDITIONS NE/SE5018 NE/SE5019 UNIT Min Typ Max Min Typ Max Resolution 8 8 8 8 8 8 Monotonicity 8 8 8 8 8 8 Bits ±0.1 %FS ±0.19 Relative accuracy Bits VCC+ Positive supply voltage 11.4 15 11.4 15 V VCC- Negative supply voltage -11.4 -15 -11.4 -15 V VIN(1) Logic “1” input voltage Pin 1=0V VIN(0) Logic “0” input voltage Pin 1=0V 0.8 V IIN(1) Logic “1” input current Pin 1=0V, 2V<VIN<18V 0.1 10 0.1 10 µA IIN(0) Logic “0” input current Pin 1=0V, -5V<VIN<0.8V -2.0 -10 -2.0 -10 µA Full-scale output Unipolar mode, VREF=5.000V, VFS 2.0 2.0 V 0.8 9.50 10.5 9.50 10.5 V 4.75 5.25 4.75 5.25 V -4.75 -5.25 -4.75 V +30 -30 +30 mV all bits high, TA=25°C +VFS Full-scale output -VFS Negative full scale Bipolar mode, VREF=5.000V all bits high, TA=25°C Bipolar mode, VREF=5.000V, -5.25 all bits low, TA=25°C VZS Zero-scale Output Unipolar mode, VREF=5.000V -30 all bits low, TA=25°C IOS Output short circuit current TA=25°C VOUT=0V PSR+(OUT) Output power supply rejection (+) V-=-15V, 13.5V≤V+≤16.5V, external VREF IN=5.000V PSR-(OUT) Output power supply rejection (-) 15 40 15 40 mA 0.001 0.01 0.001 0.01 %FS %VS 0.001 0.01 0.001 0.01 %FS %VS V+=-15V, -13.5V≤V-≤-16.5V, external VREF IN=5.000V TCFS Full-scale temperature coefficient TCZS Zero-scale temperature coefficient IREF Reference output current IREFSC Reference short circuit current TA=25°C VREF OUT=0V PSR+(REF) Reference power supply rejection (+) PSR-(REF) VREF IN=5.000V 20 20 5 ppm/°C 5 3 ppm/°C 3 mA 15 30 15 30 mA V-=-15V, 13.5V≤V+≤16.5V, IREF=1.0mA 0.003 0.01 0.003 0.01 %VR/%VS Reference power supply rejection (-) V+=-15V, -13.5V≤V-≤16.5V, 0.003 0.01 0.003 0.01 %VR/%VS VREF Reference voltage IREF=1.0mA TA=25°C 5.0 5.25 5.0 5.25 V TCREF Reference voltage temperature coefficient IREF=1.0mA ZIN DAC VREF IN input impedance IREF=1.0mA, TA=25°C ICC+ Positive supply current VCC+=15V ICC- Negative supply current VCC-=-15V -10 -15 -10 -15 mA PD Power dissipation IREF=1.0mA, VCC=±15V 255 435 255 435 mW 4.9 60 NOTES: 1. Refer to Figure 1. August 31, 1994 4.9 753 4.15 60 5.0 5.85 7 14 4.15 ppm/°C 5.0 5.85 kΩ 7 14 mA Philips Semiconductors Linear Products Product specification 8-Bit µp-compatible D/A converter NE/SE5018/5019 AC ELECTRICAL CHARACTERISTICS1 VCC = ±15V, TA = 25°C SYMBOL PARAMETER tSLH tSHL TEST CONDITIONS NE/SE5018/19 TO FROM Settling time ±1/2LSB Input All bits low-to-high2 1.8 µs Settling time ±1/2LSB Input All bits high-to-low3 2.3 µs low-to-high2 Min Typ UNIT Max tPLH Propagation delay Output Input All bits switched 300 ns tPHL Propagation delay Output Input All bits switched high-to-low3 150 ns tPLSB Propagation delay Output Input 1 LSB change2, 3 150 ns transition4 300 ns 150 ns tPLH Propagation delay Output LE Low-to-high tPHL Propagation delay Output LE High-to-low transition5 tS Setup time LE Input 1, 6 100 ns tH Hold time Input LE 1, 6 50 ns 1, 6 150 ns tPW Latch enable pulse width NOTES: 1. Refer to Figure 2. 2. See Figure 5. 3. See Figure 6. 4. See Figure 7. 5. See Figure 8. 6. See Figure 9. 7. For reference currents>3mA, use of an external buffer is required. LE MSB VCC+ LSB 0.47µF 98 76 543 2 10 5.000V MSB LE 0.47µF 19 DIG GND 1 98 76 543 2 10 ANA GND 22 14 VREF IN 5018 0.01µF 2k AMP 21 COMP 5018 12 22pF SUM 20 15 ANA GND 22 13 OUTPUT VOUT 18 DAC COMP 16 17 15 MSB Figure 2. AC Parametric Test Configuration VCC+ LSB 0.47µF 98 76 543 2 10 19 DIG GND 1 ANA GND 22 14 VREF IN 13 VREF OUT 10k 12 VREF ADJ 5018 OUTPUT VOUT 18 80k FULL SCALE ADJUST DAC COMP 16 17 0.01µF 22pF SUM 20 AMP 21 COMP 15 0.1µF 2k 1N914 100pF VCC+ 1M 20k VCC– 10T VCC– ZERO SCALE ADJUST Figure 3. Full-/Zero-Scale Adjust — Unipolar Output (0–10V) August 31, 1994 2k 1N914 100pF VCC– Figure 1. DC Parametric Test Configuration LE AMP 21 COMP 0.1µF 0.01µF VCC– 22pF SUM 20 DAC COMP 16 17 1N914 100pF OUTPUT VOUT 18 0.1µF 10T 19 DIG GND 1 14 13 VREF OUT 12 VCC+ LSB 754 Philips Semiconductors Linear Products Product specification 8-Bit µp-compatible D/A converter LE MSB NE/SE5018/5019 VCC+ LSB 0.47µF 98 76 543 2 10 19 DIG GND 1 ANA GND 22 14 VREF IN 13 VREF OUT 10k 12 VREF ADJ 10T 5018 OUTPUT VOUT 18 80k DAC COMP BIP OFFSET 16 17 15 0.01µF 22pF SUM 20 2k AMP 21 COMP 1N914 100pF VCC+ 0.1µF 1M 20k VCC– ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ 10T VCC– ZERO SCALE ADJUST Figure 4. Bipolar Output Operation (–5 to +5V) DATA DATA tSLH 10V 1LSB LE tPLH OUTPUT tPLH 10V 0V OUTPUT LE = LOW 0V ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ Figure 5. Settling Time and Propagation Delay, Low-to-High Data Figure 7. Propagation Delay, Latch Enable to Output DATA DATA tSHL tPHL 10V tPHL LE OUTPUT tPHL 0V 10V 1LSB LE = LOW OUTPUT 0V Figure 6. Settling Time and Propagation Delay, High-to-Low Data August 31, 1994 Figure 8. Propagation Delay, Latch Enable to Output 755 Philips Semiconductors Linear Products Product specification 8-Bit µp-compatible D/A converter NE/SE5018/5019 tPW LE DATA ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ tS th ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ Figure 9. Latch Pulse Width, Setup and Hold Times August 31, 1994 756