PHILIPS AM6012F

Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
DESCRIPTION
PIN CONFIGURATION
The AM6012 12-bit multiplying Digital-to-Analog converter provides
high-speed and 0.025% differential nonlinearity over its full
commercial temperature range.
D1 and F Packages
The D/A converter uses a 3-bit segment generator for the MSBs in
conjunction with a 9-bit R-2R diffused resistor ladder to provide
12-bit resolution without costly trimming processes. This technique
guarantees a very uniform step size (up to ± LSB from the ideal),
monotonicity to 12 bits and integral nonlinearity to 0.05% at its
differential current outputs.
The dual complementary outputs of the AM6012 increase its
versatility, and effectively double the peak-to-peak output swing.
Digital inputs, in addition, can be configured to accept all popular
logic families.
D1
1
20 V+
D2
2
19 I
O
D3
3
18 I
O
D4
4
17 V–
D5
5
16 COMP
D6
6
D7
7
15 V
REF(–)
14 VREF(+)
D8
8
D9
9
13 GND/V
LC
12 D LSB
12
D10 10
11 D
11
TOP VIEW
While the device requires a reference input of 1mA for a 4mA
full-scale current, operation is nearly independent of power supply
voltage shifts. The power supply rejection ratio is ±0.001% FS/% ∆V.
The devices will work from +5, -12V to ±18V rails, with as low as
230mW power consumption typical.
NOTE:
1. Available in large SO (SOL) package only.
APPLICATIONS
• CRT displays, computer graphics
• Robotics and machine tools
• Automatic test equipment
• Programmable power supplies
• CAD/CAM systems
• Data acquisition and control systems
• Analog-to-digital converter systems
FEATURES
• 12-bit resolution
• Accurate to within ±0.05%
• Monotonic over temperature
• Fast settling time, 250ns typical
• Trimless design for low cost
• Differential current outputs
• High-speed multiplying capability
• Full-scale current, 4mA (with 1mA reference)
• High output compliance voltage, -5 to +10V
• Low power consumption, 230mW
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
20-Pin Ceramic Dual In-Line Package (CERDIP)
0 to +70°C
AM6012F
0584B
20-Pin Plastic Small Outline Large (SOL) Package
0 to +70°C
AM6012D
0172D
August 31, 1994
776
853-0904 13721
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
BLOCK DIAGRAM
GND/MSB
VLC B1
V(+)
20
13
B2
1
B3
2
B4
3
B5
4
5
B6
6
B7
7
b8
B9
8
9
B10
10
B11
LSB
B12
11
12
LOGIC SWITCHES
DECODER
18
BIAS
NETWORK
VREF (+)
VREF (–)
14
19
REFERENCE
AMPLIFIER
CURRENT
SWITCHES
15
9-SEGMENT
IO
IO
9-BIT R-2R
ISEG
D/A CONVERTER
GENERATOR
16
COMP
17
V(–)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
TA
PARAMETER
TSOLD
VS
UNIT
Operating temperature
0 to +70
°C
-65 to +150
°C
300
°C
±18
V
Logic inputs
-5V to +18
V
Voltage across current outputs
-8V to +12
V
AM6012F
TSTG
RATING
Storage temperature range
Lead soldering temperature 10sec max
Power supply voltage
VREF
Reference inputs V14, V15
VREF
Reference input differential voltage (V14 to V15)
V- to V+
±18
V
IREF
Reference input current (I14)
1.25
mA
PD
Maximum power dissipation, TA=25°C, (still-air)1
F package
1560
mW
D package
1390
mW
NOTES:
1. Derate above 25°C, at the following rate:
F package at 12.5mW/°C
D package at 11.1mW/°C
August 31, 1994
777
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
DC ELECTRICAL CHARACTERISTICS
V+=+15V, V-=-15V, IREF=1.0mA, 0°C ≤ TA ≤ 70°C
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Min
Resolution
12
Monotonicity
12
DNL
Differential nonlinearity
NL
Nonlinearity
IFS
Full-scale current
TCIFS
Full-scale tempco
Typ
Max
Bits
Bits
Deviation from ideal step size
±0.025
%FS
±.05
%FS
4.063
mA
12
VOC
Output voltage compliance
IFSS
Symmetry
IZS
Zero-scale current
VIL
VIH
Logic
input
levels
DNL Specification guaranteed over
compliance range
ROUT>10MΩ typ.
±10
±40
ppm/°C
±0.001
±0.004
%FS/°C
+10
V
±2.0
µA
0.10
µA
0.8
V
40
µA
-5
±0.4
2.0
Logic input current
VIN=-5 to +18V
VIS
Logic input swing
V-=-15V
IREF
Reference current range
I15
Reference bias current
dl/dt
Reference input slew rate
PSSIFS+
Power supply sensitivity
PSSIFSPower supply range
R14(eq)=800Ω
CC=0pF
I+
-5
1.0
1.1
mA
0
-0.5
-2.0
µA
4.0
8.0
mA/µs
±0.0005
±0.001
V-=-13.5V to -16.5V, V+=+15V
±0.00025
±0.001
VOUT=0V
4.5
18
-18
-10.8
V+=+5V, V-=-15V
V+=+15V, V-=-15V
5.7
8.5
-13.7
-18.0
5.7
8.5
-13.7
-18.0
V+=+5V, V-=-15V
234
312
V+=+15V, V-=-15V
291
397
IPower dissipation
V
0.2
Power supply current
I+
+18
V+=+13.5V to +16.5V, V-=-15V
V-
PD
3.999
Logic “0”
IIN
I-
3.935
IFS-IFS
Logic “1”
V+
Bits
Deviation from ideal straight line
VREF=10.000V
R14-R15=10.000kΩ
TA=25°C
UNIT
%FS/%
V
mA
mW
AC ELECTRICAL CHARACTERISTICS
V+=+15V, V-=-15V, IREF=1.0mA, 0°C ≤ TA ≤ 70°C
SYMBOL
PARAMETER
tS
Settling time
tPLH
tPHL
Propagation
delay—all bits
COUT
Output capacitance
August 31, 1994
TEST CONDITIONS
LIMITS
Min
UNIT
Typ
Max
To ± 1/2LSB, all bits ON or OFF, TA=25°C
250
500
ns
50% to 50%
25
50
ns
20
778
pF
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
splitting utilizing scaled emitters. This saves ladder resistors and
greatly reduces the range of emitter scaling required in the 9-bit
DAC. All current switches in the step generator are high-speed
fully-differential switches which are capable of switching low currents
at high speed. This allows the use of a binary scaled network all the
way to the least significant bit which saves power and simplifies the
circuitry.
CIRCUIT DESCRIPTION
The AM6012 is a 12-bit DAC which uses diffused resistors and
requires no trimming to guarantee monotonicity over the
temperature range. A segmented DAC design guarantees a more
uniform step size over the temperature range than is normally
available with trimmed 12-bit converters. The converter features
differential high compliance current outputs, wide supply range, and
a multiplying reference input.
Diffused resistors have advantages over thin film resistors beyond
simple economy and bipolar process compatibility. The resistors are
fabricated in single crystal rather than amorphous material which
gives them better long term stability and tracking and much higher
moisture resistance. They are diffused at 1000°C and so are
resistant to changes in value due to thermal and chemical causes.
Also, no burn-in is required for stability. The contact resistance
between aluminum and silicon is more predictable than between
aluminum and an amorphous thin film, and no sandwich metals are
required to enhance or protect the contact or limit alloying. The initial
match between two diffused resistors is similar to that of thin film
since both are defined by photomasks and chemical etching. Since
the resistors are not trimmed or altered after fabrication, their
tracking and long-term characteristics are not degraded.
In many converter applications, uniform step size is more important
than conformance to an ideal straight line. Many 12-bit converters
are used for high resolution rather than high linearity, since few
transducers are more linear than ±0.1%. All classic binarily weighted
converters require ±1/2LSB (±0.012%) linearity in order to guarantee
monotonicity, which requires very tight resistor matching and
tracking. The AM6012 uses conventional bipolar processing to
achieve high differential linearity and monotonicity without requiring
correspondingly high linearity, or conformance to an ideal straight
line.
One design approach which provides monotonicity without requiring
high linearity is the MOS switch-resistor string. This circuit is actually
a full complement to a current-switched R-2R DAC since it is slower,
has a voltage output, and, if implemented at the 12-bit level, would
use 4096 low tolerance resistors rather than a minimum number of
high tolerance resistors as in the R-2R network. Its lack of speed
and density for 12 bits are its drawbacks.
DIFFERENTIAL VS INTEGRAL NONLINEARITY
Integral nonlinearity, for the purposes of the discussion, refers to the
“straightness” of the line drawn through the individual response
points of a data converter. Differential nonlinearity, on the other
hand, refers to the deviation of the spacing of the adjacent points
from a 1 LSB ideal spacing. Both may be expressed as either a
percentage of full-scale output or as fractional LSBs or both. The
graphs in Figure 1 define the manner in which these parameters are
specified. The left graph shows a portion of the transfer curve of a
DAC with 1/2LSB INL and the (implied) DNL spec of 1 LSB. Below
this is a graphic representation of the way this would appear on a
CRT screen where the AM6012 is used as a display driver. On the
right is a portion of the transfer curve of a DAC specified for 1/2LSB
INL with LSB DNL specified and the graphic display below it.
With the segmented DAC approach, the 4096 required output levels
are composed of 8 groups of 512 steps each. Each step group is
generated by a 9-bit DAC, and each of the segment slopes is
determined by one of 8 equal current sources. The resistors which
determine monotonicity are in the 9-bit DAC. The major carry of the
9-bit DAC is repeated in each of the 8 segments, and requires eight
times lower initial resistor accuracy and tracking to maintain a given
differential nonlinearity over temperature.
The operation of the segmented DAC may be visualized by
assuming an input code of all zeroes. The first segment current IO is
divided into 512 levels by the 9-bit multiplying DAC and fed to the
output, IOUT. As the input code increases, a new segment current is
selected for each 512 counts. The previous segment is fed to output
IOUT where the new step group is added to it, thus ensuring
monotonicity independent of segment resistor values. All higher
order segments feed IOUT.
One of the characteristics of an R-2R DAC in standard form is that
any transition which causes a zero LSB change (i.e., the same
output for two different codes) will exhibit the same output each time
that transition occurs. The same holds true for transitions causing a
2 LSB change. These two problem transitions are allowable for the
standard definition of monotonicity and also allow the device to be
specified very tightly for INL. The major problem arising from this
error type is in A/D converter implementations. Inputs producing the
same output are now represented by ambiguous output codes for an
identical input. Also, two LSB gaps can cause large errors at those
input levels (assuming 1/2LSB quantizing levels). It can be seen
from the two figures that the DNL-specified D/A converter will yield
much finer grained data than the INL-specified part, thus improving
the ability of the A/D to resolve changes in the analog input.
With the segmented DAC approach, the precision of the 8 main
resistors determines linearity only. The influence of each of these
resistors on linearity is four times lower than that of the MSB resistor
in an R-2R DAC. Hence, assuming the same resistor tolerances for
both, the linearity of the segmented approach would actually be
higher than that of an R-2R design.
The step generator or 9-bit DAC is composed of a master and a
slave ladder. The slave ladder generates the four least significant
bits from the remainder of the master ladder by active current
August 31, 1994
779
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
DIFFERENTIAL LINEARITY COMPARISON
+1/2LSB
LIMIT
SEGMENT
CHANGE
IDEAL OUTPUTS
ACUTAL OUTPUTS
2LSB CHANGE ON
X011–X100
TRANSITION
ANALOG OUT
ANALOG OUT
IDEAL OUTPUTS
ACUTAL OUTPUTS
SEGMENT
OF 12-BIT
DAC TRANSFER
CURVE FOR:
INL = ±1/2LSB
DNL = ±1LSB
SEGMENT
CHANGE
–2 LSB
LIMIT
+2LSB
LIMIT
SEGMENT OF 12-BIT DAC
TRANSFER CURVE FOR:
INL = ±2LSB
DNL = ±ℑ√2LSB
NO CHANGE ON
XX01–XX10 TRANSITION
–1/2LSB LIMIT
0010 0010 0100 0110 1000 1010 1100 1110
0001 0011 0101 0111 1001 1011 1101 1111
DIGITAL INPUT
0000 0010 0100 0110 1000 1010 1100 1110
0001 0011 0101 0111 1001 1011 1101 1111
DIGITAL INPUT
±1/2LSB INL, ±1LSB DNL
±2LSB INL, ±1LSB DNL
Figure 1. Differential Linearity Comparison
compliance, reference amplifier negative common-mode range,
negative logic input range, and negative logic threshold range;
consult the various figures for guidance. For example, operation at
-9V with IREF=1mA is not recommended because negative output
compliance would be reduced to near zero. Operation from lower
supplies is possible, however at least 8V total must be applied to
insure turn-on of the internal bias network.
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided
where IO+IO=IFR. Current appears at the “true” output when a “1” is
applied to each logic input. As the binary count increases, the sink
current at Pin 18 increases proportionally, in the fashion of a
“positive logic” D/A converter. When a “0” is applied to any input bit,
that current is turned off at Pin 18 and turned on at Pin 19. A
decreasing logic count increases IO as in a negative or inverted logic
D/A converter. Both outputs may be used simultaneously. If one of
the outputs is not required, it must still be connected to ground or to
a point capable of sourcing IFR; do not leave an unused output pin
open.
Symmetrical supplies are not required, as the AM6012 is quite
insensitive to variations in supply voltage. Battery operation is
feasible as no ground connection is required; however, an artificial
ground may be used to insure logic swings, etc., remain between
acceptable limits.
Both outputs have an extremely wide voltage compliance enabling
fast direct current-to-voltage conversion through a resistor tied to
ground or other voltage source. Positive compliance is 25V above Vand is independent of the positive supply. Negative compliance is
+10V above V-.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the AM6012 are
guaranteed to apply over the entire rated operating temperature
range. Full-scale output current drift is tight, typically ±10ppm/°C,
with zero-scale output current and drift essentially negligible
compared to 1/2LSB.
The dual outputs enable double the usual peak-to-peak load swing
when driving loads in quasi-differential fashion. This feature is
especially useful in cable driving, CRT deflection and in other
balanced applications such as driving center-tapped coils and
transformers.
The temperature coefficient of the reference resistor R14 should
match and track that of the output resistor for minimum overall
full-scale drift.
POWER SUPPLIES
SETTLING TIME
The AM6012 operates over a wide range of power supply voltages
from a total supply of 20V to 36V. When operating with V- supplies
of -10V or less, IREF≤1mA is recommended. Low reference current
operation decreases power consumption and increases negative
August 31, 1994
The AM6012 is capable of extremely fast settling times, typically
250ns at IREF=1.0mA. Judicious circuit design and careful board
layout must be employed to obtain full performance potential during
780
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
testing and application. The logic switch design enables propagation
delays of only 25ns for each of the 12 bits. Settling time to within
LSB of the LSB is therefore 25ns, with each progressively larger bit
taking successively longer. The MSB settles in 250ns, thus
determining the overall settling time of 250ns. Settling to 10-bit
accuracy requires about 90 to 130ns. The output capacitance of the
AM6012 including the package is approximately 20pF; therefore, the
output RC time constant dominates settling time if RL>500Ω.
When a DC reference is used, a reference bypass capacitor is
recommended. A 5.0V TTL logic supply is not recommended as a
reference. If a regulated power supply is used as a reference, R14
should be split into two resistors with the junction bypassed to
ground with a 0.1µF capacitor.
For most applications, the tight relationship between IREF and IFS
will eliminate the need for trimming IREF. If required, full-scale
trimming may be accomplished by adjusting the value of R14, or by
using a potentiometer for R14.
Settling time and propagation delay are relatively insensitive to logic
input amplitude and rise and fall times, due to the high gain of the
logic switches. Settling time also remains essentially constant for
IREF values down to 0.5mA, with gradual increases for lower IREF
values lies in the ability to attain a given output level with lower load
resistors, thus reducing the output RC time constant.
MULTIPLYING OPERATION
The AM6012 provides excellent multiplying performance with an
extremely linear relationship between IFS and IREF over a range of
1mA to 1µA. Monotonic operation is maintained over a typical range
of IREF from 100µA to 1.0mA.
Measurement of settling time requires the ability to accurately
resolve ±2µA, therefore a 2.5kΩ load is needed to provide adequate
drive for most oscilloscopes. At IREF values of less than 0.5mA,
excessive RC damping of the output is difficult to prevent while
maintaining adequate sensitivity. However, the major carry from
011111111111 to 100000000000 provides an accurate indicator of
settling time. This code change does not require the normal 6.2 time
constants to settle to within ±0.1% of the final value, and thus
settling times may be observed at lower values of IREF.
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
reference applications will require the reference amplifier to be
compensated using a capacitor from pin 16 to V-. The value of this
capacitor depends on the impedance presented to Pin 14. For R14
values of 1.0, 2.5 and 5.0kΩ, minimum values of CC are 5, 12 and
25pF. Larger values of R14 require proportionately increased values
of CC for proper phase margin (see Figure 2b).
AM6012 switching transients or “glitches” are very low and may be
further reduced by small capacitive loads at the output at a minor
sacrifice in settling time.
For fastest response to a pulse, low values of R14 enabling small CC
values should be used. If Pin 14 is driven by a high impedance such
as a transistor current source, none of the above values will suffice
and the amplifier must be heavily compensated which will decrease
overall bandwidth and slew rate. For R14=1kΩ and CC=5pF, the
reference amplifier slews at 4mA/ms enabling a transition from
IREF=0 to IREF=1mA in 250ns.
Fastest operation can be obtained by using short leads, minimizing
output capacitance and load resistor values, and by adequate
bypassing at the supply, reference, and VLC terminals. Supplies do
not require large electrolytic bypass capacitors as the supply current
drain is independent of input logic states; 0.1µF capacitors at the
supply pins provide full transient protection.
Operation with pulse inputs to the reference amplifier may be
accommodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a cutoff
(IREF=0) condition. Full-scale transition (0 to 1mA) occurs in 62.5ns
when the equivalent impedance at Pin 14 is 800Ω and CC=0. This
yields a reference slew rate of 8mA/µs which is relatively
independent of RIN and VIN values.
APPLICATIONS INFORMATION
Reference Amplifier Setup
The AM6012 is a multiplying D/A converter in which the output
current is the product of a digital number and the input reference
current. The reference current may be fixed or may vary from nearly
zero to +1.0mA. The full range output current is a linear function of
the reference current and is given by:
I FR LOGIC INPUTS
4095
x 4 x (I REF) 3.999 I REF
4096
The AM6012 design incorporates a unique logic input circuit which
enables direct interface to all popular logic families and provides
maximum noise immunity. This feature is made possible by the large
input swing capability, 40µA logic input current, and completely
adjustable logic threshold voltage. For V-=-15V, the logic inputs may
swing between -5 and +10V. This enables direct interface with +15V
CMOS logic, even when the AM6012 is powered from a +5V supply.
Minimum input logic swing and minimum logic threshold voltage are
given by:
where IREF = I14
In positive reference applications, an external positive reference
voltage forces current through R14 into the VREF(+) terminal (Pin 14)
of the reference amplifier. Alternatively, a negative reference may be
applied to VREF(-) at Pin 15. Reference current flows from ground
through R14 into VREF(+) as in the positive reference case. This
negative reference connection has the advantage of a very high
impedance presented at Pin 15. The voltage at Pin 14 is equal to
and tracks the voltage at Pin 15 due to the high gain of the internal
reference amplifier. R15 (nominally equal to R14) is used to cancel
bias current errors (Figure 2a).
V- plus (IREF×3kΩ) plus 1.8V.
The logic threshold may be adjusted over a wide range by placing
an appropriate voltage at the logic threshold control pin (Pin 13,
VLC). For TTL interface, simply ground Pin 13. When interfacing
ECL, an IREF≤1mA is recommended. For general setup of the logic
control circuit, it should be noted that Pin 13 will sink 1.1mA typical.
External circuitry should be designed to accommodate this current
(Figure 3).
Bipolar references may be accommodated by offsetting VREF or Pin
15. The negative common-mode range of the reference amplifier is
given by: VCM-=V- plus (IREF×3kΩ) plus 1.8V. The positive
common-mode range is V+ less 1.23V.
August 31, 1994
781
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
VR+
AM6012
R14
RIN
IREF
14
VIN
REFERENCE
AMPLIFIER
18
IO
15 I15
IO + IO = IFS
FOR ALL INPUT CODES
R15 = R14 = RIN
IO
R15
VIN
19
COMP
CC
VR–
REFERENCE CONFIGURATION
V–
R14
R15
0.1
V+
20
22µF TANTALUM
(NOTE 5)
0.1
V–
RIN
CC
IREF
Positive reference
VR+
0V
N/C
0.01µF
VR+/R14
Negative reference
0V
VR–
N/C
0.01µF
–VR–/R14
Lo impedance bipolar reference
VR+
0V
VIN1
(VR+/R14) + (VIN/RIN)2
Hi impedance bipolar reference
VR+
VIN
N/C1
(VR+ – RIN) / R143
VR+
0V
VIN
Pulsed
reference4
No Cap
(VR+/R14) + (VIN/RIN)
NOTES:
1. The compensation capacitor is a function of the impedance seen at the +VREF input and must be at least 5pF x R14(eq) in kΩ. For R14 < 800Ω no capacitor is necessary.
2. For negative values of VIN, VR+ / R14 must be greater than –VIN max / RIN so that the amplifier is not turned off.
3.
4.
5.
For positive values of VIN, VR+ must be greater than –VIN max so the amplifier is not turned off.
For pulsed operation, VR+ provides a DC offset and may be set to zero in some cases. The impedance at Pin 14 should be 800Ω or less.
For optimum settling time, decouple V– with 20Ω and bypass with 22µF tantalum capacitor.
6.
Reference current and reference resistor — there is a 1-to-4 scale factor between the reference current (IREF) and the full-scale output current (IFS).
If VREF = +10V and IFS = 4mA, the value of the R14 is:
R 14 4 x 10V
4mA
10k
R 14 R 15
a. Reference Amplifier Biasing
Reference Amplifier
Frequency Response
6
(IFS = 4mA, IREF = 1.0mA)
4
R14(EQ) (kΩ)
10
5
2
1
.5
RELATIVE OUTPUT, dB
Minimum Size
Compensation Capacitor
CC (pF)
50
25
10
5
0
NOTE:
A 0.01µF capacitor is recommended for fixed
reference operation.
R14 (EQ) = 2kΩ
CC = 10pF
2
0
–2
LARGE SIGNAL = 50%
MODULATION OF 4mA
FULL SCALE CURRENT
–4
–6
–8
.01
SMALL SIGNAL = 1%
MODULATION OF 2mA
FULL SCALE CURRENT
0.1
1.0
FREQUENCY MHz
b.
Figure 2.
August 31, 1994
782
10
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
ECL
CMOS, HTL
V+
13kΩ
20kΩ
“A”
“A”
2N3904
2N3904
2N3904
2N3904
3kΩ
3kΩ
TO PIN 13
VLC
20kΩ
R
TO PIN 13
VLC
39kΩ
6.2kΩ
400µA
–5.2V
NOTE:
1. Set the voltage ‘A’ to the desired logic input switching threshold.
2. Allowable range of logic threshold is typically –5V to +13.5V when operating the DAC on ±15V supplies.
Figure 3. Interfacing Circuits for ECL, CMOS, HTL Logic Inputs
ACCOMMODATING BIPOLAR REFERENCE
BASIC NEGATIVE REFERENCE OPERATION
RREF
VREF(+)
IIN
AM6012
IREF
RREF
18
RIN
R15
VREF(–)
14
VIN
18
14
AM6012
NOTE:
I
19
FS
[
IO
15
19
IO
IO
15
IO
V REF(*
R REF
)
x 4
RREF sets IFS; R15 is for a bias current cancellation.
IREF > PEAK NEGATIVE SWING OF IIN
NOTE:
RECOMMENDED FULL-SCALE ADJUSTMENT
CIRCUIT
IREF > Peak negative swing of IIN.
VREF(+)
RREF = R15
RREF
R15
(OPTIONAL)
VIN
18
14
AM6012
IO
VREF(+)
RREF = R15
IO
15
R15
(OPTIONAL)
19
VIN
HIGH INPUT
IMPEDANCE
18
14
AM6012
IO
IO
15
19
HIGH INPUT
IMPEDANCE
VREF MUST BE ABOVE PEAK POSITIVE SWING OF V IN
VREF+ MUST BE ABOVE PEAK POSITIVE SWING OF V IN
NOTE:
VREF(+) Must be above peak positive swing of VIN.
August 31, 1994
RREF
783
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
APPLICATION CIRCUITS
2.000mA
5,000kΩ
ROFF
R3
R1
f
+10V
VREF(+)
REF
IO
a
IO
b
NE535
d
AM6012
R15
10kΩ
R 14 V REF
VREF(–)
B1
B12
MSB
LSB
–
c
e
R14
10kΩ
VOUT
+
g
R2
OPTIONAL
(SEE CODE TABLE)
1.0mA
V REF
R
OFF
2.0mA
CODE FORMAT
CONNECTIONS
MSB
B1 B2
OUTPUT SCALE
B3
B4
B5
B6
B7
B8
B9
LSB
B10 B11 B12
IO
(mA)
IO
(mA)
VOUT
Straight binary; one
a–c
Positive full-scale
1
1
1
1
1
1
1
1
1
1
1
1
3.999
0.000
9.9976
polarity with true input
b–g
Positive full-scale – LSB
1
1
1
1
1
1
1
1
1
1
1
0
3.998
0.001
9.9951
code, true zero output.
R1 = R2 = 2.5k
Zero-scale
0
0
0
0
0
0
0
0
0
0
0
0
0.000
3.999
0.0000
Complementary binary;
a–g
Positive full-scale
0
0
0
0
0
0
0
0
0
0
0
0
0.000
3.999
9.9976
one polarity with
b–c
Positive full-scale – LSB
0
0
0
0
0
0
0
0
0
0
0
1
0.001
3.998
9.9951
Zero-scale
1
1
1
1
1
1
1
1
1
1
1
1
3.999
0.000
0.0000
Unipolar
complementary input
R1 = R2 = 2.5k
code, true zero output.
Straight offset binary;
a–c
Positive full-scale
1
1
1
1
1
1
1
1
1
1
1
1
3.999
0.000
9.9976
offset half-scale,
b–d
Positive full-scale – LSB
1
1
1
1
1
1
1
1
1
1
1
0
3.998
0.001
9.9927
symmetrical about zero,
f–g
(+) Zero-scale
1
0
0
0
0
0
0
0
0
0
0
0
2.000
1.999
0.0024
R1 = R3 = 2.5k
(–) Zero-scale
0
1
1
1
1
1
1
1
1
1
1
1
1.999
2.000 –0.0024
Negative full-scale – LSB
0
0
0
0
0
0
0
0
0
0
0
1
0.001
3.998 –9.9927
Negative full-scale
0
0
0
0
0
0
0
0
0
0
0
0
0.000
3.999 –9.9976
no true zero output.
R2 = 1.25k
Symmetrical
Offset
1’s complement; offset
a–c
Positive full-scale
0
1
1
1
1
1
1
1
1
1
1
1
3.999
0.000
9.9976
half-scale, symmetrical
b–d
Positive full-scale – LSB
0
1
1
1
1
1
1
1
1
1
1
0
3.998
0.001
9.9927
about zero, no true zero
f–g
(+) Zero-scale
0
0
0
0
0
0
0
0
0
0
0
0
2.000
1.999
0.0024
R1 = R3 = 2.5k
(–) Zero-scale
1
1
1
1
1
1
1
1
1
1
1
1
1.999
2.000 –0.0024
Negative full-scale – LSB
1
0
0
0
0
0
0
0
0
0
0
1
0.001
3.998 –9.9927
Negative full-scale
1
0
0
0
0
0
0
0
0
0
0
0
0.000
3.999 –9.9976
Positive full-scale
1
1
1
1
1
1
1
1
1
1
1
1
3.999
0.000
9.9951
Positive full-scale – LSB
1
1
1
1
1
1
1
1
1
1
1
0
3.998
0.001
9.9902
+ LSB
1
0
0
0
0
0
0
0
0
0
0
1
2.001
1.998
0.0049
Zero-scale
1
0
0
0
0
0
0
0
0
0
0
0
2.000
1.999
0.000
– LSB
0
1
1
1
1
1
1
1
1
1
1
1
1.999
2.000 –0.0049
Negative full-scale + LSB
0
0
0
0
0
0
0
0
0
0
0
1
0.001
3.998 –9.9951
Negative full-scale
0
0
0
0
0
0
0
0
0
0
0
0
0.000
3.999 –10.000
Positive full-scale
0
1
1
1
1
1
1
1
1
1
1
1
Positive full-scale – LSB
0
1
1
1
1
1
1
1
1
1
1
0
3.998
0.001
9.9902
+ 1 LSB
0
0
0
0
0
0
0
0
0
0
0
1
2.001
1.998
0.0049
Zero-scale
0
0
0
0
0
0
0
0
0
0
0
0
2.000
1.999
0.000
– 1 LSB
1
1
1
1
1
1
1
1
1
1
1
1
1.999
2.000
–0.049
Negative full-scale + LSB
1
0
0
0
0
0
0
0
0
0
0
1
0.001
3.998 –9.9951
Negative full-scale
1
0
0
0
0
0
0
0
0
0
0
0
0.000
3.999 –10.000
output, MSB complemented
(need inverter at B1).
Offset binary; offset halfscale, true zero output.
R2 = 1.25k
e–a–c
b–g
R1 = R2 = 5k
Offset with
True Zero
2’s complement; offset
half-scale, true zero
output, MSB complemented
e–a–c
b–g
R1 = R2 = 5k
(need inverter at B1).
Figure 4. AM6012 Logic Inputs
ADDITIONAL CODE MODIFICATIONS
1. Any of the offset binary codes may be complemented by
reversing the output terminal pair.
August 31, 1994
784
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
APPLICATION CIRCUITS
+120VDC
60V COMMON
MODE LEVEL
CRT
“X” INPUT
“Y” INPUT
IO
IO
AM6012
–15V
AM6012
–15V
IO
IO
NOTES:
1. Full differential drive lowers power supply voltage.
2. Eliminates inverting amplifiers and transformers.
3. Independent beam centering controls.
Figure 5. CRT Display Driver
CONVERSION TIME vs ACCURACY
1.25
1.00
E
CLOCK
CP Q11
S
CC
2504 SAR
(NAT’L, AMD)
ACCURACY, LSB
SERIAL
DATA OUT
DO
D
O0
LSB
(WORST CASE)
AM6012
WITH
NE529
0.75
0.50
AM6012
WITH
NE529
(TYP)
0.25
+15V
VREF
5.000k
5.000k
+10V
REF
MSB
10.000kΩ
ANALOG IN
(0–10V)
AM6012
2.5kΩ
NE529
IO
COMP
CONVERSION
TIME (ns)
0.001 0.001
µF
µF
0.1µF
0.01
µF
1µF
V(–0
1µF
V(+)
Figure 6. 12-Bit High-Speed A/D Converter
August 31, 1994
200 300 400 500 600 700
CONVERSION TIME PER TRIAL, ns
LSB
IO
MSB
10.000kΩ
0.00
100
785
TYP
WORST
CASE
SAR
33
55
NE529
100
150
TOTAL
383ns
705ns
X 13
5.0µs
9.1µs
800
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
APPLICATION CIRCUITS
OE
MSB
7
6
5
µP
BUS
4
LS373
3
2
6012
1
0
E2
E1
LSB
EB
D3A
Q3A
D3B
Q2A
D2B
D1A
Q1A
D1B
Q1B
D0A
Q0A
D0B
Q0B
D2A
1/2LS100
EA
Q3B
1/2LS100
Q2B
a. Interface With 8-Bit Microprocessor Bus
E1
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
E2
DB0–3
DB4–11
a. Timing Sequence
NOTE:
Data remains on inputs of DAC until updated by E2 pulse. Timing will depend on processor used.
Figure 7.
August 31, 1994
786