Philips Semiconductors Linear Products Product specification 10-Bit µP-compatible D/A converter NE5020 DESCRIPTION PIN CONFIGURATION The NE5020 is a microprocessor-compatible monolithic 10-bit digital-to-analog converter subsystem. This device offers 10-bit resolution and ±0.1% accuracy and monotonicity guaranteed over full operating temperature range. F, N Packages DIGITAL GND 1 24 ANALOG GND DB0(LSB) 2 23 AMP COMP DB1 3 22 SUM MODE DB2 4 21 V CC+ DB3 5 DB4 6 20 V OUT 19 VCC– DB5 7 18 BIPOLAR OFFSET R DB6 8 DB7(MSB) 9 17 +V REFIN 16 –VREFIN Low loading latches, adjustable logic thresholds, and addressing capability allow the NE5020 to directly interface with most microprocessor- and logic-controlled systems. The NE5020 contains internal voltage reference, DAC switches and resistor ladder. Also, the input buffer and output summing amplifier are included. In addition, the matched application resistors for scaling either unipolar or bipolar output values are included on a single monolithic chip. The result is a near minimum component count 10-bit resolution DAC system. NC 10 15 VREFOUT 11 14 V REFADJ 13 LE2 LE1 12 FEATURES • 10-bit resolution • Guaranteed monotonicity over operating range • ±0.1% relative accuracy • Unipolar (0V to +10V) and bipolar (± 5V) output range • Logic bus compatible • 5µs settling time APPLICATIONS • Precision 10-bit D/A converters • 10-bit analog-to-digital converters • Programmable power supplies • Test equipment • Measurement instruments ORDERING INFORMATION TEMPERATURE RANGE ORDER CODE DWG # 24-Pin Ceramic Dual In-Line Package (CERDIP) DESCRIPTION 0 to 70°C NE5020F 0588B 24-Pin Plastic Dual In-Line Package (DIP) 0 to 70°C NE5020N 0412A August 31, 1994 757 853-0392 13721 Philips Semiconductors Linear Products Product specification 10-Bit µP-compatible D/A converter NE5020 BLOCK DIAGRAM (11) DB9 (10) DB8 (9) DB7 (8) DB6 (7) DB5 (6) DB4 (5) DB3 (4) DB2 (3) DB1 (2) DB0 LSB MSB (13) LE2 (12) LE1 LATCHES AND SWITCH DRIVERS SUM (22) NODE Rfb (1) DIGITAL GND (21) +VCC DAC OUTPUT CURRENT VREF (15) OUT DAC SWITCHES R RREF AMP (23) COMP ANALOG (24) GND RBIP QR (18) BIPOLAR OFFSET (16) –VREF IN VOUT (20) VREF VREF (14) ADJ (17) +VREF IN – + INT Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 QT + – R –VCC (19) ABSOLUTE MAXIMUM RATINGS RATING UNIT VCC+ SYMBOL Positive supply voltage 18 V VCC- Negative supply voltage -18 V VIN Logic input voltage 0 to 18 V VREF IN Voltage at +VREF input 12 V VREF ADJ Voltage at VREF adjust 0 to VREF V VSUM Voltage at sum node 12 V IREFSC Short-circuit current to ground at VREF OUT Continuous IOUTSC Short-circuit current to ground or either supply at VOUT Continuous PD PARAMETER Maximum power dissipation TA=25°C, (still-air)1 F package 2150 mW N package 2150 mW TA Operating temperature range NE5020 0 to +70 °C TSTG Storage temperature range -65 to +150 °C TSOLD Lead soldering temperature (10 sec. max) 300 °C NOTES: 1. Derate above 25°C at the following rates: F package at 17.2mW/°C N package at 17.2mW/°C August 31, 1994 758 Philips Semiconductors Linear Products Product specification 10-Bit µP-compatible D/A converter NE5020 DC ELECTRICAL CHARACTERISTICS VCC+=+15V, VCC-=-15V, 0 ≤ TA≤70°C, unless otherwise specified.1 Typical values are specified at 25°C. SYMBOL PARAMETER TEST CONDITIONS LIMITS Min Typ Resolution Monotonicity Relative accuracy 11.4 -11.4 UNIT 10 10 ±0.1 Bits Bits %FS 16.5 -16.5 V V 0.8 V V 10 -10 µA µA VCC+ VCC- Positive supply voltage Negative supply voltage VIN(1) VIN(0) Logic “1” input voltage Logic “0” input voltage Pin 1=0V Pin 1=0V IIN(1) IIN(0) Logic “1” input current Logic “0” input current Pin 1=0V, 2<VIN<18V Pin 1=0V, -5V<VIN<0.8V VFS Full-scale output Unipolar mode, VREF=5.000V, all bits high, TA=25°C 9.5 10.5 V +VFS Full-scale output Bipolar mode, VREF=5.000V, all bits high, TA=25°C 4.75 5.25 V -VFS Negative full-scale Bipolar mode, VREF=5.000V, all bits low, TA=25°C -5.25 -4.75 V NOTES: 1. Refer to Figure 1. August 31, 1994 759 15 -15 Max 2.0 0.1 -2.0 Philips Semiconductors Linear Products Product specification 10-Bit µP-compatible D/A converter NE5020 DC ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER VZS Zero-scale output IOS Output short-circuit current PSR+(OUT) LIMITS TEST CONDITIONS Min Unipolar mode, VREF=5.000V, all bits low, TA=25°C Typ Max -30 UNIT +30 mV TA=25°C VOUT=0V ±15 ±40 mA Output power supply rejection (+) V-=-15V, 13.5V≤V+≤16.5V, external VREF IN=5.000V 0.001 0.01 %FS/ %VS PSR-(OUT) Output power supply rejection (-) V+=15V, -13.5V≤V-≤-16.5V, external VREF IN=5.000V 0.001 0.01 %FS/ %VS TCFS Full-scale temperature coefficient VREF IN=5.000V 20 ppmFS /°C TCZS Zero-scale temperature coefficient 5 ppmFS/°C IREF2 Reference output current IREF SC Reference short circuit current PSR+REF 3 mA TA=25°C VREF OUT=0V 15 30 mA Reference power supply rejection (+) V-=-15V, 13.5V≤V+≤16.5V, IREF=1.0mA .003 .01 %VR/ %VS PSR-REF Reference power supply rejection (-) V+=15V, -13.5V≤V-≤16.5V, .003 .01 %VR/ %VS VREF Reference voltage 5.0 5.25 TCREF Reference voltage temperature coefficient IREF=1.0mA 60 ZIN DAC VREF IN input impedance IREF=1.0mA 5.0 ICC+ Positive supply current VCC+=15V 7 ICC - Negative supply current PD Power dissipation IREF=1.0mA, TA=25°C 4.9 V ppm/°C kΩ 14 mA VCC -=-15V -10 -15 mA IREF=1.0mA, VCC=±15V 255 435 mW NOTES: 1. Refer to Figure 1. 2. For IREF OUT greater than 3mA, an external buffer is required. AC ELECTRICAL CHARACTERISTICS1 VCC = +15V, TA = 25°C. SYMBOL LIMITS TO FROM TEST CONDITIONS Settling time ±1/2LSB Input All bits low-to-high2 tSHL Settling time ±1/2LSB Input high-to-low3 tPLH Propagation delay Output Input All bits switched low-to-high2 high-to-low3 150 ns 150 ns transition4 300 ns 150 ns tSLH PARAMETER tPHL Propagation delay Output Input tPLSB Propagation delay Output Input All bits All bits switched 1 LSB change2,3 tPLH Propagation delay Output LE Low-to-high tPHL Propagation delay Output LE High-to-low transition5 tS Set-up time LE Input 1,6 LE tH Hold time tPW Latch enable pulse width Input NOTES: 1. Refer to Figure 2. 2. See Figure 5. 3. See Figure 6. 4. See Figure 7. 5. See Figure 8. 6. See Figure 9. August 31, 1994 Min 760 Typ Max UNIT 5 µs 5 µs 30 ns 100 ns 1,6 50 ns 1,6 150 ns Philips Semiconductors Linear Products Product specification 10-Bit µP-compatible D/A converter LE2 LE1 5.000V MSB NE5020 VCC+ LSB LE2 LE1 MSB LSB VCC+ 0.47µF 0.47µF 11 10 9 8 7 6 5 4 3 2 12 13 17 VREF IN 15 VREF OUT 5020 14 11 10 9 8 7 6 5 4 3 2 12 13 17 21 DIG GND 1 ANA GND 24 15 –VREF IN 16 VOUT 20 18 –VREF IN 16 OUTPUT 30pF SUM 22 5k AMP 23 COMP ANA GND 24 VOUT 20 30pF SUM 22 19 5020 14 OUTPUT 21 DIG GND 1 19 18 AMP 23 COMP 5k 100pF 100pF 0.1µF 0.1µF VCC– VCC– Figure 1. DC Parametric Test Configuration LE2 LE1 Figure 2. AC Parametric Test Configuration MSB 0.47µF 11 10 9 8 7 6 5 4 3 2 12 13 17 VREF IN 15 VREF OUT 10k 10T VCC+ LSB 14 VREF ADJ 21 DIG GND 1 ANA GND 24 –VREF IN 16 5020 30pF VOUT 20 80k OUTPUT SUM 22 19 FULL SCALE ADJUST 5k AMP 23 COMP 18 100pF VCC+ 0.1µF 1M 20k VCC– 10T VCC– ZERO SCALE ADJUST Figure 3. Full-/Zero-Scale Adjust — Unipolar Output (0–10V) LE2 LE1 MSB 0.47µF 11 10 9 8 7 6 5 4 3 2 12 13 17 VREF IN 15 VREF OUT 10k 10T VCC+ LSB 14 VREF ADJ 5020 21 DIG GND 1 ANA GND 24 –VREF IN 16 VOUT 20 80k 30pF OUTPUT SUM 22 19 BIP OFF 18 AMP 23 COMP 5k 100pF VCC+ 0.1µF 1M 20k VCC– 10T VCC– FULL SCALE ADJUST Figure 4. Bipolar Output Operation (–5 to +5V) August 31, 1994 761 Philips Semiconductors Linear Products Product specification 10-Bit µP-compatible D/A converter NE5020 ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ DATA DATA tSLH tPHL 10V 1LSB LE tPLH OUTPUT tPHL 10V 0V LE = LOW OUTPUT 0V Figure 5. Settling Time and Propagation Delay, Low-to-High Data Figure 8. Propagation Delay, Latch Enable to Output DATA ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ tSHL LE tPHL 10V OUTPUT DATA 0V 1LSB LE = LOW ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ Figure 6. Settling Time and Propagation Delay, High-to-Low Data tS ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ th Figure 9. Latch Enable Pulse Width, Setup and Hold Times DATA LE tPLH 10V OUTPUT 0V Figure 7. Propagation Delay, Latch Enable to Output August 31, 1994 tMIN 762 Philips Semiconductors Linear Products Product specification 10-Bit µP-compatible D/A converter TTL, DTL VTH = +1.4V NE5020 PMOS VTH = VPIN1 + 1.4V +15V CMOS, HTL, HNIL VTH = 0V VTH = +7.6V +15V +12V TO +15V NE5020 9.1kΩ 10kΩ IN4148 PIN 1 DIG GND (PIN 1) PIN 1 6.2kΩ 6.2V ZENER PIN 1 0.1µF 10kΩ –5V TO –10V NOTE: DO NOT EXCEED NEGATIVE LOGIC INPUT RANGE OF DAC +5V CMOS +10V CMOS 10k ECL VTH = +2.8V VTH = +9.0V VTH ≥ –1.29V +5V +10V 1.3kΩ 6.2kΩ 3.6kΩ 2N3904 PIN 1 IN4148 PIN 1 0.1µF 3.6kΩ IN4148 PIN 1 3.9kΩ 1kΩ Figure 10. 10 details several bias schemes used to provide the proper threshold voltage levels for various logic families. CIRCUIT DESCRIPTION The NE5020 provides ten data latches, an internal voltage reference, application resistors, and a scaled output voltage in addition to the basic DAC components (see Block Diagram). To be compatible with a bus-oriented system, the DAC should respond in as short a period as possible to insure full utilization of the microprocessor, controller and I/O control lines. Figure 9 shows the typical timing requirements of the latch and data lines. This figure indicates that data on the data bus should be stable for at least 50ns after LE is changed to a high state. Latch Circuit Digital interface with the NE5020 is readily accomplished through the use of two latch enable ports (LE1 and LE2) and ten data input latches. LE2 controls the two most significant bits of data (DB9 and DB8) while LE1 controls the eight lesser significant bits (DB7 through DB0). Both the latch enable ports (LE) and the data inputs are static- and threshold-sensitive. When the latch enable ports (LE) are high (Logic ‘1’) the data inputs become very high impedances and essentially disappear from the data bus. Addressing the LE with a low static (Logic ‘0’), the latches become active and adapt the logic states present on the data bus. During this state, the output of the DAC will change to the value proportional to the data bus value. When the latch enable returns to a high state, the selected set of data inputs (i.e., depending on which LE goes high) ‘memorizes’ the data bus logic states and the output changes to the unique output value corresponding to the binary word in the latch. The independent LE (LE1 and LE2) lines allow for direct interface from an 8-bit bus (see Figure 11). Data for the two MSBs is supplied and stored when LE2 is activated low and returned high according to the NE5020 timing requirements. Then LE1 is activated low and the remaining eight LSBs of data are transferred into the DAC. With LE1 returning high, the loading of 10-bit data word from an 8-bit data bus is complete. Occasionally the analog output must change to its data value within one data address operation. This is no problem using the NE5020 on a 16-bit bus or any other data bus with 10 or greater data bits. This can be accomplished from an 8-bit data bus by utilizing an external latch circuit to pre-load the two MSB data values. Figure 12 shows the circuit configuration. The data inputs are inactive and high impedance (typically requiring –2µA for low (0.8V max) or 0.1µA for high (2.0V min) when the LE is high. Any changes on the data bus with LE high will have no effect on the DAC output. After pre-loading (via LE pre-load) the external latch with the two MSB values, LE2 is activated low and the eight LSBs and the two MSBs are concurrently loaded into the DAC in one address operation. This permits the DAC output to make its appropriate change at one time. The digital logic inputs (LE and DB) for the NE5020 utilize a differential input logic system with a threshold level of +1.4V with respect to the voltage level on the digital ground pin (Pin 1). Figure August 31, 1994 763 Philips Semiconductors Linear Products Product specification 10-Bit µP-compatible D/A converter NE5020 B0 DATA BUS B6 B7 DB 9 8 7 6 5 4 3 2 1 0 MSB LSB LATCHES LE2 LE1 LATCHES OUTPUT DAC Figure 11. NE5020 µP Interface 8-Bit Data Bus Example 8-BIT DATA BUS +5V 1 4 10 13 2 74LS74 3 11 12 9 5 LE PRE-LOAD INVERTER 11 10 9 8 7 6 MSB LE LOAD 5 4 3 2 LSB 12 20 13 NE5020 Figure 12. Pre-loading the 2 MSBs to Provide a Single-Step Output August 31, 1994 764 Philips Semiconductors Linear Products Product specification 10-Bit µP-compatible D/A converter NE5020 5k VREF IN (17) + IREF 5k To R-2R Ladder (16) – BIPOLAR OFFSET (18) JUMPER FOR BIPOLAR OPERATION SUM NODE (22) DAC AMP VCC (ID IREF) 5k ID DAC CURRENT FROM CURRENT SWITCHES – + OUTPUT AMP Figure 13. Bipolar Output Reference Interface I OUT The NE5020 contains an internal bandgap voltage reference which is designed to have a very low temperature coefficient and excellent long-term stability characteristics. DB9 2 DB8 DB7 4 8 DB5 DB3 DB6 DB4 32 64 128 16 The internal bandgap reference (1.23V) is buffered and amplified to provide the 5V reference output. Providing a VREF ADJ (Pin 14) allows trimming of the reference output. Utilization of the adjust circuit shown in Figure 15 performs not only VREF adjustment, but also full-scale output adjust. Notice that the VREF ADJ pin is essentially the sum node of an op amp and is sensitive to excessive node capacitance. Any capacitance on the node can be minimized by placing the external resistors as close as possible to the VREF ADJ pin and observing good layout DB0 DB2 DB1 256 512 1024 Because of the fixed internal compensation of the reference amp, the slew rate is limited to typically 0.7V/µs and source impedance at the VREF INPUT greater than 5kΩ should be avoided to maintain stability. The –VREF INPUT pin is uncommitted to allow utilization of negative polarity reference voltages. In this mode +VREF INPUT is grounded and the negative reference is tied directly to the –VREF INPUT contains a 5kΩ resistor that matches a like resistor in the +VREF INPUT to reduce voltage offset caused by op amp input bias currents. practices. The VREF OUT node can drive loads greater than the DAC VREF input requirements and can be used as an excellent system voltage reference. However, to minimize load effects on the DAC system accuracy, it is recommended that a buffer amplifier be used. Output Amplifier and Interface The NE5020 provides an on-chip output op amp to eliminate the need for additional external active circuits. Its two-stage design with feed-forward compensation allows it to slew at 15V/µs and settle to within ±1/2LSB in 5µs. These times are typical when driving the rated loads of RL ≥ 5k and CL 50pF with recommended values of CFF = 1nF and CFB = 30pF. Typical input offset voltages of 5mV and 50kΩ open-loop gain insure that an accurate current-to-voltage conversion is performed when using the on-chip RFB resistor. RFB is matched to RREF and RBIP to maintain accurate voltage gain over operating conditions. The diode shown from ground to sum node prevents the DAC current switches from saturating the op amp during large signal transitions which would otherwise increase the settling time. Input Amplifier The DAC reference amplifier is a high gain internally-compensated op amp used to convert the input reference voltage to a precision bias current for the DAC ladder network. The Block Diagram details the input reference amplifier and current ladder. The voltage-to-current converter of the DAC amp will generate a 1mA reference current through QR with a 5V VREF. This current sets the input bias to the ladder network. Data bit 9 (DB9)(Q9), when turned on, will mirror this current and will contribute 1mA to the output. DB8 (Q8) will contribute 1/2 of that value or 0.5mA, and so on. These current values act as current sinks and will add at the sum node to produce a DAC ladder to sum node function of: August 31, 1994 2V REF R REF The output op amp also incorporates output short circuit protection for both positive and negative excursions. During this fault condition IOUT will limit at ±15mA typical. Recovery from this condition to rated accuracy will be determined by duration of short-circuit and die temperature stabilization. 765 Philips Semiconductors Linear Products Product specification 10-Bit µP-compatible D/A converter NE5020 R1 = 20K, 10T POTENTIOMETER VCC –VCC R2 = 1MΩ SUM NODE (22) (OPTIONAL) 5k DAC CURRENT OUTPUT – (20) VOUT CFF + 5k AMP COMP (23) (24) CC Figure 14. Zero-Scale Adjustment + VREF OUT VREF OUT (15) INT REF – 15k R3 = 80k VREF ADJ R3 = 10k 10T POT (14) 5k Figure 15. Reference Adjust Circuit potentiometer R1 until VOUT equals 0.000V in the unipolar mode or –5.000V in the bipolar mode (see bipolar section accomplishes this The NE5020 includes a thermally matched resistor, RBIP, to offset trim. the output voltage by 5V to obtain –5V to +5V output voltage range operation. This is accomplished by shorting Pins 18 and 22 (see Full-Scale Adjustment Figure 13). This connection produces a current equal to (VREFIN – A recommended full-scale adjustment circuit, when using the SUM NODE) ÷ RBIP (1mA nominal), which is injected into the sum internal voltage reference, is shown in Figure 15. Potentiometer R3 node. Since full-scale current out is approximately 2mA is adjusted until VOUT equals 9.99023V. In many applications where (1.9980mA), (2mA – 1mA)5kΩ = 5V will appear at the output. For the absolute accuracy of full-scale is of low importance when zero DAC output currents, 1mA is still injected into sum node and compared to the other system accuracy factors this adjustment VOUT = –(5kΩ) (1mA) = –5V. Zero-scale adjust and full-scale adjust circuit is optional. are performed as described below, noting that full-scale voltage is Bipolar Output Voltage now approximately +5V. Zero-scale adjust may be used to trim VOUT = 0.00 with the MSB high or VOUT = –5.0V with all bits off. As resistors RREF, RFB, and RBIP shown in the Block Diagram are integrated in close proximity, they match and track in value closely over wide ambient temperature variations. Typical matching is less than ±0.3% which implies that typical full-scale (or gain) error is less than ±0.3% of ideal full-scale value. Zero-Scale Adjustment The method of trimming the small offset error that may exist when all data bits are low is shown in Figure 14. The trim is the result of injecting a current from resistor R2 that counteracts the error current. Adjusting August 31, 1994 766