PHILIPS NE5410F

Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
DESCRIPTION
NE/SE5410
PIN CONFIGURATION
The NE5410/SE5410 are 10-bit Multiplying Digital-to-Analog
Converters pin- and function-compatible with the industry-standard
MC3410, but with improved performance. These are capable of
high-speed performance, and are used as general-purpose building
blocks in cost effective D/A systems.
F Package
VEE 1
16 VREF+
15 V
–
GND 2
OUTPUT 3
REF
14 V
CC
13 D (LSB)
D1 (MSB) 4
D2 5
The NE/SE5410 provides complete 10-bit accuracy and differential
non-linearity over temperature, and a wide compliance voltage
range. Segmented current sources, in conjunction with an R/2R
DAC, provide the binary weighted currents. The output buffer
amplifier and voltage reference have been omitted to allow greater
speed, lower cost, and maximum user flexibility.
10
12 D9
D3 6
D4 7
10 D7
D5 8
9
11 D8
D6
TOP VIEW
FEATURES
• Pin- and function-compatible with MC3410
• 10-bit resolution and accuracy (±0.05%)
• Guaranteed differential non-linearity over temperature
• Wide compliance voltage range—-2.5 to +2.5V
• Fast settling time—250ns typical
• Digital inputs are TTL- and CMOS-compatible
• High-speed multiplying input slew rate—20mA/µs
• Reference amplifier internally-compensated
• Standard supply voltages +5V and -15V
BLOCK DIAGRAM
MSB
LSB
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
4
5
6
7
8
9 10 11 12 13
IO
3
CURRENT SWITCHES
LADDER TERMINATORS
R-2R LADDER
APPLICATIONS
• Successive approximation A/D converters
• High-speed, automatic test equipment
• High-speed modems
• Waveform generators
• CRT displays
• Strip CHART and X-Y plotters
• Programmable power supplies
• Programmable gain and attenuation
VREF(+)
VREF(–)
16
15
BIAS
CIRCUITRY
REFERENCE
CURRENT
AMPLIFIER
14
1
2
VEE
GND
VCC
ORDERING INFORMATION
TEMPERATURE RANGE
ORDER CODE
DWG #
16-Pin Ceramic Dual In-Line Package (CERDIP)
DESCRIPTION
0 to +70°C
NE5410F
0582B
16-Pin Ceramic Dual In-Line Package (CERDIP)
-55 to +125°C
SE5410F
0582B
August 31, 1994
767
853-0945 13721
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
ABSOLUTE MAXIMUM RATINGS
TA=+25°C, unless otherwise specified.
SYMBOL
PARAMETER
VCC
Power supply
VEE
VI
Digital input voltage
VO
Applied output voltage
IREF(16)
Reference current
VREF
Reference amplifier inputs
VREF(D)
Reference amplifier differential inputs
TA
Operating temperature range
RATING
UNIT
+7.0
VDC
-18
VDC
+15
VDC
+4, -5.0
VDC
2.5
mA
VCC, VEE
VDC
0.7
VDC
SE5410
-55 to +125
°C
NE5410
0 to +70
°C
TJ
Junction temperature
TSTG
Storage temperature
PD
Maximum power dissipation
TA=25°C (still-air)1
Ceramic package
+150
°C
-65 to +150
°C
1190
mW
NOTES:
1. Derate above 25°C at the following rate:
F package at 9.5mW/°C
DC ELECTRICAL CHARACTERISTICS (Continued)
VCC=+5.0VDC, VEE=-15VDC, IREF=2.0mA, all digital inputs at high logic level. SE5410: TA=-55°C to +125°C, NE5410 Series: TA=0°C to +70°C,
unless otherwise noted.
SYMBOL
∈R
PARAMETER
Relative accuracy
TEST CONDITIONS
LIMITS
Min
Over Temperature
(Error relative to full scale IO)
Differential non-linearity
Over temperature
UNIT
Typ
Max
±0.025
±0.05
%
±1/4
±1/2
LSB
±0.025
±0.05
%
±1/4
±1/2
LSB
tS
Settling time to within ±1/2 LSB
(all bits low to high)
TA = 25°C
250
ns
tPLH
tPHL
Propagation delay time
TA = 25°C
35
20
ns
TCIO
Output full-scale current drift
VIH
Digital input logic levels (all bits)
High level, Logic “1”
Low level, Logic “0”
20
Digital input current (all bits)
High level, VIH = 5.5V
Low level, VIL = 0.8V
IREF(15)
Reference input bias current (Pin 15)
IOH
Output current (all bits high)
VREF = 2.000V, R16 = 1000Ω
IOL
Output currents (all bits low)
TA = 25°C
VO
Output voltage compliance
SR IREF
Reference amplifier slew rate
ST IREF
Reference amplifier settling time
PSRR(–)
Output current power supply sensitivity
CO
Output capacitance
August 31, 1994
0.8
20
–20
3.937
–1.0
–5.0
µA
4.054
mA
0
0.4
µA
–2.5
+2.5
VDC
20
768
mA/µs
µs
2.0
0.003
VO = 0
µA
3.996
TA = 25°C
∈R < 0.050%
relative to full-scale
0 to 4.0mA, ±0.1%
ppm/°C
VDC
2.0
IIH
IIL
40
25
0.01
%/%
pF
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
DC ELECTRICAL CHARACTERISTICS
VCC=+5.0VDC, VEE=-15VDC, IREF=2.0mA, all digital inputs at high logic level. SE5410: TA=-55°C to +125°C, NE5410 Series: TA=0°C to +70°C,
unless otherwise noted.
SYMBOL
CI
PARAMETER
LIMITS
TEST CONDITIONS
Min
Typ
Max
UNIT
Digital input capacitance (all bits high)
4.0
ICC
IEE
Power supply current (all bits low)
+2
–12
+4
–18
mA
VCC
VEE
Power supply voltage range
+5.0
–15
+5.25
–15.75
VDC
190
300
mW
TA = 25°C
VO = 0
+4.75
–14.25
Power consumption
pF
ICC IEEPOWER SUPPLY CURRENT (mA)
OUTPUT CURRENT (mA)
4.0
3.0
+VCC = +5V
–VEE = –15V
2.0
TA = 25°C
IREF = 2mA
1.0
0
–1.0
–5
–3
–1 0 1
3
COMPLIANCE VOLTAGE (VOLT)
5
13
12
IEE
11
10
+VCC = +5V
4
–VEE = –15V
IREF = 2mA
3
2
+ICC
1
0
–75 –50 –25
0
25
50
75 100 125
TA (°C)
OUTPUT COMPLIANCE VOLTAGE (VOLTS)
Figure 1. Output Current vs Output Compliance Voltage
Figure 3. Power Supply Currents vs Temperature
4.0
3.0
2.0
+VCC = +5V
1.0
–VEE = –15V
0
IREF = 2mA
–1.0
–2.0
–3.0
–4.0
–75 –50 –25
0
25
50
75 100 125
TA (°C)
Figure 2. Maximum Output Compliance Voltage
vs Temperature
Figure 4. Reference Amplifier Frequency Response
An on-chip high slew reference current amplifier drives the R/2R
ladder and segment decoder. The currents are scaled in such a way
that, with all bits on, the maximum output current is two times
1023/1024 of the reference amplifier current, or nominally 3.996mA
for a 2.000mA reference input current. The reference amplifier
allows the user to provide a voltage input: out-board resistor R16
(see Figure 6) converts this voltage to a usable current. A current
mirror doubles this reference current and feeds it to the segment
decoder and resistor ladder. Thus, for a reference voltage of 2.0V
and a 1kΩ resistor tied to Pin 16, the full-scale current is
CIRCUIT DESCRIPTION
The NE5410 consists of four segment current sources which
generate the 2 Most Significant Bits (MSBs), and an R/2R DAC
implemented with ion-implanted resistors for scaling the remaining 8
Least Significant Bits (LSBs) (see Figure 5). This approach provides
complete 10-bit accuracy without trimming.
The individual bit currents are switched ON or OFF by
fully-differential current switches. The switches use current steering
for speed.
August 31, 1994
769
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
approximately 4.0mA. This relationship will remain regardless of the
reference voltage polarity.
bypassing the junction of the two resistors with a 0.1µF capacitor to
ground.
Connections for a positive reference voltage are shown in Figure 6a.
For negative reference voltage inputs, or for bipolar reference
voltage inputs in the multiplying mode, R15 can be tied to a negative
voltage corresponding to the minimum input level. For a negative
reference input, R16 should be grounded (Figure 6b). In addition,
the negative voltage reference must be at least 3V above the VEE
supply voltage for best operation. Bipolar input signals may be
handled by connecting R16 to a positive voltage equal to the peak
positive input level at Pin 15.
The reference amplifier is internally-compensated with a 10pF
feed-forward capacitor, which gives it its high slew rate and fast
settling time. Proper phase margin is maintained with all possible
values of R16 and reference voltages which supply 2.0mA reference
current into Pin 16. The reference current can also be supplied by a
high impedance current source of 2.0mA. As R16 increases, the
bandwidth of the amplifier decreases slightly and settling time
increases. For a current source with a dynamic output impedance of
1.0MΩ, the bandwidth of the reference amplifier is approximately
half what it is in the case of R16=1.0kΩ, and settling time is ±10µs.
The reference amplifier phase margin decreases as the current
source value decreases in the case of a current source reference,
so that the minimum reference current supplied from a current
source is 0.5mA for stability.
When a DC reference voltage is used, capacitive bypass to ground
is recommended. The 5V logic supply is not recommended as a
reference voltage. If a well regulated 5.0V supply, which drives logic,
is to be used as the reference, R16 should be decoupled by
connecting it to the +5.0V logic supply through another resistor and
(4)
MSB
D1
(5)
D2
(6)
D3
(7)
D4
(8)
D5
(9)
D6
(10)
D7
(11)
D8
(12)
D9
(13)
LSB
D10
GND
(2)
IOUT
(3)
SEGMENT
DECODER
VBIAS
(INTERNAL)
2R
2R
R
2R
R
R
2R
2R
R
R
2R
2R
R
(16)
+
VREF
+
CODE SELECTED 0111110011
(15)
–
–
2R1
R1
R1
R1
R1
VEE (1)
Figure 5. NE5410 Equivalent Circuit
August 31, 1994
770
2R
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
and full-scale current drift. Relative accuracy, or linearity, is the
measure of each output current with respect to its intended fraction
of the full-scale current. The relative accuracy of the NE5410 is fairly
constant over temperature due to the excellent temperature tracking,
of the implanted resistors. The full-scale current from the reference
amplifier may drift with temperature causing a change in the
absolute accuracy. However, the NE5410 has a low full-scale
current drift with temperature.
VR (+)
RT
R16
14
VCC
R15
15
16
IO
5410
D1 THROUGH D10
NE/SE5410
The SE5410 and the NE5410 are accurate to within ± LSB at 25°C
with a reference current of 2.0mA on Pin 16.
3
1
2
NOTES:
VEE
R16 + RT = R15 = RREF
RT < <R16
IO F.S. = 2 IR = VREF/RREF a. Positive Reference Voltage
MONOTONICITY
The NE5410 and SE5410 are guaranteed monotonic over
temperature. This means that for every increase in the input digital
code, the output current either remains the same or increases but
never decreases. In the multiplying mode, where reference input
current will vary, monotonicity can be assured if the reference input
current remains above 0.5mA.
VR (–)
RT
VCC
R15
R16
13
SETTLING TIME
15
The worst-case switching condition occurs when all bits are
switched “on,” which corresponds to a LOW-to-HIGH transition for
all bits. This time is typically 250ns for the output to settle to within ±
1/2LSB for 10-bit accuracy, and 200ns for 8-bit accuracy. The
turn-off time is typically 120ns. These times apply when the output
swing is limited to a small (<0.7V) swing and the external output
capacitance is under 25pF.
IO
5410
D1 THROUGH D10
NOTES:
R15 + RT = R16
RT < <R15
IVREF ≥ RVEE + 3V
1
2
VEE
b. Negative Reference Voltage
The major carry (MSB off-to-on, all others on-to-off) settles in
approximately the same time as when all bits are switched off-to-on.
Figure 6. Basic Connections
If a load resistor of 625Ω is connected to ground, allowing the output
to swing to -2.5V, the settling time increases to 1.5µs.
OUTPUT VOLTAGE COMPLIANCE
The output voltage compliance ranges from -2.5 to +2.5V. As shown
in Figure 2, this compliance range is nearly constant over
temperature. At the temperature extremes, however, the compliance
voltage may be reduced if VEE>-15V.
Extra care must be taken in board layout as this is usually the
dominant factor in satisfactory test results when measuring settling
time. Short leads, 100µF supply bypassing, and minimum scope
lead length are all necessary.
A typical test setup for measuring settling time is shown in Figure 7.
The same setup for the most part can be used to measure the slew
rate of the reference amplifier (Figure 9) by tying all data bits high,
pulsing the voltage reference input between 0 and 2V, and using a
500Ω load resistor RL.
ACCURACY
Absolute accuracy is a measure of each output current level with
respect to its intended value. It is dependent upon relative accuracy
August 31, 1994
771
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
VCC
0.1µF
+2VDC
14
4
16
1k
15
1k
2.4V
5
6
9
0.4V
RL
0.5V
500
NE5410
10
3
VO
VO
11
0
12
13
VI
VI
0.1µF
7
8
RISE AND FALL TIMES ≤ 10ns
50
tS — 250ns TYPICAL
TO ± 1/2 LSB
CO ≤ 25pF
2
1
0.1µF
VEE
Figure 7. Settling Time
VCC
0.1µF
14
4
16
1k
15
1k
+2VDC
5
6
RISE AND FALL TIMES ≤ 10ns
0.1µF
2.4V
7
8
9
VI
NE5410
10
0.4V
3
VO
11
12
13
VI
50
2
RL
20
VO
0V
1
–80mV
0.1µF
TO ± 1/2 LSB
tPLH
VEE
Figure 8. Propagation Delay Time
August 31, 1994
tPHL
FOR PROPAGATION
DELAY TIME
772
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
VCC
0.1µF
VREF (+)
2V
0
14
4
16
1k
15
1k
2.0V
5
6
7
8
9
VREF (+)
0.1µF
0
RL
10
0.5V
500
NE5410
VO
11
12
13
SLEW RATE
VO
3
0
tS = 2µs TYPICAL
TO ±0.1%
≤ 25pF
2
1
NOTE:
0.1µF
Use RL = 20Ω to GND for slew rate measurement.
VEE
Figure 9. Reference Amplifier Settling Time and Slew Rate
F.S. ADJ
5V
REF
RF
RT
2.5k
RREF
+15V
VCC
0.1µF
2.5k
16
5410
15
1/2 NE5535
VOUT
2.5k
VEE
0
ADJ
0.1µF
10k
–15V
Figure 10. Bipolar Voltage Output Circuits (-10V to +10V)
August 31, 1994
773
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
5V
REF
ANALOG
INPUT
(0-10V)
2.4k
20k
+5VDC
F.S.
ADJ
+5VDC
–V
+V
200Ω
ZERO
ADJ
2.5k
16
2.5k 15
500k
3
NE5410
3
1
14
V1+
IN A
V2+
NE529
2.5k
4
–15VDC
DOUT
IN B
OUT A
6
E
Q9
Q0
2504 SAR
CLOCK
–10VDC
D
S
START
Q10
CP
10
EOC
+5VDC
NOTES:
10-bit conversion time = 3.3µs with 3MHz clock.
This converter uses a 2504 12-bit successive approximation register in the short cycle operating mode where the end of conversion signal is taken from the first unused bit of the
SAR (Q10).
Figure 11. Successive Approximation A/D Converter
7
16
6
15
5
µP
BUS
12
4
LS373
9
3
NE5410
6
2
5
1
2
0
CONTROL
SIGNALS
FROM µP
1
OE
19
E2
E1
1 D
0
E2,3
Q0 2
1/2 LS375
7
D1
Q1
Q2
11
1/2LS375
6
Q3
E0,1
13
4
TIMING SEQUENCE
ÉÉ É ÉÉ
ÉÉ É ÉÉ
ÉÉ É ÉÉ
E1
E2
DATA
DB0,1
DB2-9
NOTES:
With this double latch technique, valid data will be latched to the DAC until updated with the E 2 pulse. Timing will depend on the processor used.
Figure 12. 8-Bit µP Bus Interface
August 31, 1994
774
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
VIN
+5V
3k
RT
VCC
5V
REF
14
2
1
3
NE5410
15
3k
RI
2.5k 16
2.5k
ZERO
ADJ
VEE
+
COMP
13 12 11 10 9
LSB
8
7
6
4 MSB
5
DOUT
–
Q0
START
RST
Q9
CP
10-BIT COUNTER
NOTE:
V
IN
FULL SCALE 4mA (R 1 R )
T
1023
1024
Figure 13. Staircase A/D
August 31, 1994
775
–15
TTL
CLOCK