TI UCC5510

UCC5510
Low Voltage Differential (LVD/SE) SCSI 9 Line Terminator
FEATURES
DESCRIPTION
• Auto Selection Multi-Mode Single
Ended or Low Voltage Differential
Termination
The UCC5510 Multi-Mode Low Voltage Differential and Single Ended
Terminator is specially designed for automatic termination of SingleEnded or Low Voltage Differential SCSI Bus. The Multi-Mode operation of
this device allows for a transition system design for the next generation
SCSI Parallel Interface (SPI-2). Compliant with SPI-2, with SPI and Fast20 the UCC5510 incorporates all the functions necessary to properly terminate the SCSI Bus and has internal thermal shut down and short circuit limiting.
• 3.0V to 5.25V Operation
• Differential Failsafe Bias
• Thermal Packaging for Low Junction
Temperature and Better MTBF
• Master/Slave Inputs
• Supports Active Negation
• 3pF Channel Capacitance
BLOCK DIAGRAM
SOURCE 5 < 15mA
SINK 200µA MAXIMUM (NOISE LOAD)
TRMPWR 38
+VDD
REF 1.3V
20 DIFFSENS
MSTR/SLV 19
1.3V ± –0.1V
2.2 > 1.9V
DEVICE MODE
SELECT LOGIC
DIFFB 21
0.7 > 0.6V
110
REF 2.7V
125 +50mV TO +62.5mV
52
REF 1.25V
5
L1–
4
L1+
32
L9–
31
L9+
52
HS/GND
8
HS/GND
28
HS/GND
27
110
125
+50mV TO +62.5mV
52
HS/GND 26
HS/GND
10
HS/GND
9
GND
52
SWITCHES UP ARE SINGLE
ENDED SWITCHES DOWN ARE
LOW VOLTAGE DIFFERENTIAL
18
SE GND
SWITCH
1
Circuit Design Patented
SLUS332A - OCTOBER 1999
REG
UDG-98033
UC5510
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS
SSOP-36 (Top View)
MWP Package
TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . 0V to TRMPWR
Package Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 2W
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C
RECOMMENDED OPERATING CONDITIONS
TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.0V TO 5.25V
All voltages are with respect to pin 1. Currents are positive into,
negative out of the specified terminal. Consult Packaging Section of the Databook for thermal limitations and considerations of
packages.
REG
1
36
N/C
2
35
N/C
N/C
3
34
N/C
L1+
4
33
N/C
L1–
5
32
L9–
L2+
6
31
L9+
L2–
7
30
L8–
HS/GND
8
29
L8+
HS/GND
9
28
HS/GND
HS/GND
10
27
HS/GND
L3+
11
26
HS/GND
L3–
12
25
L7–
L4+
13
24
L7+
L4–
14
23
L6–
L5+
15
22
L6+
L5–
16
21
DIFF B
N/C
17
20
DIFFSENS
GND
18
19
MSTR/SLV
TRMPWR
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0°C to 70°C, TRMPWR = 3.3V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
TRMPWR Supply Current Section
TRMPWR Supply Current
Disable Terminator, in DISCNCT mode.
20
mA
35
µA
Regulator Section
1.25V Regulator
LVD Mode
1.15
1.25
1.25V Regulator Source Current
LVD Mode, Differential Sense Floating
–80
–100
1.35
V
mA
1.25V Regulator Sink Current
LVD Mode, Differential Sense Floating
80
100
1.3V Regulator
DIFFSENS
1.2
1.3
1.3V Regulator Source Current
DIFFSENS
1.3V Regulator Sink Current
DIFFSENS
2.7V Regulator
Single Ended Mode
2.5
2.7
3
V
2.7V Regulator Source Current
Single Ended Mode
–200
–400
–800
mA
2.7V Regulator Sink Current
Single Ended Mode
100
200
2.7V Regulator Dropout Voltage
VTRMPWR – (VREG – 3.0 Min)
2
mA
1.4
V
–5
–15
mA
50
200
µA
400
mA
200
mV
UC5510
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0°C to 70°C, TRMPWR = 3.3V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Differential Impedance
100
105
110
Ω
Common Mode Impedance
110
125
165
Ω
125
mV
Differential Termination Section
Differential Bias Voltage
Drivers Tri-stated
100
Common Mode Bias
Output Capacitance
1.25
Single Ended Measurement to Ground (Note 1)
V
3
pF
Single Ended Termination Section
Impedance
Termination Current
Signal Level 0.2V
102.3
110
117.7
Ω
–21
–23
–24
mA
–22.4
mA
400
nA
3
pF
60
Ω
Signal Level 0.5V
Output Leakage
Disabled, TRMPWR = 0V to 5.25V
Output Capacitance
Single Ended Measurement to Ground (Note 1)
Single Ended GND SW Impedance
Differential Sense (DIFF B) Input Sections
DIFFB Single Ended Threshold
0.6
0.7
V
DIFFB Sense LVD Threshold
1.9
2.2
V
–10
10
µA
DIFFB Input Current
VDIFFB = 0V and 3.3V
Master/Slave (MSTR/SLV) Input Section
MSTR/SLV Threshold
0.8
2
V
MSTR/SLV Input Current
–30
30
µA
Note 1: Guaranteed by design. Not 100% tested in production.
PIN DESCRIPTIONS
DIFFB: DIFF SENSE filter pin should be connected to a
0.1µF capacitor to GND and 20k resistor to SCSI/Bus
DIFF SENSE Line.
negative line in differential applications for the SCSI bus.
DIFFSENS: The SCSI bus DIFF SENSE line is driven to
1.3V to detect what type of devices are connected to the
SCSI bus.
MSTR/SLV: Mode select for the non-controlling terminator. MSTR enables the 1.3V regulator, when the terminator is enabled. Note: This function will be removed on
further generations of the multimode terminators.
L1+ thru L9+: Ground line for single ended or positive
line for differential applications for the SCSI bus.
HS/GND: Heat Sink GND. Connect to large area PC
board traces to increase power dissipation capability.
GND: Power Supply Return.
REG: Regulator bypass, must be connected to a 4.7µF
capacitor.
L1– thru L9–: Signal line/active line for single ended or
TRMPWR: VIN 3.0V to 5.25V supply.
3
UC5510
APPLICATION INFORMATION
TRMPWR
36 TRMPWR
19
1
L1+
L1+
L1–
L1–
MSTR/SLV
REG
CONTROL LINES (9)
L9+
L9–
L9–
DIFFSENS 20
20 DIFFSENS
REG
1
20k
DIFFB 21
4.7µF
TRMPWR
MSTR/SLV 19
L9+
20k
TRMPWR 36
21 DIFFB
0.1µF
4.7µF
0.1µF
4.7µF
4.7µF
36 TRMPWR
L10+
L10+
L10–
L10–
TRMPWR 36
L18+
L18+
MSTR/SLV 19
L18–
L18–
DATA LINES + PARITY
19 MSTR/SLV
1
REG
DIFFSENS 20
NO CONNECT
DIFFB 21
4.7µF
36 TRMPWR
REG
REG
1
21 DIFFB
4.7µF
L19+
L19+
L19–
L19–
TRMPWR 36
L27+
L27+
MSTR/SLV 19
L27–
L27–
19 MSTR/SLV
1
20 DIFFSENS
DATA LINES + PARITY
DIFFSENS 20
NO CONNECT
20 DIFFSENS
4.7µF
REG
1
4.7µF
DIFFB 21
21 DIFFB
UDG-98034a
Figure 1. Application Drawing
The master is selected by placing TRMPWR on
MSTR/SLV and enabling the 1.3V regulator. The master
is the only terminator connected directly to the DIFFSENS bus line. All the other terminators receive a mode
signal by connecting the DIFFB pins together.
in the MWP package where between L8 and L9 the balance is 0.23pF and 0.4pF respecitvely The negative (–)
signal line has a higher capacitance than the positive (+)
signal line. The FQP package has typically 0.2pF less
capacitance than the MWP package, where the typical
balance is 0.1pF except for L8 and L3, where the balance is 0.4pF.
The balancing capacitor is very important during high
speed operation. The typical capacitor balance between
the positive (+) and negative (–) signals is 0.1pF, except
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
Note: The master/slave function will not be included in future
Unitrode terminators.
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