SN74LS228 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS SDLS024 – JANUARY 1991 – REVISED SEPTEMBER 1993 • • • • • • • N PACKAGE (TOP VIEW) Independent Synchronous Inputs and Outputs 16 Words by 4 Bits Data Rates From 0 to 10 MHz Fall-Through Time . . . 50 ns Typ Data Terminals Arranged for Printed-Circuit-Board Layout Expandable Using External Gating Packaged in Standard Plastic 300-mil DIPs OE IR LDCK D0 D1 D2 D3 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC UNCK OR Q0 Q1 Q2 Q3 CLR description This 64-bit memory is a low-power Schottky memory array organized as 16 words by 4 bits. It can be expanded in multiples of 15m + 1 words or 4n bits, or both (where n is the number of packages in the vertical array and m is the number of packages in the horizontal array), however some external gating is required (see Figure 1). For longer words using the SN74LS228, the IR signals of the first-rank packages and OR signals of the last-rank packages must be ANDed for proper synchronization. A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array at independent data rates. These FIFOs are designed to process data at rates from 0 to 10 MHz in a bit-parallel format, word by word. Data is written into memory on a low-to-high transition at the load-clock (LDCK) input and is read out on a low-to-high transition at the unload-clock (UNCK) input. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect. Status of the FIFO memory is monitored by the input-ready (IR) and output-ready (OR) flags that indicate not-full and not-empty conditions. IR is high only when the memory is not full and the LDCK is low. OR is high only when the memory is not empty and UNCK is high. A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the IR and OR outputs. The SN74LS228 is characterized for operation from 0°C to 70°C. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10–1 SN74LS228 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS SDLS024 – JANUARY 1991 – REVISED SEPTEMBER 1993 logic symbol† FIFO 16 × 4 OE CLR 1 9 EN5 CT = 0 CT < 16 LDCK CTR 2 & 3 Z2 CT > 0 & 15 D1 D2 D3 OR Z3 2 D0 14 – CT = 0 4 IR + /C1 3 UNCK 2 1D & V4 4, 5 13 5 12 6 11 7 10 Q0 Q1 Q2 Q3 † This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. This symbol is functionally accurate but does not show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0. 10–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LS228 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS SDLS024 – JANUARY 1991 – REVISED SEPTEMBER 1993 logic diagram (positive logic) OE CLR LDCK 1 9 3 Ring Counter CTR 1 DIV 16 2 S 1D C1 COMP 3 4 + 5 6 Write 7 Address 8 9 10 11 12 CT = 1 13 14 15 16 S 2D C2 Q=P+1 16 P P=Q+1 Q P=Q EMPTY 2 14 UNCK 15 Ring Counter CTR 1 2 DIV 16 3 R 3D C3 4 5 + 6 Read 7 Address 8 9 10 11 12 CT = 1 13 14 15 16 R 4D C4 IR OR 16 16 RAM 16 × 4 1 1A 16 16 2A 1 16 EN C5 4 D0 5 D1 6 D2 D3 7 1A,5D 2A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ≥1 13 12 11 10 Q0 Q1 Q2 Q3 10–3 SN74LS228 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS SDLS024 – JANUARY 1991 – REVISED SEPTEMBER 1993 schematics of inputs and outputs EQUIVALENT OF OTHER INPUTS EQUIVALENT OF CLR AND ORE INPUTS VCC VCC 13 kΩ NOM 19 kΩ NOM Input Input TYPICAL OF IR AND OR OUTPUTS TYPICAL OF Q OUTPUTS VCC Output 120 Ω NOM Output 10–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LS228 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS SDLS024 – JANUARY 1991 – REVISED SEPTEMBER 1993 timing diagram CLR LDCK UNCK ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌ D0 – D3 W1 W2 W1 W2 W15 W16 IR ÌÌÌÌ ÌÌÌÌ OR Q0 – Q3 Invalid Word 1 ÌÌÌ ÌÌÌ Word 2 Invalid Word 1 Word 2 Initialize Load Two Words Unload Two Words Load Until Full Unload absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Off-state output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70° Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10–5 SN74LS228 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS SDLS024 – JANUARY 1991 – REVISED SEPTEMBER 1993 recommended operating conditions (see Note 2) VCC VIH Supply voltage VIL VOH Low-level input voltage High-level output voltage Q outputs IOH High-level output current IR, OR IOL Low level output current Low-level tw High-level input voltage Setup time th TA Hold time NOM MAX UNIT 5 5.25 V 2 V 0.8 5.5 – 0.4 Q outputs 24 IR, OR Pulse duration tsu MIN 4.75 8 LDCK high 60 LDCK low 15 UNCK low 30 UNCK high 30 CLR low 20 Data to LDCK↓ 50 LDCK↓ before UNCK↓ 50 UNCK↑ before LDCK↑ 50 Data from LDCK↓ Operating free-air temperature V V mA mA ns ns 0 ns 0 70 °C NOTE 2: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs. Any excessive noise or glitching on the clock inputs that violates the VIL, VIH, or minimum pulse duration limits can cause a false clock or improper operation of the internal read and write pointers. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK IOH Q outputs VCC = 4.75 V, VCC = 4.75 V, II = – 18 mA VOH = 5.5 V VOH IR, OR VCC = 4.75 V, Q outputs VCC = 4 4.75 75 V IOH = – 0.4 mA IOL = 12 mA VOL IOZH IOZL IR OR IR, VCC = 4 4.75 75 V Q outputs VCC = 5.25 V, VCC = 5.25 V, Q outputs II IIH VCC = 5.25 V, VCC = 5.25 V, IIL IOS‡ ICC VCC = 5.25 V, IR, OR TYP† – 1.5 0.1 2.7 3.4 0.4 0.35 0.5 0.25 0.4 IOL = 8 mA VO = 2.7 V 0.35 0.5 20 VO = 0.4 V VI = 7 V VI = 2.7 V VI = 0.4 V – 20 POST OFFICE BOX 655303 V mA V µA – 20 µA 0.1 mA 20 µA – 0.4 mA – 100 mA Outputs high 84 135 Outputs low 87 155 Outputs disabled 89 155 • DALLAS, TEXAS 75265 UNIT V 0.25 † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second. 10–6 MAX IOL = 24 mA IOL = 4 mA VCC = 5.25 V VCC = 5.25 V MIN mA SN74LS228 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS SDLS024 – JANUARY 1991 – REVISED SEPTEMBER 1993 switching characteristics, VCC = 5 V, TA = 25°C (see Note 3) PARAMETER FROM (INPUT) tPLH tPHL IRE↑ tPLH tPHL ORE↑ tPLH tPHL LDCK↓ tPLH tPLH tPHL tPLH tPLH tPHL tPHL tPLH tPHL IRE↓ ORE↓ LDCK↑ LDCK↓ UNCK↑ UNCK↓ UNCK↑ CLR↓ LDCK↓ UNCK↑ tPLH OE↓ tPHL OE↑ TO (OUTPUT) TEST CONDITIONS TYP MAX N/A N/A N/A N/A N/A N/A N/A N/A 25 40 36 50 48 70 29 45 28 45 IR 49 70 IR 36 55 OR 25 40 Q 34 50 54 80 45 70 21 30 20 35 IR OR IR RL = 2 kΩ,, CL = 15 pF OR OR RL = 667 Ω Ω, CL = 45 pF F Q Q UNIT ns ns ns ns ns ns ns ns ns ns NOTE 3: Load circuit and voltage waveforms are shown in Section 1 of the 1988 TTL Logic Data Book, literature #SDLD001A. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10–7 SN74LS228 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS SDLS024 – JANUARY 1991 – REVISED SEPTEMBER 1993 APPLICATION INFORMATION CLR OE CLR LDCK OE LDCK IR ORE IRE 5V Q0 Q1 Q2 Q3 CLR OE 5V OR Open UNCK IR ORE IRE 5V Q0 Q1 Q2 Q3 CLR OE 5V OR Open UNCK IR ORE IRE D0 D1 D2 D3 Q0 Q1 Q2 Q3 CLR OE 5V OR Open LDCK IR IRE D0 D1 D2 D3 UNCK ORE Q0 Q1 Q2 Q3 ORE IRE 5V Q0 Q1 Q2 Q3 CLR OE 5V OR Open LDCK UNCK ORE IRE 5V Q0 Q1 Q2 Q3 CLR OE 5V OR Open UNCK ORE IRE D0 D1 D2 D3 Q0 Q1 Q2 Q3 CLR OE 5V OR Open LDCK ORE Q0 Q1 Q2 Q3 D0 D1 D2 D3 • DALLAS, TEXAS 75265 ORE OE LDCK OR UNCK IRE ORE D0 D1 D2 D3 Q0 Q1 Q2 Q3 CLR OE LDCK OR UNCK IRE CLR LDCK IRE D0 D1 D2 D3 ≡ Noninverting delay ≥ 10 ns (e.g., two stages of ’LS04), two places. POST OFFICE BOX 655303 OR CLR Figure 1. 48-Word by 16-Bit Expansion Using ’LS227 10–8 OR Q0 Q1 Q2 Q3 IR 5V UNCK D0 D1 D2 D3 D0 D1 D2 D3 UNCK IRE IRE IR 5V OE UNCK IR D0 D1 D2 D3 LDCK LDCK IR D0 D1 D2 D3 IR 5V 5V CLR 10 ns UNCK IR 5V OR LDCK IR D0 D1 D2 D3 LDCK OE IR D0 D1 D2 D3 LDCK 10 ns 10 ns UNCK IR 5V OR 5V CLR ORE Q0 Q1 Q2 Q3 OE OR UNCK ORE Q0 Q1 Q2 Q3 5V PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing SN74LS228N OBSOLETE PDIP N Pins Package Eco Plan (2) Qty 16 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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