SN74F193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR SDFS031A – D3693, JANUARY 1991 – REVISED OCTOBER 1993 • • • • • D OR N PACKAGE (TOP VIEW) High-Speed fmax of 100 MHz Typical Parallel Asynchronous Load for Modulo-N Count Lengths Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs B QB QA DOWN UP QC QD GND description 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC A CLR BO CO LOAD C D The SN74F193A is a synchronous, 4-bit binary up/down counter. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count /clock (UP or DOWN) input. The direction of the count is determined by which count input is pulsed while the other count input is high. All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the LOAD input and entering the desired data at the data (D) inputs. The output will change to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A high level applied to the clear (CLR) input forces all outputs to the low level. The clear function is independent of the count and load inputs. These counters were designed to be cascaded without the need for external circuitry. The borrow (BO) output produces a low-level pulse while the count is zero (all Q outputs low) and the DOWN input is low. Similarily, the carry (CO) output produces a low-level pulse while the count is 15 (all Q outputs high) and the UP input is low. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs, respectively, of the succeeding counter. The SN74F193A is characterized for operation from 0°C to 70°C. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 SN74F193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR SDFS031A – D3693, JANUARY 1991 – REVISED OCTOBER 1993 logic symbol† CLR UP DOWN LOAD A B C D 14 5 4 11 15 state diagram CTRDIV16 CT = 0 2+ G1 1– G2 1CT = 15 2CT = 0 0 12 13 3D 3 2 10 6 9 7 3 4 15 5 14 6 13 7 BO QA QB QC QD † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2–2 2 CO C3 1 1 POST OFFICE BOX 655303 12 Count up Count down • DALLAS, TEXAS 75265 11 10 9 8 SN74F193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR SDFS031A – D3693, JANUARY 1991 – REVISED OCTOBER 1993 logic diagram (positive logic) 14 12 CLR LOAD UP DOWN 13 11 CO BO 5 4 S A R 15 S 3 C1 1D R QA 1 B S 2 C1 1D R C 10 S 6 C1 1D R D QB QC 9 S C1 1D R POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 QD 2–3 SN74F193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR SDFS031A – D3693, JANUARY 1991 – REVISED OCTOBER 1993 typical clear, load, and count sequence Illustrated below is the following sequence: 1. Clear outputs to zero 2. Load (preset) to binary thirteen 3. Count up to fourteen, fifteen (carry), zero, one, and two 4. Count down to one, zero (borrow), fifteen, fourteen, and thirteen CLR LOAD A Data Inputs B C D UP DOWN QA QB Outputs QC QD CO BO 0 13 Sequence Illustrated Clear 2–4 14 15 0 Count Up 1 2 Preset POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 15 14 0 Count Down 13 SN74F193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR SDFS031A – D3693, JANUARY 1991 – REVISED OCTOBER 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 °C to 70 °C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input-voltage ratings may be exceeded if the input-current ratings are observed. recommended operating conditions MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IIK Low-level input voltage 0.8 V Input clamp current 18 mA IOH IOL High-level output current –1 mA Low-level output current 20 mA TA Operating free-air temperature 70 °C High-level input voltage 2 V V 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IIH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = – 18 mA IOH = – 1 mA VCC = 4.75 V, VCC = 4.5 V, IOH = – 1 mA to 3 mA IOL = 20 mA VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL VCC = 5 5.5 5V V, VI = 0 0.5 5V IOS§ ICC VCC = 5.5 V, VCC = 5.5 V, VO = 0 Outputs open MIN TYP‡ 2.5 3.4 MAX UNIT – 1.2 V V 2.7 0.3 0.5 V 0.1 mA 20 µA UP – 1.8 Others – 0.6 – 60 34 mA – 150 mA 54 mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5 SN74F193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR SDFS031A – D3693, JANUARY 1991 – REVISED OCTOBER 1993 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C fclock Clock frequency CLR high tw LOAD low Pulse duration UP or DOWN high UP or DOWN low Setup time th Hold time MIN MAX MIN MAX 0 85 0 85 4 4 5.5 5.5 4 4 6 6 3.5 3.5 5 5 LOAD inactive before UP↑ or DOWN↑ 7.5 7.5 Data after LOAD inactive 2.5 2.5 Data before LOAD inactive tsu VCC = 4.5 V to 5.5 V, TA = MIN to MAX† CLR inactive before UP↑ or DOWN↑ UNIT MHz ns ns ns switching characteristics (see Note 2) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) TYP 85 100 MAX MIN 9 3 8 3 9 2.5 8.5 2.5 9 5 12 5 13 2 7 1.5 8 6 13.5 5 15 4.5 10 4 11 5.5 12 5 13 Any Q 5 11 5 12 CO 6 12 5.5 13 BO 5 11 5 12 6 13.5 6 15 6 12.6 6 13.8 Any Q A B A, B, C C, or D Any Q LOAD Any Q tPLH tPHL LOAD CO or BO tPLH tPHL A B A, B, C C, or D CO or BO 5.5 13 5 14 4.5 12.5 4.5 13.5 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 2: Load circuits and waveforms are shown in Section 1. 2–6 MHz 2.5 UP or DOWN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX 85 8.5 CO or BO CLR MIN VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† 2.5 UP or DOWN CLR VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C ns ns ns ns ns ns ns ns PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74F193AD OBSOLETE SOIC D 16 TBD Call TI Call TI SN74F193ADR OBSOLETE SOIC D 16 TBD Call TI Call TI SN74F193AN OBSOLETE PDIP N 16 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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