TI CDC329

CDC329
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCBS117A–D4501, JANUARY 1991–REVISED NOVEMBER 1992
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D PACKAGE
(TOP VIEW)
Low Output Skew for Clock-Distribution
and Clock-Generation Applications
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
TTL-Compatible Inputs and
CMOS-Compatible Outputs
Distributes One Clock Input to Six Clock
Outputs
Polarity Control Selects True or
Complementary Outputs
Distributed VCC and GND Pins Reduce
Switching Noise
High-Drive Outputs (–15-mA IOH,
64-mA IOL )
Packaged in Plastic Small-Outline Package
GND
1Y2
2Y1
GND
2Y2
3Y
GND
4Y
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1Y1
1T/C
VCC
2T/C
A
VCC
3T/C
4T/C
description
The CDC329 contains a clock driver circuit that distributes one input signal to six outputs with minimum skew
for clock distribution. Through the use of the polarity control inputs (T/C), various combinations of true and
complementary outputs can be obtained.
The CDC329 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE
INPUTS
T/C
A
OUTPUT
Y
L
L
L
L
H
H
H
L
H
H
H
L
logic symbol †
A
1T/C
2T/C
3T/C
4T/C
12
1
15
13
N1
1
N2
2
2
10
9
N3
3
N4
4
16
2
3
5
6
8
1Y1
1Y2
2Y1
2Y2
3Y
4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright  1992, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CDC329
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCBS117A–D4501, JANUARY 1991–REVISED NOVEMBER 1992
logic diagram (positive logic)
1T/C
15
16
1Y1
2
1Y2
2T/C
A
13
3
5
3T/C
2Y1
12
10
2Y2
6
3Y
4T/C
9
8
4Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
Voltage range applied to any output in the high state
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Continuous total power dissipation at (or below) 25°C free-air temperature (see Note 2) . . . . . . . . 1000 mW
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. For operation above 25°C free-air temperature, derate to 478 mW at 85°C at the rate of 8.7 mW/°C.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
∆t / ∆v
Input transition rise or fall rate
High-level input voltage
NOM
MAX
UNIT
5
5.25
V
2
V
0.8
V
V
High-level output current
VCC
–15
mA
Low-level output current
64
mA
5
ns / V
85
°C
Input voltage
0
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low.
2
MIN
4.75
POST OFFICE BOX 655303
– 40
• DALLAS, TEXAS 75265
CDC329
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCBS117A–D4501, JANUARY 1991–REVISED NOVEMBER 1992
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.75 V,
VCC = 4.75 V,
II = –18 mA
IOH = – 15 mA
VOL
II
VCC = 4.75 V,
VCC = 5.25 V,
IOL = 64 mA
VI = VCC or GND
ICC
VCC = 5.25 V,,
VI = VCC or GND
IO = 0,,
MIN
TYP†
MAX
UNIT
–1.2
V
3.85
V
Outputs high
Outputs low
20
Ci
VI = 2.5 V or 0.5 V
† All typical values are at VCC = 5 V, TA = 25°C
0.55
V
±1
µA
50
µA
30
mA
3
pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Any Y
tPLH
tPHL
T/C
Any Y
tsk(o)
k( )
A
MIN
TYP
MAX
2
6.6
1.7
5.4
1.6
7.4
1.7
6.3
Any Y (same phase)
0.5
Any Y (any phase)
2.5
tr
tf
UNIT
ns
ns
ns
2
ns
1.3
ns
switching characteristics, VCC = 5 V ± 0.25 V, TA = 25°C to 70°C (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Any Y
tsk(o)
k( )
A
Any Y (same phase)
Any Y (any phase)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
MAX
2.3
5.9
1.7
4.8
0.5
2
UNIT
ns
ns
3
CDC329
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCBS117A–D4501, JANUARY 1991–REVISED NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
LOAD CIRCUIT FOR OUTPUTS
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPHL
tPLH
Output
50% VCC
20% VCC
80% VCC
tr
VOH
50% VCC
20% VCC
VOL
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC329
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCBS117A–D4501, JANUARY 1991–REVISED NOVEMBER 1992
WAVEFORMS FOR CALCULATION OF tsk(o)
A
1T/C
1Y1
tPLH1
tPHL1
tPLH5
tPHL5
tPLH2
tPHL2
tPLH6
tPHL6
tPLH3
tPHL3
tPHL7
tPLH7
tPLH4
tPHL4
tPHL8
tPLH8
1Y2
2T/C
2Y1
2Y2
Output skew, tsk(o), from A to any Y (same phase), can be measured only between outputs for which the respective polarity control inputs (T/C)
are at the same logic level. It is calculated as the greater of:
a) the difference between the fastest and slowest of tPLH from A↑ to any Y
(e.g., tPLHn, n = 1 to 4; or tPLHn, n = 5 to 6),
b) the difference between the fastest and slowest of tPHL from A↓ to any Y
(e.g., tPHLn, n = 1 to 4; or tPHLn, n = 5 to 6),
c) the difference between the fastest and slowest of tPLH from A↓ to any Y
(e.g., tPLHn, n = 7 to 8), and
d) the difference between the fastest and slowest of tPHL from A↑ to any Y
(e.g., tPHLn, n = 7 to 8).
Output skew, tsk(o), from A to any Y (any phase), can be measured between outputs for which the respective polarity control inputs (T/C) are at
the same or different logic levels. It is calculated as the greater of:
a) the difference between the fastest and slowest of tPLH from A↑ to any Y or tPHL from A↑ to any Y
(e.g., tPLHn, n = 1 to 4; or tPLHn, n = 5 to 6, and tPHLn, n = 7 to 8), and
b) the difference between the fastest and slowest of tPHL from A↓ to any Y or tPLH from A↓ to any Y
(e.g., tPHLn, n = 1 to 4; or tPHLn, n = 5 to 6, and tPLHn, n = 7 to 8).
Figure 2. Skew Waveforms and Calculations
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5
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