PHILIPS TDA8359J

INTEGRATED CIRCUITS
DATA SHEET
TDA8359J
Full bridge vertical deflection output
circuit in LVDMOS
Product specification
Supersedes data of 13 March 2000
Filed under Integrated Circuits, IC02
2002 Jan 21
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
TDA8359J
FEATURES
GENERAL DESCRIPTION
• Few external components required
The TDA8359J is a power circuit for use in 90° and 110°
colour deflection systems for 25 to 200 Hz field
frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC
contains a vertical deflection output circuit, operating as a
high efficiency class G system. The full bridge output
circuit allows DC coupling of the deflection coil in
combination with single positive supply voltages.
• High efficiency fully DC-coupled vertical bridge output
circuit
• Vertical flyback switch with short rise and fall times
• Built-in guard circuit
• Thermal protection circuit
• Improved EMC performance due to differential inputs.
The IC is constructed in a Low Voltage DMOS (LVDMOS)
process that combines bipolar, CMOS and DMOS
devices. DMOS transistors are used in the output stage
because of absence of second breakdown.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VP
supply voltage
7.5
12
18
V
VFB
flyback supply voltage
2 × VP 45
66
V
Iq(P)(av)
average quiescent supply current
during scan
−
10
15
mA
Iq(FB)(av)
average quiescent flyback supply current
during scan
−
−
10
mA
Ptot
total power dissipation
−
−
10
W
Inputs and outputs
Vi(p-p)
input voltage (peak-to-peak value)
−
1000
1500
mV
Io(p-p)
output current (peak-to-peak value)
−
−
3.2
A
−
−
±1.8
A
Flyback switch
Io(peak)
t ≤ 1.5 ms
maximum (peak) output current
Thermal data; in accordance with IEC 60747-1
Tstg
storage temperature
−55
−
+150
°C
Tamb
ambient temperature
−25
−
+85
°C
Tj
junction temperature
−
−
150
°C
ORDERING INFORMATION
TYPE
NUMBER
TDA8359J
2002 Jan 21
PACKAGE
NAME
DBS9P
DESCRIPTION
plastic DIL-bent-SIL power package; 9 leads (lead length
12/11 mm); exposed die pad
2
VERSION
SOT523-1
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
TDA8359J
BLOCK DIAGRAM
handbook, full pagewidth
GUARD
8
VP
VFB
3
6
GUARD
CIRCUIT
M5
D2
D3
M2
Vi(p-p)
D1
VI(bias)
7 OUTA
INA 1
M4
0
Vi(p-p)
INB
VI(bias)
9
INPUT
AND
FEEDBACK
CIRCUIT
FEEDB
M1
2
4
0
OUTB
M3
TDA8359J
5
MGL862
GND
Fig.1 Block diagram.
PINNING
SYMBOL
PIN
DESCRIPTION
handbook, halfpage
INA
1
INB
2
VP
3
OUTB
4
ground
GND
5
6
flyback supply voltage
VFB
6
7
output A
OUTA
7
GUARD
8
guard output
GUARD
8
FEEDB
9
feedback input
FEEDB
9
INA
1
input A
INB
2
input B
VP
3
supply voltage
OUTB
4
output B
GND
5
VFB
OUTA
TDA8359J
MGL863
The exposed die pad is connected to pin GND.
Fig.2 Pin configuration.
2002 Jan 21
3
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
TDA8359J
FUNCTIONAL DESCRIPTION
Guard circuit
Vertical output stage
A guard circuit with output pin GUARD is provided.
The vertical driver circuit has a bridge configuration. The
deflection coil is connected between the complimentary
driven output amplifiers. The differential input circuit is
voltage driven. The input circuit is specially designed for
direct connection to driver circuits delivering a differential
signal but it is also suitable for single-ended applications.
For processors with output currents, the currents are
converted to voltages by the conversion resistors
RCV1 and RCV2 (see Fig.5) connected to pins INA
and INB. The differential input voltage is compared with
the voltage across the measuring resistor RM, providing
feedback information. The voltage across RM is
proportional with the output current. The relationship
between the differential input voltage and the output
current is defined by:
The guard circuit generates a HIGH-level during the
flyback period. The guard circuit is also activated for one
of the following conditions:
• During thermal protection (Tj = 170 °C)
• During an open-loop condition.
The guard signal can be used for blanking the picture tube
and signalling fault conditions. The vertical
synchronization pulses of the guard signal can be used by
an On Screen Display (OSD) microcontroller.
Damping resistor compensation
HF loop stability is achieved by connecting a damping
resistor RD1 across the deflection coil. The current values
in RD1 during scan and flyback are significantly different.
Both the resistor current and the deflection coil current flow
into measuring resistor RM, resulting in a too low deflection
coil current at the start of the scan.
Vi(dif)(p-p) = Io(p-p) × RM
Vi(dif)(p-p) = VINA − VINB
The output current should not exceed 3.2 A (p-p) and is
determined by the value of RM and RCV. The allowable
input voltage range is 100 mV to 1.6 V for each input. The
formula given does not include internal bondwire
resistances. Depending on the values of RM and the
internal bondwire resistance (typical value of 50 mΩ) the
actual value of the current in the deflection coil will be
approximately 5% lower than calculated.
The difference in the damping resistor current values
during scan and flyback have to be externally
compensated in order to achieve a short settling time. For
that purpose a compensation resistor RCMP in series with
a zener diode is connected between pins OUTA and INA
(see Fig.4). The zener diode voltage value should be
equal to VP. The value of RCMP is calculated by:
Flyback supply
( V FB – V loss ( FB ) – V Z ) × R D1 × R CV1
R CMP = ----------------------------------------------------------------------------------------------------------( V FB – V loss ( FB ) – I coil ( peak ) × R coil ) × R M
The flyback voltage is determined by the flyback supply
voltage VFB. The principle of two supply voltages (class G)
allows to use an optimum supply voltage VP for scan and
an optimum flyback supply voltage VFB for flyback, thus
very high efficiency is achieved. The available flyback
output voltage across the coil is almost equal to VFB, due
to the absence of a coupling capacitor which is not
required in a bridge configuration. The very short rise and
fall times of the flyback switch are determined mainly by
the slew rate value of more than 300 V/µs.
where:
• Vloss(FB) is the voltage loss between pins VFB and OUTA
at flyback
• Rcoil is the deflection coil resistance
• VZ is the voltage of zener diode D4.
Protection
The output circuit contains protection circuits for:
• Too high die temperature
• Overvoltage of output A.
2002 Jan 21
4
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
TDA8359J
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VP
supply voltage
−
18
V
VFB
flyback supply voltage
−
68
V
Vn
DC voltage
−
68
V
pin OUTB
−
VP
V
pins INA, INB, GUARD and FEEDB
−0.5
VP
V
pin OUTA
In
note 1
DC current
pins OUTA and OUTB
during scan (p-p)
−
3.2
A
pins OUTA and OUTB
at flyback (peak); t ≤ 1.5 ms
−
±1.8
A
−20
+20
mA
current into any pin; pin voltage is
1.5 × VP; note 2
−
+200
mA
−
mA
pins INA, INB, GUARD and FEEDB
Ilu
latch-up current
current out of any pin; pin voltage is −200
−1.5 × VP; note 2
Ves
electrostatic handling voltage
machine model; note 3
−500
+500
V
human body model; note 4
−5000
+5000
V
Ptot
total power dissipation
−
10
W
Tstg
storage temperature
−55
+150
°C
Tamb
ambient temperature
−25
+85
°C
Tj
junction temperature
−
150
°C
note 5
Notes
1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.
2. At Tj(max).
3. Equivalent to 200 pF capacitance discharge through a 0 Ω resistor.
4. Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor.
5. Internally limited by thermal protection at Tj = 170 °C.
THERMAL CHARACTERISTICS
In accordance with IEC 60747-1.
SYMBOL
PARAMETER
Rth(j-c)
thermal resistance from junction to case
Rth(j-a)
thermal resistance from junction to ambient
2002 Jan 21
CONDITIONS
in free air
5
MAX.
UNIT
3
K/W
65
K/W
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
TDA8359J
CHARACTERISTICS
VP = 12 V; VFB = 45 V; fvert = 50 Hz; VI(bias) = 880 mV; Tamb = 25 °C; measured in test circuit of Fig.3; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VP
operating supply voltage
7.5
12
18
V
VFB
flyback supply voltage
note 1
2 × VP
45
66
V
Iq(P)(av)
average quiescent supply current
during scan
−
10
15
mA
Iq(P)
quiescent supply current
no signal; no load
−
45
75
mA
Iq(FB)(av)
average quiescent flyback supply
current
during scan
−
−
10
mA
−
1000
1500
mV
Inputs A and B
Vi(p-p)
input voltage (peak-to-peak value)
note 2
VI(bias)
input bias voltage
note 2
100
880
1600
mV
II(bias)
input bias current
source
−
25
35
µA
Io = 1.1 A
−
−
4.5
V
Io = 1.6 A
−
−
6.6
V
Io = −1.1 A
−
−
3.3
V
Io = −1.6 A
−
−
4.8
V
−
−
3.2
A
adjacent blocks
−
1
2
%
non adjacent blocks
−
1
3
%
VI(bias) = 200 mV
−
−
±15
mV
VI(bias) = 1 V
Outputs A and B
Vloss(1)
Vloss(2)
voltage loss first scan part
voltage loss second scan part
Io(p-p)
output current
(peak-to-peak value)
LE
linearity error
Voffset
offset voltage
note 3
note 4
Io(p-p) = 3.2 A; notes 5 and 6
across RM; Vi(dif) = 0 V
−
−
±20
mV
∆Voffset(T)
offset voltage variation with
temperature
across RM; Vi(dif) = 0 V
−
−
40
µV/K
VO
DC output voltage
Vi(dif) = 0 V
−
0.5 × VP −
Gv(ol)
open-loop voltage gain
notes 7 and 8
−
60
−
dB
f− 3dB(h)
high −3 dB cut-off frequency
open-loop
−
1
−
kHz
Gv
voltage gain
note 9
−
1
−
∆Gv(T)
voltage gain variation with the
temperature
−
−
10−4
K−1
PSRR
power supply rejection ratio
80
90
−
dB
2002 Jan 21
note 10
6
V
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
SYMBOL
PARAMETER
TDA8359J
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Flyback switch
Io(peak)
maximum (peak) output current
t ≤ 1.5 ms
Vloss(FB)
voltage loss at flyback
note 11
−
−
±1.8
A
Io = 1.1 A
−
7.5
8.5
V
Io = 1.6 A
−
8
9
V
Guard circuit
VO(grd)
guard output voltage
IO(grd) = 100 µA
5
6
7
V
VO(grd)(max)
allowable guard voltage
maximum leakage current
IL(max) = 10 µA
−
−
18
V
IO(grd)
output current
VO(grd) = 0 V; not active
−
−
10
µA
VO(grd) = 4.5 V; active
1
−
2.5
mA
Notes
1. To limit VOUTA to 68 V, VFB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA
and VFB at the first part of the flyback.
2. Allowable input range for both inputs: VI(bias) + Vi < 1600 mV and VI(bias) − Vi > 100 mV.
3. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTA, and
between pins OUTB and GND. Specified for Tj = 125 °C. The temperature coefficient for Vloss(1) is a positive value.
4. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTB, and
between pins OUTA and GND. Specified for Tj = 125 °C. The temperature coefficient for Vloss(2) is a positive value.
5. The linearity error is measured for a linear input signal without S-correction and is based on the ‘on screen’
measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time
parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists
of two successive parts. The voltage amplitudes are measured across RM, starting at k = 1 and ending at k = 10,
where Vk and Vk+1 are the measured voltages of two successive blocks. Vmin, Vmax and Vavg are the minimum,
maximum and average voltages respectively. The linearity errors are defined as:
Vk – Vk + 1
a) LE = -------------------------- × 100 % (adjacent blocks)
V avg
V max – V min
b) LE = ------------------------------- × 100 % (non adjacent blocks)
V avg
6. The linearity errors are specified for a minimum input voltage of 300 mV (p-p). Lower input voltages lead to voltage
dependent S-distortion in the input stage.
7.
V OUTA – V OUTB
G v ( ol ) = ------------------------------------------V FEEDB – V OUTB
8. Pin FEEDB not connected.
9.
V FEEDB – V OUTB
G v = ------------------------------------------V INA – V INB
10. VP(ripple) = 500 mV (RMS value); 50 Hz < fP(ripple) < 1 kHz; measured across RM.
11. This value specifies the internal voltage loss of the current path between pins VFB and OUTA.
2002 Jan 21
7
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
TDA8359J
APPLICATION INFORMATION
VP
handbook, full pagewidth
RGRD
4.7 kΩ
VFB
GUARD
VP
VFB
8
3
6
GUARD
CIRCUIT
Vi(p-p)
C1
100 nF
C2
100 nF
M5
D2
D3
VI(bias)
M2
0
D1
I I(bias)
7 OUTA
INA 1
RCV1
2.2 kΩ
(1%)
I i(dif)
M4
9
INPUT
AND
FEEDBACK
CIRCUIT
RL
3.2 Ω
2.7 kΩ
I I(bias)
CM
10 nF
M1
INB 2
4
RCV2
2.2 kΩ
(1%)
M3
Vi(p-p)
TDA8359J
VI(bias)
5
0
GND
Fig.3 Test diagram.
2002 Jan 21
FEEDB
RS
8
MGL864
OUTB
RM
0.5 Ω
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VP
VFB
3
6
GUARD
CIRCUIT
Vi(p-p)
C3
100 nF
M5
D2
VI(bias)
C4
100 nF
VFB = 30 V
C2
220 µF
(25 V)
D4
(14 V)
D3
RCMP
680 kΩ
M2
0
D1
7 OUTA
INA 1
C6
2.2 nF
RCV1
2.2 kΩ
(1%)
9
TV SIGNAL
PROCESSOR
M4
INB 2
C7
2.2 nF
9 FEEDB
INPUT
AND
FEEDBACK
CIRCUIT
RCV2
2.2 kΩ
(1%)
2.7 kΩ
0
deflection
coil
5 mH
6Ω
(W66ESF)
RM
0.5 Ω
M1
CD
47 nF
RD2
1.5 Ω
4 OUTB
M3
TDA8359J
Vi(p-p)
VI(bias)
RS
RD1
270 Ω
Philips Semiconductors
GUARD
8
C1
47 µF
(100 V)
Full bridge vertical deflection output circuit
in LVDMOS
ook, full pagewidth
2002 Jan 21
VP = 14 V
RGRD
12 kΩ
5
GND
MBL364
Product specification
Fig.4 Application diagram.
TDA8359J
fvert = 50 Hz; tFB = 640 µs; II(bias) = 400 µA; Ii(p-p) = 290 µA; Io(p-p) = 2.4 A.
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
TDA8359J
RM calculation
Supply voltage calculation
Most Philips brand TV signal processors have outputs in
the form of current. This current has to be converted to a
voltage by using resistors at the input of the TDA8359J
(RCV1 and RCV2). The differential voltage across these
resistors can be calculated by:
V i ( dif ) ( p – p ) = I i1 ( p – p ) × R CV1 – ( – I i2 ( p – p ) ) × R CV2
For calculating the minimum required supply voltage,
several specific application parameter values have to be
known. These parameters are the required maximum
(peak) deflection coil current Icoil(peak), the coil impedance
Rcoil and Lcoil, and the measuring resistance of RM. The
required maximum (peak) deflection coil current should
also include overscan.
For calculating the measuring resistor RM, use the
differential input voltage (Vi(dif)(p-p)). This voltage can also
be measured between pins INA and INB (see Fig.5). The
calculation for RM is:
The deflection coil resistance has to be multiplied by 1.2 in
order to take account of hot conditions.
Chapter “Characteristics” supplies values for voltage
losses of the vertical output stage. For the first part of the
scan, the voltage loss is given by Vloss(1). For the second
part of the scan, the voltage loss is given by Vloss(2).
V i ( dif ) ( p – p )
R M = --------------------------Io ( p – p )
The voltage drop across the deflection coil during scan is
determined by the coil impedance. For the first part of the
scan the inductive contribution and the ohmic contribution
to the total coil voltage drop are of opposite sign, while for
the second part of the scan the inductive part and the
ohmic part have the same sign.
Ii1(p-p)
handbook, halfpage
II(bias)
0
INA
C6
2.2 nF
For the vertical frequency the maximum frequency
occurring must be applied to the calculations.
1
The required power supply voltage VP for the first part of
the scan is given by:
RCV1
2.2 kΩ
V P ( 1 ) = I coil ( peak ) × ( R coil + R M )
– L coil × 2I coil ( peak ) × f vert ( max ) + V loss ( 1 )
TV SIGNAL
PROCESSOR
INB
C7
2.2 nF
The required power supply voltage VP for the second part
of the scan is given by:
2
RCV2
2.2 kΩ
Ii2(p-p)
V P ( 2 ) = I coil ( peak ) × ( R coil + R M )
+ L coil × 2I coil ( peak ) × f vert ( max ) + V loss ( 2 )
MBL366
The minimum required supply voltage VP shall be the
highest of the two values VP(1) and VP(2). Spread in supply
voltage and component values also has to be taken into
account.
II(bias)
0
Fig.5 Input Circuit
EXAMPLE
Measured or given values: II(bias) = 400 µA; Ii1(p-p) = Ii2(p-p)=
290 µA.
The differential input voltage will be:
V i ( dif ) ( p – p ) = 290µA × 2.2kΩ – ( – 290µA × 2.2kΩ ) = 1.27V
2002 Jan 21
10
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
Flyback supply voltage calculation
Table 2
If the flyback time is known, the required flyback supply
voltage can be calculated by the simplified formula:
Calculated values
SYMBOL
L coil
x = -------------------------R coil + R M
The flyback supply voltage calculated this way is
approximately 5% to 10% higher than required.
UNIT
V
7.8
0.02
0.000641
Ω
s
VFB
Psup
PL
30
8.91
V
W
3.74
W
Ptot
5.17
W
tvert
x
where:
VALUE
14
VP
RM + Rcoil (hot)
R coil + R M
V FB = I coil ( p –p ) × -------------------------– t FB ⁄ x
1–e
Heatsink calculation
The value of the heatsink can be calculated in a standard
way with a method based on average temperatures. The
required thermal resistance of the heatsink is determined
by the maximum die temperature of 150 °C. In general we
recommend to design for an average die temperature
not exceeding 130 °C.
Calculation of the power dissipation of the vertical
output stage
The IC total power dissipation is given by the formula:
Ptot = Psup − PL
The power to be supplied is given by the formula:
EXAMPLE
I coil ( peak )
P sup = V P × ----------------------- + V P × 0.015 [A] + 0.3 [W]
2
Measured or given values: Ptot = 6 W; Tamb(max) = 40 °C;
Tj = 120 °C; Rth(j-c) = 4 K/W; Rth(c-h) = 2 K/W.
In this formula 0.3 [W] represents the average value of the
losses in the flyback supply.
The required heatsink thermal resistance is given by:
T j – T amb
R th ( h – a ) = ----------------------- – ( R th ( j – c ) + R th ( c – h ) )
P tot
The average external load power dissipation in the
deflection coil and the measuring resistor is given by the
formula:
When we use the values given we find:
2
( I coil ( peak ) )
P L = -------------------------------- × ( R coil + R M )
3
120 – 40
R th ( h – a ) = ---------------------- – ( 4 + 2 ) = 7 K/W
6
The heatsink temperature will be:
Example
Table 1
TDA8359J
Th = Tamb + (Rth(h-a) × Ptot) = 40 + (7 × 6) = 82 °C
Application values
SYMBOL
Icoil(peak)
VALUE
UNIT
Icoil(p-p)
1.2
2.4
A
A
Lcoil
Rcoil
RM
5
6
0.6
mH
Ω
Ω
fvert
tFB
50
640
Hz
µs
2002 Jan 21
11
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
TDA8359J
INTERNAL PIN CONFIGURATION
PIN
1
SYMBOL
EQUIVALENT CIRCUIT
INA
1
300 Ω
MBL100
2
INB
2
300 Ω
MBL102
3
VP
4
OUTB
5
GND
6
VFB
7
OUTA
6
3
7
4
MGS805
2002 Jan 21
12
5
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
PIN
8
SYMBOL
TDA8359J
EQUIVALENT CIRCUIT
GUARD
300 Ω
8
MBL103
9
300 Ω
FEEDB
9
MBL101
2002 Jan 21
13
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
TDA8359J
PACKAGE OUTLINE
DBS9P: plastic DIL-bent-SIL power package; 9 leads (lead length 12/11 mm); exposed die pad
SOT523-1
q1
non-concave
x
Eh
Dh
D
D1
view B: mounting base side
P
A2
k
q2
B
E
q
L2
L3
L1
L
1
9
e1
Z
e
Q
w M
bp
0
5
scale
DIMENSIONS (mm are the original dimensions)
UNIT A2(2) bp
mm
c
D(1) D1(2) Dh E(1) Eh
2.7 0.80 0.58 13.2
2.3 0.65 0.48 12.8
10 mm
v M
c
e2
m
e
e1
e2
L
L1
L2
L3
m
6.2
14.7
3.0 12.4 11.4 6.7
3.5
3.5 2.54 1.27 5.08
5.8
14.3
2.0 11.0 10.0 5.5
4.5
3.7
2.8
k
P
Q
q
q1
q2
3.4 1.15 17.5
4.85 3.8
3.1 0.85 16.3
3.6
v
0.8
w
x
0.3 0.02
Z(1)
1.65
1.10
Notes
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
2. Plastic surface within circle area D1 may protrude 0.04 mm maximum.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
98-11-12
00-07-03
SOT523-1
2002 Jan 21
EUROPEAN
PROJECTION
14
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
TDA8359J
The total contact time of successive solder waves must not
exceed 5 seconds.
SOLDERING
Introduction to soldering through-hole mount
packages
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
This text gives a brief insight to wave, dip and manual
soldering. A more in-depth account of soldering ICs can be
found in our “Data Handbook IC26; Integrated Circuit
Packages” (document order number 9398 652 90011).
Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.
Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.
Soldering by dipping or by solder wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods
SOLDERING METHOD
PACKAGE
DIPPING
DBS, DIP, HDIP, SDIP, SIL
WAVE
suitable(1)
suitable
Note
1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
2002 Jan 21
15
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
TDA8359J
DATA SHEET STATUS
DATA SHEET STATUS(1)
PRODUCT
STATUS(2)
DEFINITIONS
Objective data
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Jan 21
16
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
NOTES
2002 Jan 21
17
TDA8359J
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
NOTES
2002 Jan 21
18
TDA8359J
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS
NOTES
2002 Jan 21
19
TDA8359J
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA74
© Koninklijke Philips Electronics N.V. 2002
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/25/02/pp20
Date of release: 2002
Jan 21
Document order number:
9397 750 08868